A multi-phase output clock circuit and method for high power management

Abstract

This invention provides a multi-phase output clock circuit and method for high-power power supply management. Flip-flop FF0 receives the clock signal CLK generated by the system's internal oscillator and divides CLK by two to obtain clock signal CLK1. Flip-flops FF1, FF2, and FF3 form a state machine structure unit, which divides CLK1 by six to output three phase-shifted clock signals. The clock input of flip-flop FF4 is connected to the clock signal CLK1N obtained from CLK1 via an inverter, and is used to output another phase-shifted clock signal. The generation of the multi-phase clock can be used as the operating clock for multiple parallel converters. In this form, each converter handles a relatively small current, reducing output ripple, power loss, and efficiency, while also lowering costs.

Description

Technical Field

[0001] This invention belongs to the field of power supply technology, specifically relating to a multi-phase output clock circuit and method for high-power power supply management. Background Technology

[0002] In high-power power management systems, a single converter often struggles to meet the demand for large load currents. Therefore, multiple converters connected in parallel are typically employed to satisfy this requirement, and this configuration also reduces thermal and current stress on the switching devices. However, if multiple converters are connected in single-phase parallel configuration (meaning the switching frequencies of the individual converters are in phase), the input and output current ripple will be relatively large, resulting in significant power losses due to the equivalent series resistance of the input capacitor and high switching losses in the power transistors, leading to relatively low power converter efficiency. Furthermore, the large input and output current ripple necessitates larger input capacitors and output inductors, increasing costs. Additionally, a relatively large inductance value is detrimental to improving transient response under load variations. Summary of the Invention

[0003] To address the problems existing in the prior art, the present invention provides a multi-phase output clock circuit and method for high-power power supply management, which realizes the output of a multi-phase clock circuit by inputting a single oscillator clock signal.

[0004] This invention is achieved through the following technical solution:

[0005] A multi-phase output clock circuit for high-power power supply management is characterized by comprising flip-flops FF0, FF1, FF2, FF3, and FF4.

[0006] The flip-flop FF0 is used to receive the clock signal CLK generated by the internal oscillator of the system, and to divide the clock signal CLK by two to obtain the clock signal CLK1; the flip-flops FF1, FF2 and FF3 form a state machine structure unit, which is used to divide the clock signal CLK1 by six to output three clock signals with different phases; the clock input terminal of the flip-flop FF4 is connected to the clock signal CLK1N obtained by CLK1 through an inverter, and is used to output another clock signal with different phases.

[0007] Furthermore, the trigger FF0 includes an input terminal D0 and an output terminal Q0;

[0008] The output terminal Q0 of the flip-flop FF0 is connected to the input terminal D0. The output terminal Q0 of the flip-flop FF0 is also connected to an inverter D1. The inverter D1 is connected to an inverter D2 and a state machine structure unit.

[0009] The inverter D2 is connected to the trigger FF4 and the state machine structure unit.

[0010] Furthermore, the inverter D1 outputs a clock signal CLK1, and the inverter D1 outputs a clock signal CLK1N;

[0011] The clock signal CLK1 is connected to the flip-flops FF1, FF2 and FF3 of the state machine structure unit respectively.

[0012] Furthermore, the state machine structure unit also includes NAND gate Y1 and NAND gate Y2;

[0013] The flip-flop FF1 includes an input terminal D1 and an output terminal Q1, the flip-flop FF2 includes an input terminal D2, an output terminal Q21 and an output terminal Q22, and the flip-flop FF3 includes an input terminal D3, an output terminal Q31 and an output terminal Q32.

[0014] The input terminal D1 of the flip-flop FF1 is connected to the clock signal CLK1N, and the output terminal Q1 is connected to one input terminal of the NAND gate Y1; the input terminal D2 of the flip-flop FF2 is connected to the output terminal of the NAND gate Y1, the output terminal Q21 is connected to one input terminal of the NAND gate Y2 and outputs a third misaligned clock signal, the output terminal Q22 is connected to the input terminal D3 of the flip-flop FF3, the output terminal Q31 of the flip-flop FF3 is connected to the other input terminal of the NAND gate Y2 and outputs a first misaligned clock signal, and the output terminal Q32 outputs a fourth misaligned clock signal; the output terminal of the NAND gate Y2 is connected to the other input terminal of the NAND gate Y1.

[0015] Furthermore, the first misaligned clock signal is CLK_0deg, the third misaligned clock signal is CLK_120deg, and the fourth misaligned clock signal is CLK_180deg.

[0016] Furthermore, the flip-flop FF4 includes an input terminal D4 and an output terminal Q4. The input terminal D4 is connected to the output terminal of the inverter D3, the input terminal of the inverter is connected to the output terminal Q1, and the output terminal Q4 outputs a second misaligned clock signal.

[0017] Furthermore, the second misaligned clock signal is CLK_90deg.

[0018] Furthermore, the triggers FF0, FF1, FF2, FF3 and FF4 are all D triggers.

[0019] A method for a multi-phase output clock for high-power power supply management includes the following steps:

[0020] When flip-flop FF0 receives the clock signal CLK, it divides the clock signal CLK by two to obtain the clock signal CLK1. The state machine structure unit composed of flip-flops FF1, FF2 and FF3 divides the clock signal CLK1 by six and outputs three clock signals with staggered phases respectively.

[0021] The clock control signal terminal of flip-flop FF4 is connected to the clock signal CLK1N. The signal input terminal D is connected to the output terminal Q1 of flip-flop FF1, and then an inverter is added to output another phase-shifted clock signal, thus completing the multi-phase output clock for power supply management.

[0022] Furthermore, when the state machine structure unit receives the clock signal CLK1, flip-flops FF1, FF2, and FF3 will be triggered at the rising edge of CLK1. At this time, the output Q1 of flip-flop FF1 changes to the state before triggering (CLK1N), the output Q21 of flip-flop FF2 changes to the state before triggering (AND gate Y1), and the output Q31 of flip-flop FF3 changes to the state before triggering (flip-flop FF2 output Q22). Ultimately, the output states will have eight possible states.

[0023] These eight states correspond to the outputs Q31, Q21, and Q1 of flip-flops FF3, FF2, and FF1, respectively: 000, 001, 010, 011, 100, 101, 110, and 111. These three outputs will cycle through the six states in the order of 010, 011, 001, 101, 100, and 110. The states 000 and 111 are invalid states. Normally, these two invalid states will not appear. If an invalid state is entered due to interference, it can enter the cycle through state S2, forming a circuit with self-starting capability. The output Q31 of flip-flop FF3 is used as the reference, the output Q21 of flip-flop FF2 is 120° away from the reference, and the output Q31 of flip-flop FF3 is 180° away from the reference.

[0024] Compared with the prior art, the present invention has the following beneficial technical effects:

[0025] This invention provides a multi-phase output clock circuit and method for high-power power supply management. Flip-flop FF0 receives the clock signal CLK generated by the system's internal oscillator and divides CLK by two to obtain clock signal CLK1. Flip-flops FF1, FF2, and FF3 form a state machine structure unit, which divides CLK1 by six to output three phase-shifted clock signals. The clock input of flip-flop FF4 is connected to the clock signal CLK1N obtained from CLK1 via an inverter, and is used to output another phase-shifted clock signal. The generation of the multi-phase clock can be used as the operating clock for multiple parallel converters. In this form, each converter handles a relatively small current, reducing output ripple, power loss, and efficiency, while also lowering costs. Attached Figure Description

[0026] Figure 1 This is a diagram of a multi-phase output clock circuit for high-power power supply management in a specific embodiment of the present invention;

[0027] Figure 2 This is a diagram of four phase-staggered clock signals in a specific embodiment of the present invention. Detailed Implementation

[0028] The present invention will be further described in detail below with reference to specific embodiments. These descriptions are for explanation purposes only and are not intended to limit the scope of the invention.

[0029] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0030] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0031] This invention provides a multi-phase output clock circuit for high-power power supply management, such as... Figure 1 As shown, it includes trigger FF0, trigger FF1, trigger FF2, trigger FF3 and trigger FF4;

[0032] The flip-flop FF0 is used to receive the clock signal CLK generated by the internal oscillator of the system, and to divide the clock signal CLK by two to obtain the clock signal CLK1; the flip-flops FF1, FF2 and FF3 form a state machine structure unit, which is used to divide the clock signal CLK1 by six to output three clock signals with different phases; the clock input terminal of the flip-flop FF4 is connected to the clock signal CLK1N obtained by CLK1 through an inverter, and is used to output another clock signal with different phases.

[0033] Preferably, the trigger FF0 includes an input terminal D0 and an output terminal Q0;

[0034] The output terminal Q0 of the flip-flop FF0 is connected to the input terminal D0. The output terminal Q0 of the flip-flop FF0 is also connected to an inverter D1. The inverter D1 is connected to an inverter D2 and a state machine structure unit.

[0035] The inverter D2 is connected to the trigger FF4 and the state machine structure unit.

[0036] Preferably, the inverter D1 outputs a clock signal CLK1, and the inverter D2 outputs a clock signal CLK1N.

[0037] The clock signal CLK1 is connected to the flip-flops FF1, FF2 and FF3 of the state machine structure unit respectively.

[0038] Furthermore, the state machine structure unit also includes NAND gate Y1 and NAND gate Y2;

[0039] The flip-flop FF1 includes an input terminal D1 and an output terminal Q1, the flip-flop FF2 includes an input terminal D2, an output terminal Q21 and an output terminal Q22, and the flip-flop FF3 includes an input terminal D3, an output terminal Q31 and an output terminal Q32.

[0040] The input terminal D1 of the flip-flop FF1 is connected to the clock signal CLK1N, and the output terminal Q1 is connected to one input terminal of the NAND gate Y1; the input terminal D2 of the flip-flop FF2 is connected to the output terminal of the NAND gate Y1, the output terminal Q21 is connected to one input terminal of the NAND gate Y2 and outputs a third misaligned clock signal, the output terminal Q22 is connected to the input terminal D3 of the flip-flop FF3, the output terminal Q31 of the flip-flop FF3 is connected to the other input terminal of the NAND gate Y2 and outputs a first misaligned clock signal, and the output terminal Q32 outputs a fourth misaligned clock signal; the output terminal of the NAND gate Y2 is connected to the other input terminal of the NAND gate Y1.

[0041] Specifically, the first misaligned clock signal is CLK_0deg, the third misaligned clock signal is CLK_120deg, and the fourth misaligned clock signal is CLK_180deg.

[0042] Preferably, the trigger FF4 includes an input terminal D4 and an output terminal Q4. The input terminal D4 is connected to the output terminal of the inverter D3, the input terminal of the inverter is connected to the output terminal Q1, and the output terminal Q4 outputs a second misaligned clock signal.

[0043] Specifically, the second misaligned clock signal is CLK_90deg.

[0044] Preferably, the triggers FF0, FF1, FF2, FF3 and FF4 are all D triggers.

[0045] This invention provides a method for a multi-phase output clock for high-power power supply management, comprising the following steps:

[0046] When flip-flop FF0 receives the clock signal CLK, it divides the clock signal CLK by two to obtain the clock signal CLK1. The state machine structure unit composed of flip-flops FF1, FF2 and FF3 divides the clock signal CLK1 by six and outputs three clock signals with staggered phases respectively.

[0047] The clock control signal terminal of flip-flop FF4 is connected to the clock signal CLK1N. The signal input terminal D is connected to the output terminal Q1 of flip-flop FF1, followed by the output of an inverter to output another phase-shifted clock signal, thus completing the multi-phase output clock for power supply management. Figure 2 As shown.

[0048] Specifically, the driving equation of the state machine structure unit is:

[0049]

[0050] The output equation is:

[0051]

[0052] The circuit state equation is:

[0053]

[0054] Where D1, D2, and D3 are the input terminals of flip-flops FF1, FF2, and FF3, respectively; CLK_0deg, CLK_120deg, and CLK_180deg are the out-of-phase clock signals at output; and Q3... n Q2 n Q1 n For the current state, the output of triggers FF3, FF2, and FF1 is Q3. n+1 Q2 n+1 Q1 n+1 This is the output of triggers FF3, FF2, and FF1 in the next state. The trigger condition is that there is a rising edge at the CLK terminal of the trigger.

[0055] State transition table 1:

[0056]

[0057] As shown in Table 1, when the state machine structure unit receives the clock signal CLK1, flip-flops FF1, FF2, and FF3 will be triggered when the rising edge of CLK1 arrives. At this time, the output Q1 of flip-flop FF1 becomes the state before triggering CLK1N, the output Q21 of flip-flop FF2 becomes the state before triggering NAND gate Y1, and the output Q31 of flip-flop FF3 becomes the output Q22 of flip-flop FF2 before triggering. The output states will eventually have eight states, which correspond to the outputs Q31, Q21, and Q1 of flip-flops F3, F2, and F1 as 000, 001, 010, 011, 100, 101, 110, and 111, respectively. These three outputs will cycle in the order of six states: 010, 011, 001, 101, 100, and 110. The states 000 and 111 are invalid states. Normally, these two invalid states will not appear. If an invalid state is entered due to interference, it can enter the cycle through state S2. Therefore, this circuit has self-starting capability. This implements a CLK frequency divider operation. The output Q31 of flip-flop FF3 is used as the reference, the output Q21 of flip-flop FF2 is 120° out of phase with the reference, and the output Q31 of flip-flop FF3 is 180° out of phase with the reference.

[0058] Analyze trigger FF4.

[0059] The trigger is triggered on the falling edge relative to CLK1.

[0060] Its driving equation:

[0061] D4=(Q1n )'

[0062] Equations of state:

[0063] Q4 n =D4=(Q1) n )'

[0064] From the above equation, Q4 n For Q1 n The result after inversion.

[0065] Output equation:

[0066] CLK_90deg=Q4 n

[0067] CLK_90° differs from the reference CLK_0° by 90°.

[0068] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-phase output clock circuit for high-power power supply management, characterized in that, This includes triggers FF0, FF1, FF2, FF3, and FF4; The flip-flop FF0 is used to receive the clock signal CLK generated by the internal oscillator of the system, and to divide the clock signal CLK by two to obtain the clock signal CLK1; the flip-flop FF1, flip-flop FF2 and flip-flop FF3 form a state machine structure unit, which is used to divide the clock signal CLK1 by six to output three clock signals with staggered phases. The clock input terminal of the flip-flop FF4 is connected to the clock signal CLK1N obtained by an inverter from CLK1, which is used to output another phase-off clock signal. The trigger FF0 includes an input terminal D0 and an output terminal Q0; The output terminal Q0 of the flip-flop FF0 is connected to the input terminal D0. The output terminal Q0 of the flip-flop FF0 is also connected to an inverter D1. The inverter D1 is connected to an inverter D2 and a state machine structure unit. The inverter D2 is connected to the trigger FF4 and the state machine structure unit respectively; The inverter D1 outputs a clock signal CLK1, and the inverter D1 outputs a clock signal CLK1N. The clock signal CLK1 is connected to the flip-flops FF1, FF2 and FF3 of the state machine structure unit respectively; The state machine structure unit also includes NAND gate Y1 and NAND gate Y2; The flip-flop FF1 includes an input terminal D1 and an output terminal Q1, the flip-flop FF2 includes an input terminal D2, an output terminal Q21 and an output terminal Q22, and the flip-flop FF3 includes an input terminal D3, an output terminal Q31 and an output terminal Q32. The input terminal D1 of the flip-flop FF1 is connected to the clock signal CLK1N, and the output terminal Q1 is connected to one input terminal of the NAND gate Y1; the input terminal D2 of the flip-flop FF2 is connected to the output terminal of the NAND gate Y1, the output terminal Q21 is connected to one input terminal of the NAND gate Y2 and outputs a third misaligned clock signal, the output terminal Q22 is connected to the input terminal D3 of the flip-flop FF3, the output terminal Q31 of the flip-flop FF3 is connected to the other input terminal of the NAND gate Y2 and outputs a first misaligned clock signal, and the output terminal Q32 outputs a fourth misaligned clock signal; the output terminal of the NAND gate Y2 is connected to the other input terminal of the NAND gate Y1.

2. The multi-phase output clock circuit for high-power power supply management according to claim 1, characterized in that, The first misaligned clock signal is CLK_0deg, the third misaligned clock signal is CLK_120deg, and the fourth misaligned clock signal is CLK_180deg.

3. The multi-phase output clock circuit for high-power power supply management according to claim 1, characterized in that, The flip-flop FF4 includes an input terminal D4 and an output terminal Q4. The input terminal D4 is connected to the output terminal of the inverter D3. The input terminal of the inverter is connected to the output terminal Q1. The output terminal Q4 outputs a second misaligned clock signal.

4. The multi-phase output clock circuit for high-power power supply management according to claim 3, characterized in that, The second misaligned clock signal is CLK_90deg.

5. The multi-phase output clock circuit for high-power power supply management according to claim 1, characterized in that, The triggers FF0, FF1, FF2, FF3 and FF4 are all D triggers.

6. A method for a multi-phase output clock for high-power power supply management, characterized in that, A multi-phase output clock circuit for high-power power supply management, based on any one of claims 1-5, includes the following steps: When flip-flop FF0 receives the clock signal CLK, it divides the clock signal CLK by two to obtain the clock signal CLK1. The state machine structure unit composed of flip-flops FF1, FF2 and FF3 divides the clock signal CLK1 by six and outputs three clock signals with staggered phases respectively. The clock control signal terminal of flip-flop FF4 is connected to the clock signal CLK1N. The signal input terminal D is connected to the output terminal Q1 of flip-flop FF1, and then an inverter is added to output another phase-shifted clock signal, thus completing the multi-phase output clock for power supply management.

7. The method for a multi-phase output clock for high-power power supply management according to claim 6, characterized in that, When the state machine structure unit receives the clock signal CLK1, flip-flops FF1, FF2, and FF3 will be triggered on the rising edge of CLK1. At this time, the output Q1 of flip-flop FF1 changes to the state before triggering (CLK1N), the output Q21 of flip-flop FF2 changes to the state before triggering (AND gate Y1), and the output Q31 of flip-flop FF3 changes to the state before triggering (Flip-flop FF2 output Q22). Ultimately, the output states will have eight possible states. These eight states correspond to the outputs Q31, Q21, and Q1 of flip-flops FF3, FF2, and FF1, respectively: 000, 001, 010, 011, 100, 101, 110, and 111. These three outputs will cycle through the six states in the order of 010, 011, 001, 101, 100, and 110. The states 000 and 111 are invalid states. Normally, these two invalid states will not appear. If an invalid state is entered due to interference, it can enter the cycle through state S2, forming a circuit with self-starting capability. The output Q31 of flip-flop FF3 is used as the reference, the output Q21 of flip-flop FF2 is 120° away from the reference, and the output Q31 of flip-flop FF3 is 180° away from the reference.

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