Superconducting anti-bypass attack encryption device and encryption method

Abstract

The present invention provides a superconducting encryption device and encryption method for resisting side-channel attacks. The superconducting encryption device for resisting side-channel attacks comprises: a byte substitution circuit, a row shift circuit, a column obfuscation circuit, a round key adding circuit and a clock control circuit. The clock control circuit is respectively connected to the byte substitution circuit, the row shift circuit, the column obfuscation circuit and the round key adding circuit, and is used to perform clock control on the byte substitution circuit, the row shift circuit, the column obfuscation circuit and the round key adding circuit. The present invention proposes a design of a superconducting encryption circuit for resisting side-channel attacks, and uses phase transmission information to solve the problem that the existing CMOS encryption circuit cannot well realize resistance to side-channel attacks.

Description

Technical Field

[0001] The invention belongs to the technical field of superconducting encryption, and relates to an encryption method, in particular to a superconducting anti-side channel attack encryption device and an encryption method. Background Art

[0002] AES (Advanced Encryption Standard) is a symmetric key encryption algorithm and one of the most popular algorithms in the world. It has good security and practicality. The encryption circuit designed by the traditional CMOS (Complementary Metal Oxide Semiconductor) circuit has certain defects in resisting side-channel attacks, and it is necessary to design a unique security circuit to protect the security of the entire encryption circuit.

[0003] Superconducting single flux quantum technology is a technology that can be used to design superconducting circuits. Compared with traditional CMOS circuits, superconducting circuits have extremely high speed and circuit security. However, the research on encryption circuits based on superconducting circuits that resist side-channel attacks is still blank in the existing technology.

[0004] The characteristic of a bypass attack is that it can bypass attacks on encryption algorithms and directly use information leaked by the encryption circuit itself to crack the encryption. Figure 1 As shown in the figure, the reason why CMOS encryption circuits are vulnerable to side-channel attacks is that the electromagnetic radiation and circuit power consumption of the CMOS encryption circuit itself will leak information about the CMOS encryption circuit. Combined with the physical properties of the semiconductor materials of the CMOS circuit (for example, there is power consumption radiation when the CMOS circuit gate is flipped), statistical analysis theory can be used to obtain the data processed by the circuit, and then bypass attacks can be carried out on the CMOS circuit.

[0005] Therefore, how to provide a superconducting encryption device and encryption method that are resistant to side channel attacks to solve the defects of the prior art that cannot provide a superconducting encryption circuit solution that is resistant to side channel attacks has become a technical problem that needs to be urgently solved by technical personnel in this field. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a superconducting encryption device and encryption method that are resistant to side channel attacks, so as to solve the problem that the prior art cannot provide a superconducting encryption circuit solution that is resistant to side channel attacks.

[0007] To achieve the above-mentioned purpose and other related purposes, the present invention provides a superconducting anti-side channel attack encryption device on one hand, and the superconducting anti-side channel attack encryption device includes: a byte substitution circuit, which is provided with a data input end, receives the data to be encrypted through the data input end, and performs a byte substitution operation on the data to be encrypted to generate a byte substitution result; a row shift circuit, which is connected to the byte substitution circuit, is used to receive the byte substitution result, and performs a row shift operation on the byte substitution result to generate a row shift result; a column obfuscation circuit, which is connected to the row shift circuit, is used to receive the row shift result, and performs a column obfuscation operation on the row shift result to generate a column obfuscation result; a round key addition circuit, which is connected to the column obfuscation circuit, is used to receive the column obfuscation result, and performs a round key addition operation on the column obfuscation result to generate an output signal; a clock control circuit, which is respectively connected to the byte substitution circuit, the row shift circuit, the column obfuscation circuit and the round key addition circuit, is used to perform clock control on the byte substitution circuit, the row shift circuit, the column obfuscation circuit and the round key addition circuit.

[0008] In one embodiment of the present invention, the clock control circuit is provided with a main clock input terminal, and the main clock input terminal is used to receive a main clock signal, and after delay adjustment based on the main clock signal, clock control is performed on the byte substitution circuit, the row shift circuit, the column confusion circuit and the round key addition circuit.

[0009] In one embodiment of the present invention, the clock control circuit performs delay adjustment based on the main clock signal to generate a first clock control signal, and the first clock control signal is used to perform clock control on the byte substitution circuit.

[0010] In one embodiment of the present invention, the time when the to-be-encrypted data arrives at the byte substitution circuit is earlier than the time when the first clock control signal arrives at the byte substitution circuit.

[0011] In one embodiment of the present invention, the time taken for the encrypted data to reach the byte substitution circuit is less than the control reference time; the control reference time refers to the sum of the time taken for the main clock signal to reach the clock control circuit, the time taken for the first clock control signal to reach the byte substitution circuit, and a preset delay time.

[0012] In one embodiment of the present invention, the clock control circuit performs delay adjustment based on the main clock signal to generate a second clock control signal, and the second clock control signal is used to perform clock control on the row shift circuit.

[0013] In an embodiment of the present invention, the clock control circuit performs delay adjustment based on the main clock signal to generate a third clock control signal, and the third clock control signal is used to perform clock control on the column confusion circuit.

[0014] In one embodiment of the present invention, the clock control circuit performs delay adjustment based on the main clock signal to generate a fourth clock control signal, and the fourth clock control signal is used to perform clock control on the round key adding circuit.

[0015] To achieve the above-mentioned purpose and other related purposes, the present invention provides a superconducting anti-side channel attack encryption method on the other hand, which includes: clock control of byte substitution operation, row shift operation, column confusion operation and round key addition operation; the clock control includes: generating a first clock control signal for controlling the byte substitution operation, generating a second clock control signal for controlling the row shift operation, generating a third clock control signal for controlling the column confusion operation, and generating a fourth clock control signal for controlling the round key addition operation; receiving data to be encrypted, and performing a byte substitution operation on the data to be encrypted based on the first clock control signal to generate a byte substitution result; performing a row shift operation on the byte substitution result based on the second clock control signal to generate a row shift result; performing a column confusion operation on the row shift result based on the third clock control signal to generate a column confusion result; performing a round key addition operation on the column confusion result based on the fourth clock control signal to generate an output signal.

[0016] In one embodiment of the present invention, the steps of receiving the data to be encrypted and performing byte substitution operation on the data to be encrypted based on the first clock control signal to generate a byte substitution result include: receiving the data to be encrypted to prepare the data before the first clock control signal arrives; when the control reference time is met, obtaining the first clock control signal, and performing byte substitution operation on the data to be encrypted based on the first clock control signal.

[0017] As described above, the superconducting anti-side channel attack encryption device and encryption method described in the present invention have the following beneficial effects:

[0018] The present invention proposes a design method for a superconducting encryption circuit that resists side-channel attacks. The clock control circuit controls the byte substitution circuit, the row shift circuit, the column confusion circuit, and the round key addition circuit. The superconducting unit used is a Josephson junction, so as to realize the use of phase to transmit information, and solve the problem that the existing CMOS encryption circuit cannot well realize the resistance to side-channel attacks. The superconducting encryption circuit is composed of basic superconducting devices, and can realize the resistance to side-channel attacks under the existing process, thereby reducing the difficulty of process development. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The figure shows the principle diagram of the bypass attack on the CMOS circuit in the prior art.

[0020] Figure 2 Shown is a structural principle diagram of a superconducting anti-side channel attack encryption device in one embodiment of the present invention.

[0021] Figure 3 Shown is a clock control principle diagram of a superconducting anti-side channel attack encryption device in one embodiment of the present invention.

[0022] Figure 4 Shown is a principle flow chart of a superconducting anti-side channel attack encryption method in one embodiment of the present invention.

[0023] Figure 5 Shown is a byte substitution flow chart of a superconducting anti-side channel attack encryption method in one embodiment of the present invention.

[0024] Component number description

[0025] 1 Superconducting anti-side channel attack encryption device

[0026] 11 Byte Substitution Circuit

[0027] 12 row shift circuit

[0028] 13-column garbled circuit

[0029] 14 rounds of secret key plus circuit

[0030] 15 Clock control circuit

[0031] Steps S41 to S45

[0032] Steps S421 to S422 DETAILED DESCRIPTION

[0033] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0034] It should be noted that the illustrations provided in the following embodiments are only used to illustrate the basic concept of the present invention in a schematic manner, and thus the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0035] The superconducting encryption device and encryption method for resisting side channel attacks of the present invention propose a design of a superconducting encryption circuit for resisting side channel attacks, and solve the problem that the existing CMOS encryption circuit cannot well resist side channel attacks by using phase transmission information.

[0036] The following will be combined Figures 1 to 5 The principles and implementation methods of a superconducting anti-side channel attack encryption device and encryption method of this embodiment are explained in detail so that those skilled in the art can understand the superconducting anti-side channel attack encryption device and encryption method of this embodiment without creative work.

[0037] See also Figure 2 , which is a schematic diagram of the structure of a superconducting anti-side-channel attack encryption device in one embodiment of the present invention. Figure 2 As shown, the superconducting anti-side channel attack encryption device 1 described in the present invention includes: a byte substitution circuit 11, a row shift circuit 12, a column confusion circuit 13, a round key addition circuit 14 and a clock control circuit 15.

[0038] The byte substitution circuit 11 is provided with a data input terminal, receives the data to be encrypted through the data input terminal, performs a byte substitution operation on the data to be encrypted, and generates a byte substitution result.

[0039] The row shift circuit 12 is connected to the byte substitution circuit 11, and is used for receiving the byte substitution result and performing a row shift operation on the byte substitution result to generate a row shift result.

[0040] The column obfuscation circuit 13 is connected to the row shift circuit 12, and is used for receiving the row shift result and performing a column obfuscation operation on the row shift result to generate a column obfuscation result.

[0041] The round key addition circuit 14 is connected to the column obfuscation circuit 13, and is used for receiving the column obfuscation result and performing a round key addition operation on the column obfuscation result to generate an output signal.

[0042] The clock control circuit 15 is respectively connected to the byte substitution circuit 11, the row shift circuit 12, the column obfuscation circuit 13 and the round key addition circuit 14, and is used to perform clock control on the byte substitution circuit 11, the row shift circuit 12, the column obfuscation circuit 13 and the round key addition circuit 14.

[0043] See also Figure 3 , which is a clock control principle diagram of a superconducting anti-side-channel attack encryption device of the present invention in one embodiment. Figure 3 As shown, the clock control circuit 15 is provided with a main clock input terminal, and the main clock input terminal is used to receive a main clock signal clk, and after delay adjustment based on the main clock signal clk, the clock of the byte substitution circuit 11, the row shift circuit 12, the column confusion circuit 13 and the round key addition circuit 14 is controlled.

[0044] The main clock signal clk reaches the clock control circuit 15 after a wiring delay of t100. The clock control circuit 15 performs a delay of tdelay1 based on the main clock signal clk, adjusts and generates a first clock control signal, and the first clock control signal reaches the byte replacement circuit 11 after a wiring delay of t101, and performs clock control on the byte replacement circuit 11.

[0045] The clock control circuit 15 performs a delay of tdelay2 based on the main clock signal clk to adjust and generate a second clock control signal. The second clock control signal reaches the row shift circuit 12 after a wiring delay of t102, and performs clock control on the row shift circuit 12.

[0046] The clock control circuit 15 performs a delay of tdelay3 based on the main clock signal clk to adjust and generate a third clock control signal. The third clock control signal reaches the column confusion circuit 13 after a wiring delay of t103, and performs clock control on the column confusion circuit 13.

[0047] The clock control circuit 15 performs a delay of tdelay4 based on the main clock signal clk, adjusts and generates a fourth clock control signal, and the fourth clock control signal reaches the round key adding circuit 14 after a wiring delay of t104, and performs clock control on the round key adding circuit 14.

[0048] In one embodiment, the time when the to-be-encrypted data arrives at the byte substitution circuit is earlier than the time when the first clock control signal arrives at the byte substitution circuit.

[0049] Specifically, the time taken for the encrypted data to reach the byte replacement circuit is less than the control reference time; the control reference time refers to the sum of the time taken for the main clock signal to reach the clock control circuit, the time taken for the first clock control signal to reach the byte replacement circuit, and a preset delay time.

[0050] In actual applications, the time taken by the master clock signal to reach the clock control circuit is the wiring delay t100, the time taken by the first clock control signal to reach the byte substitution circuit is the wiring delay t101, the preset delay time is tsfqdelay, and the time taken by the encrypted data to reach the byte substitution circuit is the wiring delay t105. Due to superconducting process limitations, the time when the encrypted data in the superconducting encryption circuit reaches the data input terminal of the byte substitution circuit should be at least tsfqdelay, i.e., t105, earlier than the time when the first clock control signal reaches the clock input terminal of the byte substitution circuit. <t100+tsfqdelay+t101。

[0051] The working principle of the superconducting anti-side channel attack encryption device is as follows:

[0052] (1) The data input terminal Din receives the data signal to be encrypted, and the data signal to be encrypted is transmitted to the input port of the byte substitution circuit 11, and waits for the signal of the input terminal clk of the clock control circuit 15 to arrive.

[0053] (2) The clock control circuit 15 receives the main clock signal clk, and after different delay adjustments, it is output from the first clock output end of the clock control circuit 15 to the clock input end of the byte substitution circuit 11 through the wiring delay t101, and is output from the second clock output end of the clock control circuit 15 to the clock input end of the row shift circuit 12 through the wiring delay t102, and is output from the output end of the clock control circuit 15 to the clock input end of the column confusion circuit 13 through the wiring delay t103, and is output from the output end of the clock control circuit 15 to the clock input end of the round key addition circuit 14 through the wiring delay t104.

[0054] (3) After the clock input of the byte substitution circuit 11 receives the first clock control signal, the byte substitution circuit 11 starts to perform the byte substitution operation. The byte substitution result generated at the output of the byte substitution circuit 11 reaches the data input of the row shift circuit 12 after a wiring delay of t106. After the clock input of the row shift circuit 12 receives the second clock control signal, the row shift operation starts. The row shift result at the output of the row shift circuit 12 reaches the data input of the column obfuscation circuit 13 after a wiring delay of t107. After the clock input of the column obfuscation circuit 13 receives the third clock control signal, the column obfuscation operation starts. The column obfuscation result at the output of the column obfuscation circuit 13 reaches the data input of the round key addition circuit 14 after a wiring delay of t108. ​​After the clock input of the round key addition circuit 14 receives the fourth clock control signal, the round key addition operation starts. The output port of the round key addition circuit 14 outputs a signal. The output signal reaches the output end Dout of the superconducting anti-bypass attack encryption device after a wiring delay of t109. Therefore, before performing operations, the byte substitution circuit 11, the row shift circuit 12, the column obfuscation circuit 13 and the round key addition circuit 14 first prepare the data to be operated at the input end, and then receive the corresponding clock control signal to realize the clock control signal output by the clock control circuit 15 as the start mark for the operation of each circuit.

[0055] See also Figure 4 , which is a principle flow chart of the superconducting anti-side channel attack encryption method of the present invention in one embodiment. Figure 4 As shown, the superconducting anti-side channel attack encryption method specifically includes the following steps:

[0056] S41, clock control is performed on the byte substitution operation, the row shift operation, the column confusion operation and the round key addition operation; the clock control includes: generating a first clock control signal for controlling the byte substitution operation, generating a second clock control signal for controlling the row shift operation, generating a third clock control signal for controlling the column confusion operation, and generating a fourth clock control signal for controlling the round key addition operation.

[0057] S42, receiving data to be encrypted, and performing a byte substitution operation on the data to be encrypted based on the first clock control signal to generate a byte substitution result.

[0058] See also Figure 5 , which is a byte substitution flow chart of the superconducting anti-side channel attack encryption method of the present invention in one embodiment. Figure 5 As shown, S42 includes the following steps:

[0059] S421, receiving data to be encrypted, so as to prepare the data before the first clock control signal arrives.

[0060] S422: When the control reference time is met, obtain the first clock control signal, and perform a byte substitution operation on the data to be encrypted based on the first clock control signal.

[0061] In one embodiment, the control reference time refers to the sum of the time taken by the main clock signal to reach the clock control circuit, the time taken by the first clock control signal to reach the byte substitution circuit, and a preset delay time. Meeting the control reference time means that the time taken by the encrypted data to reach the byte substitution circuit is less than the control reference time.

[0062] S43: Perform a row shift operation on the byte substitution result based on the second clock control signal to generate a row shift result.

[0063] S44, performing a column confusion operation on the row shift result based on the third clock control signal to generate a column confusion result.

[0064] S45, performing a round key addition operation on the column obfuscation result based on the fourth clock control signal to generate an output signal.

[0065] The protection scope of the superconducting anti-side channel attack encryption method described in the present invention is not limited to the execution order of the steps listed in this embodiment. All solutions implemented by adding, reducing or replacing steps in the prior art based on the principles of the present invention are included in the protection scope of the present invention.

[0066] The principle of the superconducting anti-side attack encryption device described in the present invention corresponds one-to-one to the superconducting anti-side attack encryption method described in the present invention. The superconducting anti-side attack encryption device described in the present invention can implement the superconducting anti-side attack encryption method described in the present invention, but the implementation device of the superconducting anti-side attack encryption method described in the present invention includes but is not limited to the structure of the superconducting anti-side attack encryption device listed in this embodiment. All structural deformations and replacements of the prior art made according to the principles of the present invention are included in the protection scope of the present invention.

[0067] In the prior art, CMOS circuits have a weak ability to resist side-channel attacks when facing side-channel attacks. There are many forms of side-channel attacks. Common side-channel attacks include time attacks, power consumption attacks, radio frequency attacks, etc. The commonly used attack method for attacking circuits is DPA (Differential Power Analysis) attack. The characteristic of DPA attack is to use an oscilloscope to detect the energy consumption of electronic devices to obtain the behavior trajectory of electronic devices, and the encryption key can be reproduced by analyzing and comparing the energy trajectory. DPA attack reuses a large amount of data to collect relevant power consumption data, and obtains the corresponding secret key through statistical analysis of the energy traces of encryption and decryption of a large amount of different data. DPA attack requires five steps. The first step is to select a certain intermediate value of the executed algorithm, the second step is to measure the energy consumption, the third step is to calculate the assumed intermediate value, the fourth step is to map the intermediate value to the energy consumption value, and the fifth step is to compare the assumed energy consumption value and the energy trace. Combined with the five steps of DPA attack, the analysis of CMOS circuits and the superconducting anti-side-channel attack encryption device (i.e., superconducting encryption circuit) of the present invention is as follows:

[0068] The first step in a DPA attack is to select an intermediate value for executing the algorithm. In this process, the values ​​of the variables in the algorithm need to be determined. In CMOS execution, the non-constant f(k, c) determined by the ciphertext and the secret key is used, where k represents the encryption key and c represents the ciphertext; this step in the superconducting encryption circuit can be determined in a similar way.

[0069] The second step is to measure the energy consumption. In CMOS, a computer is used to send plaintext data to the encryption chip, and the power consumption of the encryption chip during the encryption process is collected through an oscilloscope to obtain the corresponding energy trace T matrix; in superconducting encryption circuits, it is difficult to directly collect the power consumption of the corresponding encryption chip, because the energy trace needs to record the energy trace of each step of the encryption process, and finally combine it into an energy trace matrix. The value of each step of the energy trace in the superconducting encryption circuit is much smaller than that in CMOS, so a more precise measurement tool is needed.

[0070] The third step is to calculate the assumed intermediate value. In CMOS, the corresponding intermediate value is guessed by the corresponding function f(k, d), and the required key matrix is ​​measured by different key guesses, and finally combined into the energy matrix V. In this process of the superconducting encryption circuit, the energy trace obtained in the second step is difficult to calculate, and more and more accurate energy traces need to be measured to guess the corresponding matrix.

[0071] The fourth step is to map the intermediate values ​​to energy consumption values. This part requires converting the intermediate value matrix V into the corresponding energy consumption matrix H. In CMOS, the Hamming distance model or the Hamming weight model is usually used for conversion. In superconducting circuits, the energy consumed by the 01 flip and 10 flip in superconducting circuits is different from that in CMOS circuits, so the Hamming model needs to be redesigned. In the process of redesign, it is necessary to measure the different energy values ​​consumed by the flips of superconducting encryption circuits under different circumstances. Compared with CMOS, the energy values ​​consumed by superconducting circuits under different circumstances are much smaller, so the difficulty of redesigning the Hamming weight model increases.

[0072] The fifth step is to compare the assumed energy consumption value and the energy trace. This part requires analyzing the measured energy matrix T and the guessed energy matrix H, and performing a matching analysis to infer the specific bits corresponding to the secret key. In this process, the advantage of the superconducting encryption circuit is that the model of the superconducting circuit is different from the existing CMOS model, and a new model needs to be reset. The energy trace of the superconducting encryption circuit is much smaller than that of CMOS, so it is difficult to measure and establish a new model, which requires a more sophisticated design, increasing the difficulty of differential power consumption analysis.

[0073] When attacking traditional CMOS encryption circuits, the main attacks are on the byte substitution and round key addition parts of the circuit. The row shift and column confusion parts only involve byte shift operations, so they are not suitable for power consumption attacks. Differential power analysis requires measuring the power consumption of CMOS itself, which can be done using filters. The power consumption calculation formula for CMOS circuits is power consumption = static power consumption + dynamic power consumption + leakage power consumption. The power consumption value of CMOS circuits is high, and it is easy to conduct bypass attacks through DPA attacks. The power consumption calculation formula for the Josephson junction used in superconducting circuits is power consumption = dynamic power consumption + extremely low static power consumption. The Josephson junction has no leakage power consumption, and the overall power consumption is very low. It is difficult to attack with DPA attacks, so it has the characteristics of resisting bypass attacks.

[0074] In terms of anti-electromagnetic radiation attacks, CMOS circuits can easily carry out electromagnetic radiation attacks through electromagnetic radiation generated by leakage power consumption and power consumption generated by MOS tube flipping during dynamic power consumption. The working environment of superconducting encryption circuits is a low-temperature environment. General electromagnetic radiation measurement devices cannot measure in low-temperature environments. At the same time, superconducting encryption circuits do not leak power consumption. Low-temperature electromagnetic radiation measurement devices require extremely high precision to capture the power consumption generated when a single Josephson junction flips. Therefore, superconducting encryption circuits can resist electromagnetic radiation attacks very well. Therefore, the advantages of the present invention are: first, the byte rotation and round key addition parts use Josephson junctions, the total power consumption is very low, and the power consumption generated when the Josephson junction flips is difficult to capture; second, the low-temperature working environment makes electromagnetic radiation difficult to measure. In summary, the above two points make the present invention have better anti-bypass attack characteristics.

[0075] In summary, the superconducting anti-side-channel attack encryption device and encryption method of the present invention proposes a design method for a superconducting encryption circuit that resists side-channel attacks, and the clock control circuit is used to control the byte substitution circuit, the row shift circuit, the column confusion circuit and the round key addition circuit. The superconducting unit used is a Josephson junction, so as to realize the use of phase transmission information, and solve the problem that the existing CMOS encryption circuit cannot well realize the resistance to side-channel attacks. The superconducting encryption circuit is composed of basic superconducting devices, and can realize the resistance to side-channel attacks under the existing process, thereby reducing the difficulty of process development. The present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0076] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A superconducting anti-side channel attack encryption device, characterized in that: The superconducting anti-side channel attack encryption device comprises: The byte substitution circuit is provided with a data input terminal, receives the data to be encrypted through the data input terminal, performs a byte substitution operation on the data to be encrypted, and generates a byte substitution result; a row shift circuit, connected to the byte substitution circuit, for receiving the byte substitution result and performing a row shift operation on the byte substitution result to generate a row shift result; a column obfuscation circuit, connected to the row shift circuit, configured to receive the row shift result, and perform a column obfuscation operation on the row shift result to generate a column obfuscation result; a round key addition circuit, connected to the column obfuscation circuit, configured to receive the column obfuscation result, perform a round key addition operation on the column obfuscation result, and generate an output signal; A clock control circuit is respectively connected to the byte substitution circuit, the row shift circuit, the column obfuscation circuit and the round key addition circuit, and is used to perform clock control on the byte substitution circuit, the row shift circuit, the column obfuscation circuit and the round key addition circuit.

2. The superconducting anti-side channel attack encryption device according to claim 1, characterized in that: The clock control circuit is provided with a main clock input end, and the main clock input end is used to receive a main clock signal, and after delay adjustment based on the main clock signal, clock control is performed on the byte substitution circuit, the row shift circuit, the column confusion circuit and the round key addition circuit.

3. The superconducting anti-side channel attack encryption device according to claim 2 is characterized in that: The clock control circuit performs delay adjustment based on the main clock signal to generate a first clock control signal, and the first clock control signal is used to perform clock control on the byte substitution circuit.

4. The superconducting anti-side channel attack encryption device according to claim 3 is characterized in that: The time when the to-be-encrypted data arrives at the byte substitution circuit is earlier than the time when the first clock control signal arrives at the byte substitution circuit.

5. The superconducting anti-side channel attack encryption device according to claim 4 is characterized in that: The time taken for the encrypted data to reach the byte replacement circuit is less than the control reference time; the control reference time refers to the sum of the time taken for the main clock signal to reach the clock control circuit, the time taken for the first clock control signal to reach the byte replacement circuit, and a preset delay time.

6. The superconducting anti-side channel attack encryption device according to claim 2, characterized in that: The clock control circuit performs delay adjustment based on the main clock signal to generate a second clock control signal, and the second clock control signal is used to perform clock control on the row shift circuit.

7. The superconducting anti-side channel attack encryption device according to claim 2, characterized in that: The clock control circuit performs delay adjustment based on the main clock signal to generate a third clock control signal, and the third clock control signal is used to perform clock control on the column confusion circuit.

8. The superconducting anti-side channel attack encryption device according to claim 2, characterized in that: The clock control circuit performs delay adjustment based on the main clock signal to generate a fourth clock control signal, and the fourth clock control signal is used to perform clock control on the round key adding circuit.

9. A superconducting anti-side channel attack encryption method, characterized in that: The superconducting anti-side channel attack encryption method comprises: Performing clock control on a byte substitution operation, a row shift operation, a column obfuscation operation, and a round key addition operation; the clock control comprises: generating a first clock control signal for controlling the byte substitution operation, generating a second clock control signal for controlling the row shift operation, generating a third clock control signal for controlling the column obfuscation operation, and generating a fourth clock control signal for controlling the round key addition operation; receiving data to be encrypted, and performing a byte substitution operation on the data to be encrypted based on the first clock control signal to generate a byte substitution result; Performing a row shift operation on the byte substitution result based on the second clock control signal to generate a row shift result; Performing a column confusion operation on the row shift result based on the third clock control signal to generate a column confusion result; A round key addition operation is performed on the column obfuscation result based on the fourth clock control signal to generate an output signal.

10. The superconducting anti-side channel attack encryption method according to claim 9, characterized in that: The step of receiving the data to be encrypted, and performing a byte substitution operation on the data to be encrypted based on the first clock control signal to generate a byte substitution result includes: receiving data to be encrypted so as to prepare the data before the first clock control signal arrives; When the control reference time is met, the first clock control signal is acquired, and a byte substitution operation is performed on the data to be encrypted based on the first clock control signal.

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