A phase change memory operation method, phase change memory and memory system

Abstract

The embodiment of the present invention provides an operation method of a phase change memory, a phase change memory and a memory system. The method includes: applying a first voltage to a selected word line coupled to a selected phase change memory cell in the phase change memory, and applying a second voltage to a selected bit line coupled to the selected phase change memory cell; performing a reset operation on the selected phase change memory cell based on a reset current pulse; the first voltage includes a minimum voltage value, a maximum voltage value and an intermediate voltage value; the minimum voltage value can turn on a selector of a selected phase change memory cell whose threshold voltage is in a first distribution; the maximum voltage value can turn on a selector of a selected phase change memory cell whose threshold voltage is in a second distribution; the intermediate voltage value is used to reduce the current flowing through the selected phase change memory cell when the first voltage applied to the selected word line rises from the minimum voltage value to the maximum voltage value; the first distribution and the second distribution constitute the threshold voltage distribution of the phase change memory cell.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to an operating method of a phase change memory, a phase change memory and a memory system. Background Art

[0002] Phase change memory is a memory element used to store information by using the conductivity or impedance difference between the crystalline and amorphous states of a specific phase change material. When setting the operation of the phase change material of the phase change memory to switch between the crystalline and amorphous states, different pulses can be used to control the heating of the phase change material. At present, the operating method used generates a relatively large surge current, which has a relatively serious impact on the life of the phase change memory. Summary of the invention

[0003] In view of this, the main purpose of the present invention is to provide a phase change memory operation method, a phase change memory and a memory system. By setting the voltage applied to the word line coupled to the phase change memory unit in a step-up form, the peak value of the inrush current introduced into the phase change memory unit due to the voltage mutation during the process of the voltage rising to the maximum voltage value in a short time is reduced, so as to reduce the damage to the phase change memory unit, thereby improving the life of the phase change memory unit.

[0004] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0005] In a first aspect, an embodiment of the present invention provides an operating method of a phase change memory, wherein the phase change memory includes a memory array, wherein the memory array includes a plurality of memory array blocks; each memory array block includes a plurality of phase change memory cells connected between word lines and bit lines; the operating method includes:

[0006] Applying a first voltage to a selected word line coupled to a selected phase change memory cell, and applying a second voltage to a selected bit line coupled to the selected phase change memory cell;

[0007] When a selector included in the selected phase-change memory cell is turned on based on the first voltage and the second voltage, a reset operation is performed on the selected phase-change memory cell based on a reset current pulse;

[0008] Wherein, the first voltage includes a minimum voltage value, a maximum voltage value and an intermediate voltage value between the maximum voltage value and the minimum voltage value; under the action of the minimum voltage value and the second voltage, the selector included in the selected phase change memory unit whose threshold voltage is in the first distribution can be turned on; under the action of the maximum voltage value and the second voltage, the selector included in the selected phase change memory unit whose threshold voltage is in the second distribution can be turned on; the intermediate voltage value is used to reduce the current flowing through the selected phase change memory unit when the first voltage applied by the selected word line rises from the minimum voltage value to the maximum voltage value; the first distribution and the second distribution constitute the threshold voltage distribution of the phase change memory unit contained in the phase change memory.

[0009] In the above solution, the intermediate voltage value includes one or more.

[0010] In the above solution, when the intermediate voltage value includes multiple intermediate voltage values, the multiple intermediate voltage values ​​increase in equal steps.

[0011] In the above solution, the number of the intermediate voltage values ​​is not greater than a preset threshold.

[0012] In the above solution, the first voltage is a positive voltage; and the second voltage is a negative voltage.

[0013] In the above solution, the first voltage is applied before the second voltage.

[0014] In the above scheme, the operation method further includes:

[0015] When the first voltage does not reach the minimum voltage value, the voltage on the selected bit line is maintained at a first low voltage until the first voltage reaches the minimum voltage value, and then the second voltage starts to be applied to the selected bit line.

[0016] In the above solution, the reset current pulse is controlled by a current mirror coupled to the selected bit line.

[0017] In the above scheme, the operation method further includes:

[0018] When the duration of the reset current pulse reaches a set time, a second low voltage is applied to the selected word line and the selected bit line to end the reset operation of the selected phase change memory.

[0019] In a second aspect, an embodiment of the present invention further provides a phase change memory, comprising a memory array, wherein the memory array comprises a plurality of memory array blocks; each memory array block comprises a plurality of phase change memory cells connected between word lines and bit lines;

[0020] and a peripheral circuit coupled to the memory array and configured to control the memory array; wherein,

[0021] The peripheral circuit is configured to: apply a first voltage to a selected word line coupled to a selected phase change memory cell, and apply a second voltage to a selected bit line coupled to the selected phase change memory cell;

[0022] When a selector included in the selected phase-change memory cell is turned on based on the first voltage and the second voltage, a reset operation is performed on the selected phase-change memory cell based on a reset current pulse;

[0023] Wherein, the first voltage includes a minimum voltage value, a maximum voltage value and an intermediate voltage value between the maximum voltage value and the minimum voltage value; under the action of the minimum voltage value and the second voltage, the selector included in the selected phase change memory unit whose threshold voltage is in the first distribution can be turned on; under the action of the maximum voltage value and the second voltage, the selector included in the selected phase change memory unit whose threshold voltage is in the second distribution can be turned on; the intermediate voltage value is used to reduce the current flowing through the selected phase change memory unit when the first voltage applied by the selected word line rises from the minimum voltage value to the maximum voltage value; the first distribution and the second distribution constitute the threshold voltage distribution of the phase change memory unit contained in the phase change memory.

[0024] In the above solution, the peripheral circuit includes a current mirror coupled to the selected bit line for controlling the reset current pulse.

[0025] In the above scheme, the peripheral circuit is further configured to: when the duration of the reset current pulse reaches a set time, apply a second low voltage to the selected word line and the selected bit line to end the reset operation of the selected phase change memory.

[0026] In a third aspect, an embodiment of the present invention further provides a memory system, comprising: one or more phase change memories as described above and a memory controller coupled to the phase change memories.

[0027] The embodiment of the present invention provides an operation method of a phase change memory, a phase change memory and a memory system. The phase change memory includes a memory array, the memory array includes a plurality of memory array blocks; each memory array block includes a plurality of phase change memory cells connected between word lines and bit lines; the operation method includes: applying a first voltage to a selected word line coupled to a selected phase change memory cell, applying a second voltage to a selected bit line coupled to the selected phase change memory cell; based on the first voltage and the second voltage, when a selector included in the selected phase change memory cell is turned on, resetting the selected phase change memory cell based on a reset current pulse; the first voltage includes a minimum voltage value, a maximum voltage value and the maximum voltage value. and the lowest voltage value; under the action of the lowest voltage value and the second voltage, the selector included in the selected phase change memory cell whose threshold voltage is in the first distribution can be turned on; under the action of the highest voltage value and the second voltage, the selector included in the selected phase change memory cell whose threshold voltage is in the second distribution can be turned on; the intermediate voltage value is used to reduce the current flowing through the selected phase change memory cell when the first voltage applied by the selected word line rises from the lowest voltage value to the highest voltage value; the first distribution and the second distribution constitute the threshold voltage distribution of the phase change memory cell included in the phase change memory. In the embodiment of the present invention, the voltage applied to the selected word line coupled to the selected phase change memory cell is set in a step-up form, so as to reduce the peak value of the inrush current introduced into the phase change memory cell due to the voltage mutation during the process of the voltage rising to the maximum voltage value in a short time, so as to reduce the harm to the phase change memory cell, thereby improving the life of the phase change memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A block diagram of an exemplary system including a memory provided for an embodiment of the present invention;

[0029] Figure 2 A schematic diagram of the structure of an exemplary memory including a peripheral circuit provided by an embodiment of the present invention;

[0030] Figure 3 A schematic diagram of a three-dimensional phase-change memory cell array observed through a scanning electron microscope provided by an embodiment of the present invention;

[0031] Figure 4 A schematic diagram of the logical structure of a three-dimensional phase change memory array provided by an embodiment of the present invention;

[0032] Figure 5 A partial three-dimensional schematic diagram of a phase change memory unit provided by an embodiment of the present invention;

[0033] Figure 6 Another partial three-dimensional schematic diagram of a phase change memory unit provided by an embodiment of the present invention;

[0034] Figure 7 A schematic diagram of the current-voltage characteristics of an OTS included in a phase change memory unit provided in an embodiment of the present invention;

[0035] Figure 8 A schematic diagram of the current-voltage characteristics of a phase change memory unit provided by an embodiment of the present invention;

[0036] Fig. 9 A block diagram of an exemplary memory including a phase change memory array and peripheral circuits provided for an embodiment of the present invention;

[0037] Fig.10 A schematic diagram of providing voltage to a phase change memory cell in a phase change memory array provided by an embodiment of the present invention;

[0038] Fig.11 A schematic diagram of a circuit structure for operating a phase change memory unit provided by an embodiment of the present invention;

[0039] Fig.12 A schematic diagram of pulses during the operation of a phase change memory unit provided by an embodiment of the present invention;

[0040] Fig.13 A schematic diagram of threshold voltage distributions of set and reset states of a phase change memory cell provided by an embodiment of the present invention;

[0041] Fig.14 A schematic flow chart of a method for operating a selected phase change memory cell provided by an embodiment of the present invention;

[0042] Fig.15 A schematic diagram of applying voltage to a selected word line and a selected bit line and providing a reset current pulse when performing a reset operation on a phase change memory cell is provided for an embodiment of the present invention;

[0043] Fig.16 Another schematic diagram of applying voltage to a selected word line and a selected bit line and providing a reset current pulse when performing a reset operation on a phase change memory cell is provided for an embodiment of the present invention;

[0044] Fig.17 An embodiment of the present invention further provides a schematic diagram of a circuit structure for applying a first voltage including multiple intermediate voltage values ​​to a selected word line;

[0045] Fig.18 A schematic diagram of a process of performing a reset operation on a phase change memory unit provided by an embodiment of the present invention;

[0046] Fig.19The embodiment of the present invention provides Fig.15 Schematic diagram of the effect of applying voltage and providing reset current pulse;

[0047] Fig. 20 The embodiment of the present invention provides Fig.16 Schematic diagram of the effect of applying voltage and providing a reset current pulse. DETAILED DESCRIPTION

[0048] Although specific configurations and arrangements have been discussed, it should be understood that this is done for illustrative purposes only. Therefore, other configurations and arrangements may be very practical without departing from the scope of the present invention. In addition, the present invention may also be used for various other applications. The functions and structural features as described in the present invention may be combined, adjusted and modified with each other and in a manner not specifically shown in the accompanying drawings, so that these combinations, adjustments and modifications are within the scope of the disclosure of the present invention.

[0049] Typically, a term can be understood, at least in part, from usage in context. For example, the term "one or more," as used herein, can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a feature, structure, or combination of features in a plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" can also be understood to express singular usage or to express plural usage, depending at least in part on the context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, but can allow for the presence of other factors that are not necessarily explicitly described, again depending at least in part on the context.

[0050] Phase Change Memory (PCM) is a non-volatile memory device that uses phase change materials to store data. PCM can be based on heating and quenching the phase change material in an electrothermal manner, using the difference between the resistivity of the amorphous state and the crystalline state in the phase change material (e.g., a chalcogenide alloy). The phase change material in the PCM cell can be located between two electrodes, and a current can be applied to repeatedly switch the material (or at least a portion of it blocking the current path) between the two phases to store data. The set state is a low resistance state of the PCM cell, which can be obtained by generating a crystalline region in the chalcogenide material. When the chalcogenide material is heated at a crystallization temperature for a sufficient time, crystallization occurs. Conversely, the reset state is a high resistance state of the PCM cell, which can be obtained by generating a non-crystalline region in the chalcogenide material. When the chalcogenide material is heated to above its melting temperature and then rapidly quenched to form an amorphous state, an amorphous state can be generated. Among them, the set state can be referred to as the on state; and the reset state can be referred to as the off state.

[0051] As described above, when the phase change material in the PCM switches between the crystalline state and the amorphous state, a different pulse (e.g., a voltage pulse) is required to control the heating of the phase change material. Currently, in the related art, during the reset process of the phase change memory cell, the voltage applied to the word line coupled to the phase change memory cell will introduce a considerable inrush current spike to the phase change memory cell, wherein the inrush current spike will damage the phase change memory cell and is also the main factor affecting the life of the phase change memory cell.

[0052] In order to solve the above technical problems, an embodiment of the present invention provides an operating method for a phase change memory cell, by setting the voltage applied to the word line coupled to the phase change memory cell in a step-up form, so as to reduce the peak value of the inrush current introduced into the phase change memory cell due to the voltage mutation during the process of the voltage rising to the maximum voltage value in a short time, thereby reducing the damage to the phase change memory cell, thereby improving the life of the phase change memory cell.

[0053] The technical solution provided by the embodiments of the present invention is described in detail below with reference to the accompanying drawings.

[0054] Figure 1 A block diagram of an exemplary system including a memory provided for an embodiment of the present invention. System 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1 As shown, the system 100 may include a host 108 and a memory system 102, wherein the memory system 102 has one or more memories 104 and a memory controller 106; the host 108 may be a processor of an electronic device, such as a central processing unit (CPU) or a system on chip (SoC), wherein the system on chip may be, for example, an application processor (AP). The host 108 may be configured to send data to the memory 104 or receive data from the memory 104.

[0055] Specifically, the memory 104 may be any memory device disclosed in the present invention, as disclosed in detail below, the memory 104, for example, a phase change random access memory (PCRAM); the memory 104 may also refer to a three-dimensional phase change memory.

[0056] According to some embodiments, the memory controller 106 is coupled to the memory 104 and the host 108. And is configured to control the memory 104. The memory controller 106 can manage the data stored in the memory 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices with low duty cycle environments such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as a solid state drive (SSD) or an embedded multimedia card (eMMC), wherein the SSD or eMMC is used as a data storage device for a mobile device with a high duty cycle environment such as a smart phone, a tablet computer, a laptop computer, and an enterprise storage array. The memory controller 106 can be configured to control the operation of the memory 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol.For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnection (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0057] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. In one example, the memory controller 106 and a single memory 104 can be integrated into a memory card. The memory card may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card may also include a memory card that connects the memory card to a host (e.g., Figure 1 In another example, the memory controller 106 and the plurality of memories 104 may be integrated into an SSD. The SSD may also include a memory card connector that couples the SSD to a host (e.g., Figure 3 The memory controller 106 may be configured to control the erase, read, and write operations of the memory 104.

[0058] Figure 2A schematic diagram of the structure of an exemplary memory including a peripheral circuit provided by an embodiment of the present invention. The memory 104 may be a three-dimensional phase change memory, which may include a phase change memory array 201 and a peripheral circuit 202 coupled to the phase change memory array 201. The phase change memory array 201 may include a word line 2011, a bit line 2012, and a phase change memory cell 2013 formed between the word line 2011 and the bit line 2012. In some embodiments, each phase change memory cell 2013 may include a PCM element (including a phase change material, not shown in the figure) connected in series with a selector (not shown in the figure). In some embodiments, the phase change memory cell 2013 may include a DRAM cell of a paired transistor and a capacitor. In order to operate the phase change memory array 201, a word line voltage (Vw) may be applied to a selected word line 2011, and a bit line voltage (Vb) may be applied to a selected bit line 2012.

[0059] Regarding the structure of the phase change memory array 201, in some embodiments, as Figure 3 As shown, it shows a schematic diagram of a three-dimensional phase change memory cell array observed by a scanning electron microscope provided by an embodiment of the present invention. Figure 3 It can be seen that the phase change memory array 201 is a three-dimensional memory array, which is composed of a plurality of small memory array blocks with a single bit line, a word line and a phase change memory cell. A three-dimensional phase change memory generally includes a top bit line, a word line, a bottom bit line and a phase change memory cell located at the intersection of the bit line and the word line. In practical applications, the word line, the top bit line and the bottom bit line are usually formed by a 20nm / 20nm equal width line (L / S, Line / Space) pattern formed after a patterning process.

[0060] In other embodiments, Figure 4 As shown, it shows a schematic diagram of the logical structure of a three-dimensional phase change memory array provided by an embodiment of the present invention. Figure 4 It can be seen that the phase-change memory array 201 includes a plurality of memory groups, each memory group includes two upper and lower phase-change memory cells 2013, wherein each group of upper and lower phase-change memory cells 2013 share the same word line, such as word lines WL1, WL2, WL3, etc.; each upper phase-change memory cell 2013 is coupled to an upper bit line, such as TCBL1, TCBL2, TCBL3, etc.; each lower phase-change memory cell 2013 is coupled to a lower bit line, such as BCBL1, BCBL2, BCBL3, etc. That is, each phase-change memory cell 2013 is located at the intersection of a word line and a bit line.

[0061] The structure of the phase change memory unit 2013 is as follows: Figure 5As shown, it shows a three-dimensional schematic diagram between the word line and the bit line of the phase change memory unit 2013 provided by an embodiment of the present invention. It should be noted that, Figure 5 yes Figure 4 A schematic diagram of a partial three-dimensional structure of a three-dimensional phase change memory array is provided. Each storage group includes two upper and lower phase change memory cells 2013, and the two phase change memory cells share the same word line. The phase change memory cell 2013 includes: a stacked PCM element 502, a selector 504, and a plurality of electrodes 501, 503, and 505. The PCM element 502 can utilize the difference between the resistivity of the amorphous phase (i.e., amorphous state) and the crystalline phase (i.e., crystalline state) in the phase change material based on the heating and quenching of the phase change material in an electrothermal manner. A current can be applied to cause the phase change material of the PCM element 502 (or at least a portion thereof that blocks the current path) to repeatedly switch between two phases to store data. A single bit of data can be stored in each phase change memory cell 2013, and a single bit of write operation or read operation can be performed by changing the voltage applied to the corresponding selector 504.

[0062] In some embodiments, the material of the PCM element 502 includes a chalcogenide-based alloy (chalcogenide glass), such as a GST (Ge-Sb-Te) alloy, or includes any other suitable phase change material; the material of the selector 504 may include any suitable bidirectional threshold switch (OTS) material, such as ZnxTey, GexTey, NbxOy, SixAsyTez, etc. The electrodes 501, 503, and 505 may include a conductive material, including but not limited to W, Co, Cu, Al, carbon, polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the material of the electrodes 501, 503, and 505 includes carbon, such as amorphous carbon.

[0063] It should be noted that the upper and lower phase change memory cells in the phase change memory array 201 can also share a bit line. For a specific structure, see Figure 6 , which shows another three-dimensional schematic diagram between the word lines and the bit lines of the phase change memory unit 2013 provided by an embodiment of the present invention.

[0064] Based on the structure of the phase change memory unit 2013 described above, it can be known that in a three-dimensional phase change memory, OTS is used as a selector to access the phase change memory unit coupled to OTS in a relatively large phase change memory array. Figure 7 As shown in FIG. 1 , a current-voltage characteristic diagram of an OTS included in a phase-change memory cell provided in an embodiment of the present invention is shown. Based on the current-voltage characteristic of OTS, it can be seen that when the voltage across OTS is greater than Vhold, OTS will be turned on instantly, which will introduce a relatively large inrush current. On this basis, Figure 8 As shown, it shows a current-voltage characteristic diagram of the phase change memory unit provided by an embodiment of the present invention. Based on the previous description, the phase change material of the phase change memory unit is in a high resistance state in the reset state and in a low resistance state in the set state. Since the phase change memory unit is a series connection of a selector and a phase change material, when the phase change memory is in the set state, its threshold voltage is equal to the threshold voltage of the selector OTS, that is, Vt, set = Vt (OTS); when the phase change memory unit is in the reset state, its threshold voltage is equal to the sum of the threshold voltage of the selector OTS, the threshold voltage of the PCM element and the threshold voltage of OTS, that is: Vt, reset = Vt (OTS) + Vt (PCM).

[0065] Based on this, when setting or resetting a phase change memory cell, it is first necessary to apply a voltage greater than its threshold voltage across the phase change memory cell to turn on the selector contained in the phase change memory cell, thereby enabling current to flow through the phase change material contained in the phase change memory cell to heat the phase change material, thereby setting or resetting the phase change memory cell.

[0066] Fig. 9 A block diagram of an exemplary memory including a phase change memory array and peripheral circuits provided for an embodiment of the present invention. Fig. 9 As shown, the memory 104 includes a phase change memory array 201 and a peripheral circuit 202, wherein the phase change memory array has been described above and will not be described again. The peripheral circuit 202 includes: a control logic 2021, an address register 2022, a voltage generator 2023, a row decoder / word line driver 4023, a page buffer / sense amplifier circuit 2025, a column decoder / bit line driver / data latch 2026, and a data register / data I / O 2027, wherein;

[0067] The page buffer / sense amplifier circuit 2025 can be configured to read data from the phase-change memory array 201 and program (write) data to the phase-change memory array 201 according to the control signal from the control logic 2021. In one example, the page buffer / sense amplifier 2025 can store data to be programmed into the phase-change memory array 201 (e.g., Figure 2In another example, the page buffer / sense amplifier 2025 can perform a program verification operation to ensure that the data has been correctly programmed into the phase change memory cell 2013 coupled to the selected word line 2011. In yet another example, the page buffer / sense amplifier 2025 can also sense a low-power signal representing a data bit stored in the phase change memory cell 2013 from the selected bit line 2012, and amplify the small voltage swing to a recognizable logic level in a read operation. In some embodiments, the page buffer / sense amplifier 2025 may include a comparator (e.g., a voltage comparator) to compare a voltage signal (e.g., a read voltage) with a reference voltage signal (e.g., a predetermined threshold voltage of a memory cell in a "set" state). The column decoder / bit line driver / data latch 2026 can be configured to be controlled by the control logic 2021 and select one or more phase change memory cells 2013 and bit lines 2012. Column decoder / bit line driver / data latch 2026 may be further configured to drive selected bit line 2012. Column decoder / bit line driver / data latch 2026 may be further configured to drive bit line 2012 using a bit line voltage generated from voltage generator 2023. Column decoder / bit line driver / data latch 2026 may be a temporary binary data storage device for storing bits. In some embodiments, column decoder / bit line driver / data latch 2026 may include a read data latch to temporarily store read data.

[0068] The data register / data I / O 416 can be coupled to the page buffer / sense amplifier 2025 and / or the column decoder / bit line driver / data latch 2026, and is configured to direct (route) data input from the data bus 2028 to the desired phase change memory cell 2013 of the phase change storage array 201, and to direct (route) data output from the desired memory cell to the data bus 2028.

[0069] The row decoder / word line driver 4023 may be configured to be controlled by the control logic 2021 and select one or more phase change memory cells 2013 and word lines 2011 of the phase change memory array 201. The row decoder / word line driver 4023 may be further configured to drive the selected word line 2011. The row decoder / word line driver 4023 may be further configured to drive the word line 2011 using a word line voltage generated from the voltage generator 2023.

[0070] The voltage generator 2023 can be configured to be controlled by the control logic 2021 according to a control signal from the control logic 2021, and generate a word line voltage (e.g., a read voltage, a programming voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be provided to the phase change memory array 201.

[0071] The control logic 2021 may be coupled to each peripheral circuit described above and configured to control the operation of each peripheral circuit. The control logic 2021 is configured to receive the data from the host (eg, Figure 1 108 in the figure) receives clock signals, command signals, address signals and data signals, wherein the command signals are received via the command bus 2029; and the data signals are received via the data bus 2028. In some embodiments, the control logic 2021 can be implemented by a microprocessor, a microcontroller (also known as a microcontroller unit (MCU, Micro Controller Unit)), a digital signal processor (DSP, Digital Signal Processor), an application specific integrated circuit (ASIC, Application Specific Integrated Circuit), a field programmable gate array (FPGA, Field Programmable Gate Array), a programmable logic device (PLD, Programmable Logic Device), a state machine, a gating logic, a discrete hardware circuit and other appropriate hardware, firmware and / or software configured to perform the various functions described.

[0072] Fig.10 A schematic diagram of providing voltage to a phase change memory cell in a phase change memory array provided by an embodiment of the present invention. Figure 4 It can be seen from the phase-change memory array shown that in a phase-change memory array, adjacent phase-change memory cells must share a common word line or a common bit line. Therefore, when a voltage is applied to the word line and bit line of the selected phase-change memory cell to turn on its selector, the bit line and word line corresponding to the phase-change memory cell adjacent to the selected phase-change memory cell will inevitably be applied with a voltage because the word line or bit line is shared with the selected phase-change memory cell. At this time, there must be a voltage difference between the bit line and word line corresponding to the phase-change memory cell adjacent to the selected phase-change memory cell. For details, see Fig.10 .exist Fig.10In the figure, (s) represents a selected phase-change memory cell, whose voltage on the word line is Vhh, the voltage on the bit line is VII, and the voltage difference between the word line and the bit line is Vhh-VII; the others (a), (b), and (c) represent three types of unselected phase-change memory cells, among which (a) the voltage on the word line of the unselected phase-change memory cell of type (type a) is Vhh, the voltage on the bit line is Vub, and the voltage difference between the word line and the bit line Va=Vhh-Vub; (b) the voltage on the word line of the unselected phase-change memory cell of type (type b) is Vuw, the voltage on the bit line is VII, and the voltage difference between the word line and the bit line Vb=Vuw-VII; (c) the voltage on the word line of the unselected phase-change memory cell of type (type c) is Vuw, the voltage on the bit line is Vub, and the voltage difference between the word line and the bit line Vc=Vuw-Vub. Regardless of the type of these unselected phase-change memory cells, the voltage difference between their word lines and bit lines will not turn on the selectors (OTS) they contain. Only the voltage difference between the word lines and bit lines of the selected phase-change memory cells can turn on the selectors they contain.

[0073] Fig.11 The circuit structure diagram of the operation of a phase change memory unit provided by the embodiment of the present invention is as follows. Fig.11 As shown, once the control logic 2021 determines that the command signal is a reset command, a read command or a write instruction, the control logic 2021 triggers the reset operation, the read operation or the write operation, and then leads the word line voltage to the word line of the selected phase change memory cell through the word line driver, and leads the bit line voltage to the bit line of the selected phase change memory through the bit line driver, and then under the action of the word line voltage and the bit line voltage, the selector of the selected phase change memory cell is turned on; thereafter, different pulses are provided to the phase change memory cell to perform reset, read or write operations.

[0074] As described above, when the phase change material in the PCM switches between the crystalline state and the amorphous state, different pulses (such as light pulses, electric pulses) can be used to control the heating of the phase change material. Fig.12As shown, when a long and medium-intensity programming pulse (also called Set Pulse) is applied to raise the temperature of the phase change material layer of the phase change memory unit to below the melting temperature Tm and above the crystallization temperature Tx, and is maintained for a period of time to promote the growth of the crystal nucleus, the phase change material layer of the phase change memory unit can be transformed from an amorphous state (corresponding to a high resistance state) to a crystalline state (corresponding to a low resistance state). The process of realizing the transformation of the phase change material of the phase change memory unit from a high state (0 state) to a low resistance state (1 state) is usually called a set (Set) process, or a write operation process; after applying a short and strong reset pulse (also called Reset Pulse) to raise the temperature of the phase change material layer of the phase change memory unit to above the melting temperature Tm, and then undergoing rapid cooling (Cooling Down), the phase change material layer of the phase change memory unit can be transformed from a crystalline state to an amorphous state. The process of realizing the transformation of the phase change material layer of the phase change memory unit from a low resistance state (1 state) to a high state (0 state) is usually called a reset (Reset) process, or an erase operation process. The Reset process and the Set process are mutually reversible processes, and thus the phase change memory cell can use the crystalline state to represent a unit binary data 1, and use the amorphous state to represent a binary data 0.

[0075] In some embodiments, Fig.13 , which is a schematic diagram showing the threshold voltage distribution of the set and reset states of the phase change memory cell provided by an embodiment of the present invention. Fig.13 In, V TH_SET is the distribution of the threshold voltage of the phase change memory cell in the set state; V TH_RESET is the distribution of the threshold voltage of the phase change memory cell in the reset state, and the two together constitute the threshold voltage distribution of the phase change memory. It should be noted that the threshold voltage distribution can change from one memory array to another memory array, and can also change from one memory array block to another memory array block, that is, for the threshold voltage distribution of different numbers of phase change memory cells, the shape will be slightly different, but the general shape is similar.

[0076] Based on the three-dimensional phase change memory described above, in order to solve the technical problems described above, an embodiment of the present invention provides an operation method of a phase change memory. Specifically, the phase change memory includes a storage array, and the storage array includes a plurality of storage array blocks; each storage array block includes a plurality of phase change memory cells connected between word lines and bit lines. Based on this, Fig.14 As shown, the operation method includes:

[0077] S1401: applying a first voltage to a selected word line coupled to a selected phase change memory cell, and applying a second voltage to a selected bit line coupled to the selected phase change memory cell;

[0078] S1402: performing a reset operation on the selected phase change memory unit based on a reset current pulse when a selector included in the selected phase change memory unit is turned on based on the first voltage and the second voltage;

[0079] Wherein, the first voltage includes a minimum voltage value, a maximum voltage value and an intermediate voltage value between the maximum voltage value and the minimum voltage value; under the action of the minimum voltage value and the second voltage, the selector included in the selected phase change memory unit whose threshold voltage is in the first distribution can be turned on; under the action of the maximum voltage value and the second voltage, the selector included in the selected phase change memory unit whose threshold voltage is in the second distribution can be turned on; the intermediate voltage value is used to reduce the current flowing through the selected phase change memory unit when the first voltage applied by the selected word line rises from the minimum voltage value to the maximum voltage value; the first distribution and the second distribution constitute the threshold voltage distribution of the phase change memory unit contained in the phase change memory.

[0080] It should be noted that the operation method can be a reset operation on a selected phase change memory cell. The selected phase change memory cell is any phase change memory cell in a certain storage array block in the storage array of the phase change memory. In other words, the operation method can be for any phase change memory in the storage array.

[0081] Here, since the threshold voltage of the selected phase change memory cell is unknown, for a phase change memory, the threshold voltage distribution of the phase change memory cells it contains may be known, for example, obtained through a preliminary durability test cycle. As described above, the threshold voltage distribution may be obtained by counting the threshold voltages of the phase change memory cells contained in a storage array, or by counting the threshold voltages of the phase change memory cells contained in a storage array block. In the case where the threshold voltage distribution is known, if you want to turn on the selector of a selected phase change memory cell with an unknown threshold voltage, a safer approach is to apply a threshold voltage value at least equal to the maximum threshold voltage distribution on the selected word line of the selected phase change memory cell, and apply a negative second voltage on the selected bit line, so that the voltage difference between the selected word line and the selected bit line is greater than the threshold voltage of the selected phase change memory cell, so that the selector contained therein is turned on.

[0082] However, it should be noted that, since the threshold voltage of the selected phase-change memory may also be relatively low, a relatively large voltage is instantly applied to the selected word line of the selected phase-change memory cell, and when a negative second voltage is applied to the selected bit line, the voltage difference between the selected word line and the selected bit line is relatively large. As described above, when the threshold voltage of the phase-change memory cell is relatively low, its resistance is also relatively low. In this case, a relatively large inrush current will be introduced into the selected phase-change memory cell, causing relatively large damage to the selected phase-change memory cell.

[0083] In some embodiments, Fig.15 Schematic diagram of applying voltage and reset current pulse to selected word line and selected bit line. Fig.15 In FIG. 1 , LWL represents a voltage curve applied to a selected word line of a selected phase change memory cell; LBL represents a voltage curve applied to a selected bit line of a selected phase change memory cell; and Ireset represents a reset current pulse applied to the selected phase change memory cell. Fig.15 It can be seen that the voltage applied to the selected word line adopts a two-stage method, first making the applied voltage reach the minimum voltage value Vr, and then making the applied voltage rise from the minimum voltage value Vr to the maximum voltage value Vhh, so that under the action of Vr and the second voltage on the selected bit line, the selector included in the selected phase change memory unit with a threshold voltage in the first distribution can be turned on, and the first distribution includes the phase change memory unit with a threshold voltage less than or equal to the minimum voltage value Vr in the threshold voltage distribution; under the action of the maximum voltage value Vhh and the second voltage, the selector included in the selected phase change memory unit with a threshold voltage in the second distribution can be turned on, and the second distribution includes the phase change memory unit in the threshold voltage distribution except the phase change memory unit corresponding to the first distribution. So far, the selector included in the selected phase change memory unit can be turned on regardless of where the selected phase change memory unit is in the threshold voltage distribution. It should be noted that, as described above, since the threshold voltage of the selected phase change memory cell is unknown before the reset operation, it may be in the first distribution or the second distribution. Therefore, the voltage finally applied to the selected word line of the selected phase change memory cell will reach the maximum voltage value Vhh to ensure that the selector contained in the selected phase change memory cell can be opened.

[0084] Based on this, in adopting Fig.15In the word line voltage application method shown, when the selector included in the selected phase change memory cell is turned on under the action of the lowest voltage value Vr and the second voltage, based on the characteristics of the selector described above, a relatively large inrush current Inrush current1 will be introduced at the turn-on moment, wherein Inrush current1 = (Vt-Vhold) / Rcell, Vt is the threshold voltage of the selected phase change memory cell; Vhold is the holding voltage of the selector; Rcell is the resistance value of the selected phase change memory cell, which is characterized in that the lower the threshold voltage, the lower the resistance value, that is, when the selector included in the selected phase change memory cell is turned on under the action of the lowest voltage value Vr and the second voltage, the resistance value of the selected phase change memory cell is relatively low. In addition, when the voltage of the selected word line rises from the minimum voltage value Vr to the maximum voltage value Vhh, since the resistance value at this time is still relatively low, another inrush current Inrush current2 will be introduced, where Inrushcurrent2 = (Vhh-Vr) / Rcell. The Inrush current2 is usually much larger than the reset current Ireset provided by the selected phase change memory cell, which may damage the selected phase change memory cell.

[0085] Therefore, in order to solve the above technical problems, an embodiment of the present invention provides an operation method, in which, Fig.16 As shown, the first voltage applied to the selected word line is set to one or more intermediate voltage values ​​that increase in sequence between the lowest voltage value and the highest voltage value, such as intermediate voltage values ​​V1, V2, and V3. In this way, when the first voltage rises from the lowest voltage value Vr to the highest voltage value Vhh, since it does not rise to the maximum voltage value Vhh instantly in a short time, a large Inrush current 2 will not be introduced, thereby reducing damage to the selected phase change memory cell. It should be noted that Fig.16 The three intermediate voltage values ​​shown are only an exemplary display. The number of intermediate voltage values ​​can be set according to actual needs.

[0086] That is, in some embodiments, the intermediate voltage value includes one or more.

[0087] In some embodiments, when the intermediate voltage value includes multiple values, the multiple intermediate voltage values ​​may increase in equal steps. In other embodiments, when the intermediate voltage value includes multiple values, the multiple intermediate voltage values ​​may also increase in different steps.

[0088] In an optional embodiment, multiple intermediate voltage values ​​can also be increased in a step-by-step manner. For example, assume that three intermediate voltage values ​​are set, a first intermediate voltage value; a second intermediate voltage value; and a third intermediate voltage value, wherein the first intermediate voltage value is less than the second intermediate voltage value; the second intermediate voltage value is less than the third intermediate voltage value; the second intermediate voltage value is 0.5 volts (V) greater than the first intermediate voltage value; and the third intermediate voltage value is 1V greater than the second intermediate voltage value, that is, different step sizes are used to increase, and the increase is made in a step-by-step manner.

[0089] In some embodiments, the number of the intermediate voltage values ​​is not greater than a preset threshold.

[0090] Theoretically, the number of intermediate voltage values ​​is not limited, but in actual application, considering external factors such as the efficiency of the reset operation, the number of intermediate voltage values ​​should not be greater than the preset threshold. The preset threshold can be considered to be set according to actual conditions, for example, the preset threshold is 6.

[0091] In some embodiments, the first voltage is a positive voltage; and the second voltage is a negative voltage.

[0092] That is, the lowest voltage value, the highest voltage value and the middle voltage value included in the first voltage are all positive voltage values. The second voltage can be a negative voltage. In some embodiments, the second voltage can also be zero.

[0093] like Fig.17 As shown, an embodiment of the present invention also provides a circuit structure schematic diagram for applying a first voltage including multiple intermediate voltage values ​​to a selected word line. Fig.17 In the figure, WL Driver represents the word line driver; V1 and V2 represent two intermediate voltage values; Vr represents the minimum voltage value; and Vhh represents the maximum voltage value. Obviously, the sizes of V1 and V2 are between Vr and Vhh, so it can be considered that V1 is greater than V2. Cell represents the selected phase change memory cell; BL represents the selected bit line; WL represents the selected word line; BLSelector represents the bit line selector, which is used to determine the bit line to be selected in the storage array, that is, the selected bit line; DL Selector represents a digital connection line, a connection line in the storage array. Ireset represents the current source of the reset current pulse.

[0094] based on Fig.17 The circuit connection structure sequentially increases the first voltage on the selected word line from zero to Vr, then to V1, then to V2, and finally to Vhh through the word line driver WL Driver.

[0095] Based on the above Fig.17In some embodiments, when a selected phase-change memory cell is reset, before a selector of the phase-change memory is turned on, a voltage drop on a word line is reduced, and a driving capability of a word line driver is improved, and the first voltage is applied before the second voltage.

[0096] For example, in an optional implementation, the operating method further includes: when the first voltage does not reach the minimum voltage value, maintaining the voltage on the selected bit line as a first low voltage, until the first voltage reaches the minimum voltage value, and starting to apply the second voltage to the selected bit line.

[0097] Here, the first low voltage may be 0 V. That is, by keeping the voltage on the selected bit line at 0 V when the first voltage does not reach the lowest voltage value, the first voltage is applied to the selected word line before the voltage is applied to the selected bit line.

[0098] In some embodiments, the reset current pulse is controlled by a current mirror coupled to the selected bit line.

[0099] Here, the amplitude of the reset current pulse is controlled by a current mirror coupled to the selected bit line.

[0100] In some embodiments, the operating method further includes:

[0101] When the duration of the reset current pulse reaches a set time, a second low voltage is applied to the selected word line and the selected bit line to end the reset operation of the selected phase change memory.

[0102] Here, the second low voltage may be 0V. The operation here is an operation after the selected phase change memory cell is reset, and is used to end the reset operation of the selected phase change memory. The set time is the time required for all phase change materials contained in the selected phase change memory cell to change from a crystalline state to an amorphous state. The set time may be an empirical value.

[0103] Based on the operating method of the phase change memory provided by the embodiment of the present invention, the reset operation is performed on the selected phase change memory unit, such as Fig.18 As shown, the specific steps are as follows:

[0104] In the first step, a selected word line and a selected bit line of the selected phase change memory are grounded;

[0105] In the second step, the lowest voltage value Vr is applied to the selected word line, and the selected word line continues to be grounded;

[0106] The third step is to apply a second voltage VII to the selected bit line to turn on the selector of the selected phase change memory cell whose threshold voltage is in the first distribution; and provide a current source connection for a reset current pulse;

[0107] Step 4, sequentially increasing the voltage on the selected word line to a first intermediate voltage value V1, a second intermediate voltage value V2, or more intermediate voltage values ​​until it reaches a maximum voltage value Vhh, so that if the threshold voltage of the selected phase change memory cell is in the second distribution, the selector included therein can also be turned on;

[0108] In the fifth step, when the duration of the reset current pulse reaches the set time, the voltage on the selected word line and the selected bit line is reduced to 0V, thereby ending the reset operation on the selected phase change memory.

[0109] The operating method of the phase change memory provided by the embodiment of the present invention is similar to the method of applying the first voltage in two stages (effect as Fig.19 By setting the voltage applied to the selected word line coupled to the selected phase change memory cell in a multi-step rising form (the effect is as shown in FIG. Fig. 20 As shown), when the selected phase-change memory cell is turned on by a smaller voltage value, the voltage suddenly changes due to the voltage rising to the maximum voltage value in a short time during the process of the selected phase-change memory cell being turned on by a smaller voltage value, thereby introducing the inrush current peak value of the phase-change memory cell, thereby reducing the damage to the phase-change memory cell, thereby improving the life of the phase-change memory cell. It should be noted that Fig.19 In the process, the T1 stage indicates that the second voltage is applied to the selected bit line first, which is the BLP process; the T2 stage indicates that the first voltage is applied to the selected word line, which is the WLP process; the T3 stage indicates that the selected phase change memory cell has been turned on in the T2 stage, and the selected phase change memory cell is reset, which is the Reset process; the T4 stage indicates the end of the reset operation of the selected phase change memory cell. ILBL indicates the current curve induced on the selected bit line; VLWL indicates the curve corresponding to the first voltage applied to the selected word line; VLBL indicates the curve corresponding to the second voltage applied to the selected bit line; VDLGate indicates that a certain driving voltage is required to introduce the second voltage to the selected bit line in order to apply the second voltage to the selected bit line. Fig. 20 In the process, the stages T1, T2, T3, and T4 are still the same, but Fig. 20 It can be seen that the embodiment of the present invention first applies a first voltage to the selected word line, and then applies a second voltage to the selected bit line. And the applied first voltage is set to have three steps, a minimum voltage value, an intermediate voltage value, and a maximum voltage value. Fig.19 and Fig. 20It can be seen from the current curve corresponding to ILBL that the word line voltage application method provided by the embodiment of the present invention can reduce the inrush current introduced into the phase change memory unit, thereby reducing the loss of the phase change memory unit.

[0110] Based on the same inventive concept, an embodiment of the present invention further provides a phase change memory, including a memory array, wherein the memory array includes a plurality of memory array blocks; each memory array block includes a plurality of phase change memory cells connected between word lines and bit lines;

[0111] and a peripheral circuit coupled to the memory array and configured to control the memory array; wherein,

[0112] The peripheral circuit is configured to: apply a first voltage to a selected word line coupled to a selected phase change memory cell, and apply a second voltage to a selected bit line coupled to the selected phase change memory cell;

[0113] When a selector included in the selected phase-change memory cell is turned on based on the first voltage and the second voltage, a reset operation is performed on the selected phase-change memory cell based on a reset current pulse;

[0114] Wherein, the first voltage includes a minimum voltage value, a maximum voltage value and an intermediate voltage value between the maximum voltage value and the minimum voltage value; under the action of the minimum voltage value and the second voltage, the selector included in the selected phase change memory unit whose threshold voltage is in the first distribution can be turned on; under the action of the maximum voltage value and the second voltage, the selector included in the selected phase change memory unit whose threshold voltage is in the second distribution can be turned on; the intermediate voltage value is used to reduce the current flowing through the selected phase change memory unit when the first voltage applied by the selected word line rises from the minimum voltage value to the maximum voltage value; the first distribution and the second distribution constitute the threshold voltage distribution of the phase change memory unit contained in the phase change memory.

[0115] In some embodiments, the peripheral circuit includes a current mirror coupled to the selected bit line for controlling the reset current pulse.

[0116] In some embodiments, the peripheral circuit is further configured to: apply a second low voltage to the selected word line and the selected bit line when the duration of the reset current pulse reaches a set time, thereby ending the reset operation on the selected phase change memory.

[0117] It should be noted that the phase change memory here and the aforementioned operating method belong to the same inventive concept, and the terms and operations appearing here have been described in detail above and will not be repeated here.

[0118] Based on the same inventive concept, an embodiment of the present invention further provides a memory system, comprising: one or more phase change memories as described above and a memory controller coupled to the phase change memories.

[0119] The memory system here belongs to the same inventive concept as the aforementioned operating method and phase change memory. The terms and operations appearing here have been described in detail above and will not be repeated here.

[0120] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention.

Claims

1. A method for operating a phase change memory, characterized in that: The phase change memory includes a memory array, and the memory array includes a plurality of memory array blocks; Each memory array block includes a plurality of phase change memory cells connected between word lines and bit lines; the operation method includes: Applying a first voltage to a selected word line coupled to a selected phase change memory cell, and applying a second voltage to a selected bit line coupled to the selected phase change memory cell; When a selector included in the selected phase-change memory cell is turned on based on the first voltage and the second voltage, a reset operation is performed on the selected phase-change memory cell based on a reset current pulse; Wherein, the first voltage includes a minimum voltage value, a maximum voltage value and an intermediate voltage value between the maximum voltage value and the minimum voltage value; under the action of the minimum voltage value and the second voltage, the selector included in the selected phase change memory unit whose threshold voltage is in the first distribution can be turned on; under the action of the maximum voltage value and the second voltage, the selector included in the selected phase change memory unit whose threshold voltage is in the second distribution can be turned on; the intermediate voltage value is used to reduce the current flowing through the selected phase change memory unit when the first voltage applied by the selected word line rises from the minimum voltage value to the maximum voltage value; the first distribution and the second distribution constitute the threshold voltage distribution of the phase change memory unit contained in the phase change memory.

2. The operating method according to claim 1, characterized in that: The intermediate voltage value includes one or more.

3. The operating method according to claim 2, characterized in that: When the intermediate voltage value includes a plurality of values, the plurality of intermediate voltage values ​​increase in equal steps.

4. The operating method according to claim 3, characterized in that: The number of the intermediate voltage values ​​is not greater than a preset threshold.

5. The operating method according to claim 1, characterized in that: The first voltage is a positive voltage; the second voltage is a negative voltage.

6. The operating method according to claim 5, characterized in that: The first voltage is applied before the second voltage.

7. The operating method according to claim 6, characterized in that: The operation method further includes: When the first voltage does not reach the minimum voltage value, the voltage on the selected bit line is maintained at a first low voltage until the first voltage reaches the minimum voltage value, and then the second voltage starts to be applied to the selected bit line.

8. The operating method according to claim 1, characterized in that: The reset current pulse is controlled by a current mirror coupled to the selected bit line.

9. The operating method according to claim 1, characterized in that: The operation method further includes: When the duration of the reset current pulse reaches a set time, a second low voltage is applied to the selected word line and the selected bit line to end the reset operation of the selected phase change memory.

10. A phase change memory, characterized in that: A memory array is included, wherein the memory array includes a plurality of memory array blocks; each memory array block includes a plurality of phase change memory cells connected between word lines and bit lines; and a peripheral circuit coupled to the memory array and configured to control the memory array; wherein, The peripheral circuit is configured to: apply a first voltage to a selected word line coupled to a selected phase change memory cell, and apply a second voltage to a selected bit line coupled to the selected phase change memory cell; When a selector included in the selected phase-change memory cell is turned on based on the first voltage and the second voltage, a reset operation is performed on the selected phase-change memory cell based on a reset current pulse; Wherein, the first voltage includes a minimum voltage value, a maximum voltage value and an intermediate voltage value between the maximum voltage value and the minimum voltage value; under the action of the minimum voltage value and the second voltage, the selector included in the selected phase change memory unit whose threshold voltage is in the first distribution can be turned on; under the action of the maximum voltage value and the second voltage, the selector included in the selected phase change memory unit whose threshold voltage is in the second distribution can be turned on; the intermediate voltage value is used to reduce the current flowing through the selected phase change memory unit when the first voltage applied by the selected word line rises from the minimum voltage value to the maximum voltage value; the first distribution and the second distribution constitute the threshold voltage distribution of the phase change memory unit contained in the phase change memory.

11. The phase change memory according to claim 10, characterized in that: The peripheral circuit includes a current mirror coupled to the selected bit line for controlling the reset current pulse.

12. The phase change memory according to claim 10, characterized in that: The peripheral circuit is further configured to: when the duration of the reset current pulse reaches a set time, apply a second low voltage to the selected word line and the selected bit line to end the reset operation of the selected phase change memory.

13. A memory system, characterized in that: include: The phase change memory as claimed in one or more claims 10 to 12 and a memory controller coupled to the phase change memory.

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