FPGA layout method, device, equipment and storage medium

Abstract

The present application provides a layout method, device, equipment and storage medium for FPGA. In an embodiment, the initial layout information of FPGA is obtained; the area information of at least one target area is determined according to multiple unit columns; the number of target units in each target area of ​​at least one target area is determined according to the position information of multiple target units and the area information of at least one target area; the position information of the legalization center point is determined according to the number of target units in each target area; the priority of each target unit in each target area is determined; and the target units in each target area are placed in the unit column in order from large to small according to the priority of each target unit in each target area. Therefore, through the technical solution provided in the embodiment of the present application, each target unit to be optimized can meet the position constraint conditions of the layout FPGA, thereby ensuring the performance of the FPGA.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and in particular to a layout method, device, equipment and storage medium of a Field Programmable Gate Array (FPGA) chip. Background Art

[0002] FPGA is a logic device with rich hardware resources, powerful parallel processing capabilities and flexible reconfiguration capabilities. These features make FPGA more and more widely used in many fields such as data processing, communication, and network.

[0003] In recent years, as the scale of FPGA circuits has grown rapidly, the functionality of FPGAs has become increasingly powerful. In order to ensure the performance of FPGAs, the layout of FPGAs has become increasingly critical and important. At present, although the legalization of FPGA layout can be achieved in related technologies, the layout of FPGAs in related technologies makes the layout accuracy of FPGAs low when multiple constraints are met, and some units cannot meet the position constraints corresponding to the units, and thus the performance of FPGAs cannot be guaranteed. Summary of the invention

[0004] The embodiments of the present application provide a layout method, apparatus, device and storage medium of an FPGA, which can improve the accuracy of the layout of the FPGA and ensure the performance of the FPGA.

[0005] In a first aspect, an embodiment of the present application provides a layout method of an FPGA, the method comprising:

[0006] Acquire initial layout information of the FPGA, wherein the initial layout information includes a plurality of cell columns for placing target cells of the same type, position information of the plurality of target cells, and the number of wire nets connected to each target cell;

[0007] Determining area information of at least one target area according to the plurality of unit columns;

[0008] Determining the number of target units in each target area of ​​the at least one target area according to the location information of the plurality of target units and the area information of each of the at least one target area;

[0009] Determining the position information of the legalization center point according to the number of target units in each target area;

[0010] Determine the priority of each target unit in each target area according to the number of target units in each target area, the location information of the multiple target units, the location information of the legalization center point, and the number of wire nets connected to each target unit;

[0011] According to the position information of the plurality of target cells, the target cells in each target area are sequentially placed in a cell column in descending order of priority of the target cells in each target area, so that the target cells in each target area meet the position constraint conditions of the FPGA layout;

[0012] For a target cell with a priority of i, after placing the target cell with a priority of i in a cell column, adjust the position of the target cell in the cell column, and determine a target cell area for placing the target cell with a priority of i from the target cell column based on the position information of the multiple target cells and the position information of the target cells in the cell column after the adjustment.

[0013] In a possible implementation, determining the respective priorities of the target units in each target area according to the number of target units in each target area, the location information of the multiple target units, the location information of the legalization center point, and the number of wire nets connected to each target unit includes:

[0014] Determine the distance between the target unit in each target area and the legalization center point according to the position information of the target unit in each target area and the position information of the legalization center point in the position information of the multiple target units;

[0015] Determining the priority of each target area according to the number of target units in each target area;

[0016] The priority of the target unit in each target area is determined according to the priority of each target area, the distance between the target unit in each target area and the legalization center point, and the number of wire meshes connected to the target unit in each target area.

[0017] In a possible implementation manner, after placing the target cell with priority i in a cell column, adjusting the position of the target cell in the cell column includes:

[0018] Determine the number of cell regions in which the target cells are not placed in the plurality of cell columns after the target cells with priorities 1 to i-1 in the at least one target region are placed in the cell column;

[0019] Determine, according to the number of cell regions in which the target cell is not placed in each of the plurality of cell columns, at least one cell column in which the target cell with the priority i can be placed;

[0020] placing the target cell with priority i in a cell column of the at least one cell column;

[0021] Adjust the position of the target cell within the cell column.

[0022] In a possible implementation, determining, from the target cell column, a target cell area for placing the target cell with priority i according to the position information of the plurality of target cells and the position information of the target cells in the cell column after the positions are adjusted, includes:

[0023] Calculating a cost value of the unit column after adjusting the positions of the target units in the unit column according to the position information of the plurality of target units and the position information of the target units in the unit column after adjusting the positions;

[0024] According to the cost value of at least one cell column, determining from the at least one cell column a target cell column in which the target cell with the priority i is placed and a target cell region in the target cell column for placing the target cell with the priority i;

[0025] The target cell with the priority i is placed in the target cell area in the target cell column.

[0026] In a possible implementation, the method further includes:

[0027] The location information of the target unit with the priority i is updated to the location information corresponding to the target unit area.

[0028] In a second aspect, an embodiment of the present application provides a layout device for an FPGA, the device comprising:

[0029] An acquisition module is used to acquire initial layout information of the FPGA, wherein the initial layout information includes a plurality of cell columns for placing target cells of the same type, position information of the plurality of target cells, and the number of wire nets connected to each target cell;

[0030] A first determination module, configured to determine area information of at least one target area according to the plurality of unit columns;

[0031] A second determining module, configured to determine the number of target units in each target area of ​​the at least one target area according to the location information of the plurality of target units and the area information of each of the at least one target area;

[0032] A third determination module is used to determine the position information of the legalization center point according to the number of target units in each target area;

[0033] A fourth determination module, configured to determine the priority of each target unit in each target area according to the number of target units in each target area, the location information of the multiple target units, the location information of the legalization center point, and the number of wire nets connected to each target unit;

[0034] A placement module, for placing the target cells in each target area in a cell column in order from large to small according to the position information of the plurality of target cells, so that the target cells in each target area meet the position constraint conditions of the FPGA layout;

[0035] For a target cell with a priority of i, after placing the target cell with a priority of i in a cell column, adjust the position of the target cell in the cell column, and determine a target cell area for placing the target cell with a priority of i from the target cell column based on the position information of the multiple target cells and the position information of the target cells in the cell column after the adjustment.

[0036] In a possible implementation manner, the fourth determining module is configured to:

[0037] Determine the distance between the target unit in each target area and the legalization center point according to the position information of the target unit in each target area and the position information of the legalization center point in the position information of the multiple target units;

[0038] Determining the priority of each target area according to the number of target units in each target area;

[0039] The priority of the target unit in each target area is determined according to the priority of each target area, the distance between the target unit in each target area and the legalization center point, and the number of wire meshes connected to the target unit in each target area.

[0040] In a possible implementation, the placement module is used to:

[0041] Determine the number of cell regions in which the target cells are not placed in the plurality of cell columns after the target cells with priorities 1 to i-1 in the at least one target region are placed in the cell column;

[0042] Determine, according to the number of cell regions in which the target cell is not placed in each of the plurality of cell columns, at least one cell column in which the target cell with the priority i can be placed;

[0043] placing the target cell with priority i in a cell column of the at least one cell column;

[0044] Adjust the position of the target cell within the cell column.

[0045] In a possible implementation, the placement module is used to:

[0046] Calculating a cost value of the unit column after adjusting the positions of the target units in the unit column according to the position information of the plurality of target units and the position information of the target units in the unit column after adjusting the positions;

[0047] According to the cost value of at least one cell column, determining from the at least one cell column a target cell column in which the target cell with the priority i is placed and a target cell region in the target cell column for placing the target cell with the priority i;

[0048] The target cell with the priority i is placed in the target cell area in the target cell column.

[0049] In a possible implementation manner, the device further includes:

[0050] An updating module is used to update the location information of the target unit with priority i to the location information corresponding to the target unit area.

[0051] In a third aspect, an embodiment of the present application provides a computing device, comprising: at least one memory for storing programs; and at least one processor for executing the programs stored in the memory, wherein when the program stored in the memory is executed, the processor is used to execute the method provided in the first aspect or any possible implementation of the first aspect.

[0052] In a fourth aspect, an embodiment of the present application provides a layout device for an FPGA, characterized in that the device runs computer program instructions to execute the method provided in the first aspect or any possible implementation of the first aspect. Exemplarily, the device may be a chip or a processor.

[0053] In one example, the device may include a processor, which may be coupled to a memory, read instructions in the memory, and execute the method provided in the first aspect or any possible implementation of the first aspect according to the instructions. The memory may be integrated in a chip or a processor, or may be independent of the chip or the processor.

[0054] In a fifth aspect, an embodiment of the present application provides a computer storage medium, in which instructions are stored. When the instructions are executed on a computer, the computer executes the method provided in the first aspect or any possible implementation of the first aspect.

[0055] The FPGA layout method, device, equipment and storage medium provided in the embodiment of the present application further legalize the target units of the same type after the initial layout of the FPGA. Among them, the priority of each target unit in the target area (that is, each target unit in the unit column) is determined, and the target unit is selected based on the position information of each target unit, so that each target unit in the target area satisfies the position constraint condition (that is, each target unit in the target area is placed in the unit column), thereby ensuring that the performance of the FPGA meets the requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 This is a schematic diagram of a design flow of an FPGA provided in an embodiment of the present application;

[0057] Figure 2 It is a schematic diagram of the internal structure of an FPGA provided in an embodiment of the present application;

[0058] Figure 3 is a schematic diagram of a cell column in an FPGA provided in an embodiment of the present application;

[0059] Figure 4 is a schematic diagram of an area in an FPGA provided in an embodiment of the present application;

[0060] Figure 5 is a schematic diagram of another region in an FPGA provided in an embodiment of the present application;

[0061] Figure 6 It is a flow chart of a FPGA layout method provided in an embodiment of the present application;

[0062] Figure 7 is a schematic diagram of another placement position of a target unit provided in an embodiment of the present application;

[0063] Figure 8 It is a schematic diagram of a process of calculating the cost value of a unit column provided in an embodiment of the present application;

[0064] Fig. 9 This is a schematic diagram of the structure of an FPGA layout device provided in an embodiment of the present application.

[0065] Fig.10 It is a structural diagram of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0066] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0067] In the description of the embodiments of the present application, words such as "exemplary", "for example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary", "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary", "for example" or "for example" is intended to present related concepts in a concrete way.

[0068] In the description of the embodiments of the present application, the term "and / or" is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, B exists alone, and A and B exist at the same time. In addition, unless otherwise specified, the term "multiple" means two or more. For example, multiple systems refers to two or more systems, and multiple terminals refers to two or more terminals.

[0069] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. The terms "include", "comprises", "has" and their variations all mean "including but not limited to", unless otherwise specifically emphasized.

[0070] like Figure 1As shown in the figure, the FPGA design process includes design definition, code implementation, functional simulation, logic synthesis, pre-simulation, layout and routing, post-simulation and board-level testing. Among them, the design definition stage mainly carries out preparatory work such as solution verification, system design and FPGA selection. According to the task requirements, evaluate the indicators and complexity of the system, weigh the working speed and the resources and cost of the chip itself, and choose a reasonable design scheme and appropriate device type; the code implementation stage is to express the divided functional modules in hardware description language; the functional simulation stage is to verify the logic function of the circuit designed by the user before compilation; the logic synthesis stage is to convert the language description of the high-level abstraction level into a lower-level circuit structure, that is, to convert the circuit logic described by the hardware description language into the interconnection relationship of basic logic units such as AND gates, OR gates, NOT gates, triggers, etc.; the pre-simulation stage is to annotate the standard delay file generated by synthesis into the comprehensive simulation model; the layout and routing stage is the process of determining the position and connection information of the gate in the gate-level netlist; layout and routing is sometimes also called implementation and layout and routing, which configures the gate-level connection relationship in the logic netlist to the inherent hardware structure inside the FPGA; post-simulation is also called timing simulation, which is to annotate the delay information of layout and routing into the design netlist to detect whether there are timing violations. All of the above stages are the process of using FPGA design software to run on computing devices. FPGA design cannot just be simulated on a computing device, but must eventually be applied on a circuit board. Therefore, board-level testing of the FPGA is required, that is, downloading the data files (bit data stream files) generated by the FPGA design software to the FPGA for actual testing.

[0071] Among them, FPGA includes various units, such as programmable logic block (PLB) / (Configurable Logic Block, CLB), digital signal processor (DSP), I / O and embedded memory (EMB) and other logic blocks. Figure 2As shown, the layout of FPGA usually has multiple cell columns, for example, cell column 201 (P / C) of PLB / CLB, cell column 202 (D) of DSP, cell column 203 (I / O) of I / O and cell column 204 (E) of EMB. In FPGA, the number of PLB / CLB is large, so the cell column 201 of PLB / CLB is arranged closely, that is, the distance between the cell columns of multiple PLB / CLB is close. However, the number of units such as DSP or EMB is small, so the corresponding column arrangement is relatively sparse, that is, the distance between the cell columns of multiple DSP or the distance between the cell columns of multiple EMB is far. In the process of using FPGA design software to layout and route FPGA, each unit is extended from the position of the center point to the cell column to which each unit belongs through a certain pulling force. In this process, the pulling force is small, and the cell columns of PLB / CLB are relatively dense. Therefore, when PLB / CLB meets the position constraint and FPGA meets the timing constraint, FPGA design software will exit the layout of this FPGA. However, due to the sparse density between the cell columns of DSP, EMB and other units, after the layout of this FPGA is completed, there are still a lot of DSP or EMB that do not meet the position constraints, so the performance of the FPGA after layout cannot meet the requirements. Figure 3 As shown in FIG. 1 , a large number of DSPs are not in the unit columns of DSPs, but between the unit columns of DSPs. It should be noted that Figure 2 and Figure 3 It is only for the convenience of describing the solution clearly and is not the internal structure of the actual FPGA.

[0072] Based on this, an embodiment of the present application provides an FPGA layout method, apparatus, device and storage medium, which legalizes the target cells with sparse cell columns again after the FPGA is laid out, so that the target cells meet the position constraints and ensure that the performance of the FPGA meets the requirements.

[0073] It is understandable that the target unit provided in the embodiment of the present application may be a unit with a sparser unit column corresponding to a unit such as a DSP or an EMB. In addition, the unit column of the target unit can divide the internal area of ​​the FPGA. The area is relative to the unit column. The area divided by the unit column to which one type of unit belongs is different from the area divided by the unit column to which another type of unit belongs, and the area divided by the unit column to which one type of unit belongs may include the unit column to which another type of unit belongs. For example, Figure 4 As shown, the area 41 is relative to the unit columns to which multiple DSPs belong, and the area 41 includes the unit columns to which I / Os belong, the unit columns to which PLBs belong, etc. Figure 5As shown, the area 51 is relative to the cell column to which multiple EMBs belong, and the area 51 includes the cell column to which DSPs belong, etc. The cell area refers to the area in the cell column where cells are placed, for example Figure 4 Area 42 and Figure 5 Area 52 in.

[0074] Figure 6 FIG. 1 is a flow chart of a FPGA layout method provided in an embodiment of the present application. Figure 6 As shown, the FPGA layout method provided in the embodiment of the present application includes:

[0075] S601: Acquire initial layout information of the FPGA, where the initial layout information includes a plurality of cell columns for placing target cells of the same type, location information of the plurality of target cells, and the number of wire nets connected to each target cell.

[0076] The initial layout information of the FPGA refers to the initial layout information after the FPGA is initially laid out and routed to meet the timing constraints and the PLB / CLB meets the location constraints. The initial layout information can be generated after the FPGA is initially laid out, and the initial layout information can be cached in the memory of the computing device. When some cells of the laid-out FPGA are legalized, the initial layout information can be read from the memory of the computing device. The target cell refers to a cell that is sparsely arranged between the cell columns to which the cell belongs, for example, Figure 3 As shown, the cell columns of units such as DSP or EMB are sparsely arranged, and DSP or EMB can be the target unit.

[0077] S602: Determine area information of at least one target area according to the plurality of unit columns.

[0078] Here, the cell columns described in this solution are all cell columns that place cells of the same type. Cell columns to which cells of the same type belong can divide the interior of the FPGA into at least one target area, as described above. Figure 4 and Figure 5 The description of the target area is omitted here. Each target area corresponds to a region information, wherein the region information is used to indicate the position of the target area. For example, the region information may be the position coordinates of the four vertices of the target area. Here, a rectangular coordinate system may be established with any point in the structural area of ​​the FPGA as the origin, thereby determining the position coordinates of the target area.

[0079] S603: Determine the number of target units in each target area of ​​at least one target area according to the location information of the plurality of target units and the area information of each of the at least one target area.

[0080] The target cells in the target area are the target cells to be optimized, that is, the target cells in the target area need to be legalized so that the target cells in the target area meet the position constraints (the target cells are all in the cell class). Figure 3 The DSP unit that is not placed in the unit column corresponding to the DSP is the target unit to be optimized. The position information of the target unit can be the coordinates of the target unit in the entire structural area of ​​the FPGA. A rectangular coordinate system can be established with any point in the structural area of ​​the FPGA as the origin to determine the position information of the target unit, and no further description is given in detail. It should be noted that the coordinates mentioned in the embodiments of the present application are all coordinates calculated under the same coordinate system.

[0081] S604: Determine the position information of the legalization center point according to the number of target units in each target area.

[0082] The legalization center point is determined based on the number of target units in each target area. The center point of the target area with the largest number of target units can be determined as the legalization center point. The coordinates of the legalization center point in the entire FPGA area are calculated to obtain the position information of the legalization center point.

[0083] S605: Determine the priority of each target unit in each target area according to the number of target units in each target area, the location information of multiple target units, the location information of the legalized center point, and the number of wire networks connected to each target unit.

[0084] Here, the priority of the target area can be determined first, and then the priority of the target unit to be optimized (for the convenience of description, the target units in the target area hereinafter are referred to as target units to be optimized) can be determined. Among them, the target area where the legalization center point is located can be the target area with the highest priority. For the convenience of description, 1, 2, 3...N are used to represent the level of priority, where 1 represents the highest priority and N represents the lowest priority. N is a positive integer. Then, the target area with the next highest priority is determined from the adjacent areas of the target area where the legalization center point is located. Among them, the target area with the largest number of target units to be optimized in the adjacent target areas of the target area where the legalization center point is located can be taken as an area with a priority of 2. Then, a target area with a priority of 3 is determined from the adjacent target areas of the target area with a priority of 2, and so on. By analogy, the priorities of all target areas are determined.

[0085] After determining the priority of each target area, the priority of the target unit to be optimized is determined according to the size of the target area priority, the location information of each target unit to be optimized, the location information of the legalization center point, and the number of wire nets connected to the target unit to be optimized. That is, the influencing factors of the priority of the target unit to be optimized include the priority of the target area where the target unit to be optimized is located, the number of wire nets connected to the target unit to be optimized, and the distance between the target unit to be optimized and the legalization center point. Among them, the greater the priority of the target area where the target unit to be optimized is located, the greater the priority of the target unit to be optimized; the greater the number of wire nets connected to the target unit to be optimized, the greater the priority of the target unit to be optimized. The smaller the distance from the legalization center point, the higher the priority of the target unit to be optimized.

[0086] Specifically, the distance between the target unit to be optimized and the legalization center point can be calculated based on the location information of the target unit to be optimized and the location information of the legalization center point. Then, the priority of the target area where the target unit to be optimized is located, the number of wire networks connected to the target unit to be optimized, and the distance between the target unit to be optimized and the legalization center point are weighted and summed to obtain the priority evaluation value of each target unit to be optimized. According to the size of the priority evaluation value, the priority of the target unit to be optimized is determined.

[0087] S606: According to the position information of the multiple target cells, the target cells in each target area are placed in a cell column in descending order of their respective priorities, so that the target cells in each target area meet the position constraint conditions for laying out the FPGA; wherein, for a target cell with a priority of i, after the target cell with a priority of i is placed in the cell column, the position of the target cell in the cell column is adjusted, and according to the position information of the multiple target cells and the position information of the target cells in the cell column after the position adjustment, a target cell area for placing the target cell with a priority of i is determined from the target cell column.

[0088] When arranging the target cells to be optimized, the target cells to be optimized can be arranged in descending order of priority, so that each target cell is placed in the cell column, such as Figure 7 As shown, each DSP to be optimized is placed in the unit column to which the DSP belongs.

[0089] S606 is described in detail below with reference to the target unit to be optimized having a priority level i.

[0090] The layout resource of FPGA can be a resource table, which records the location information of all target cells in FPGA, the number of cell areas in each cell column where no target cells are placed, etc. Each time a target cell to be optimized is placed in a cell column, some information recorded in the resource table needs to be updated. For example, the number of cell areas in each cell column where no target cells are placed, the label information of the target cell to be optimized after placement is changed from to be optimized to already placed, etc.

[0091] In S606, first, according to the number of cell regions in the plurality of cell columns after the target cells to be optimized with priorities 1 to i-1 are placed in the cell column, at least one cell column in which the target cell to be optimized with priority i can be placed is determined; then, the target cell with priority i is placed in one of the at least one cell column; then, the positions of all the target cells in the cell column are adjusted. Finally, according to the position information of the target cell and the position information of the target cells in the cell column after the position adjustment, the target cell region for placing the target cell with priority i is determined from the target cell column.

[0092] In some embodiments, each time a target unit to be optimized is placed, it is necessary to determine the cost value of the target unit to be optimized after being placed in the unit column. The position of the target unit to be optimized in the unit column when the cost value is minimum is the final position of the unit to be optimized. Specifically, based on the position information of the multiple target units and the position information of the target units in the unit column after the positions are adjusted, the cost value of the unit column after the positions of the target units in the unit column are calculated.

[0093] Then, based on the cost value of each cell column where the target cell with priority i can be placed, determine the target cell column where the target cell with priority i is finally placed and the target cell area in the target cell column, the target cell area being the area in the target cell column where the target cell is placed. Wherein, the target cell column where the target cell with priority i is placed and the target cell area in the target cell column for placing the target cell with priority i can be determined from the at least one cell column according to the cost value of at least one cell column. The target cell with priority i is placed in the target cell area in the target cell column.

[0094] For example, Figure 8As shown, after the target unit D1, the target unit D2 and the target unit D3 are all placed in the unit column 80, the target unit D4 needs to be placed. After the target unit D4 is placed in the unit column 80, the positions of the target units placed in the unit column 80 are adjusted. Here, the target units placed in the unit column 80 include the target unit D1, the target unit D2, the target unit D3 and the target unit D4. The positions of the target units placed in the unit column 80 are adjusted multiple times, and according to the initial position information and the position information after the adjustment of the target unit D1, the target unit D2, the target unit D3 and the target unit D4, the cost value of the unit column 80 after each adjustment is calculated, and the position of each placed target unit when the cost value is the minimum is determined as the final position of each placed target unit.

[0095] In the embodiment of the present application, after the initial layout of the FPGA, the target unit to be optimized is further legalized according to the priority of the target unit to be optimized, so that the target unit to be optimized satisfies the position constraint condition, thereby ensuring that the performance of the FPGA meets the requirements and reducing the use of wiring resources.

[0096] Fig. 9 FIG. 1 is a schematic diagram of a structure of an FPGA layout device provided in an embodiment of the present application. Fig. 9 As shown, the FPGA layout device provided in the embodiment of the present application may include:

[0097] An acquisition module 901 is used to acquire initial layout information of the FPGA, wherein the initial layout information includes a plurality of cell columns for placing target cells of the same type, location information of the plurality of target cells, and the number of wire nets connected to each target cell;

[0098] A first determination module 902, configured to determine area information of at least one target area according to the plurality of unit columns;

[0099] A second determining module 903 is used to determine the number of target units in each target area of ​​the at least one target area according to the location information of the plurality of target units and the area information of each of the at least one target area;

[0100] A third determination module 904 is used to determine the position information of the legalization center point according to the number of target units in each target area;

[0101] A fourth determination module 905, configured to determine the priority of each target unit in each target area according to the number of target units in each target area, the location information of the multiple target units, the location information of the legalization center point, and the number of wire nets connected to each target unit;

[0102] A placement module 906 is used to place the target cells in each target area in a cell column in descending order of priority of the target cells in each target area according to the position information of the multiple target cells, so that the target cells in each target area meet the position constraint conditions of the FPGA layout;

[0103] For a target cell with a priority of i, after placing the target cell with a priority of i in a cell column, adjust the position of the target cell in the cell column, and determine a target cell area for placing the target cell with a priority of i from the target cell column based on the position information of the multiple target cells and the position information of the target cells in the cell column after the adjustment.

[0104] In a possible implementation, the fourth determining module 905 is configured to:

[0105] Determine the distance between the target unit in each target area and the legalization center point according to the position information of the target unit in each target area and the position information of the legalization center point in the position information of the multiple target units;

[0106] Determining the priority of each target area according to the number of target units in each target area;

[0107] The priority of the target unit in each target area is determined according to the priority of each target area, the distance between the target unit in each target area and the legalization center point, and the number of wire meshes connected to the target unit in each target area.

[0108] In a possible implementation, the placement module 906 is used to:

[0109] Determine the number of cell regions in which the target cells are not placed in the plurality of cell columns after the target cells with priorities 1 to i-1 in the at least one target region are placed in the cell column;

[0110] Determine, according to the number of cell regions in which the target cell is not placed in each of the plurality of cell columns, at least one cell column in which the target cell with the priority i can be placed;

[0111] placing the target cell with priority i in a cell column of the at least one cell column;

[0112] Adjust the position of the target cell within the cell column.

[0113] In a possible implementation, the placement module 906 is used to:

[0114] Calculating a cost value of the unit column after adjusting the positions of the target units in the unit column according to the position information of the plurality of target units and the position information of the target units in the unit column after adjusting the positions;

[0115] According to the cost value of at least one cell column, determining from the at least one cell column a target cell column in which the target cell with the priority i is placed and a target cell region in the target cell column for placing the target cell with the priority i;

[0116] The target cell with the priority i is placed in the target cell area in the target cell column.

[0117] In a possible implementation manner, the device further includes:

[0118] An updating module is used to update the location information of the target unit with priority i to the location information corresponding to the target unit area.

[0119] A computing device provided in an embodiment of the present application is introduced below.

[0120] Fig.10 Schematic diagram of a computing device provided in an embodiment of the present application. Fig.10 As shown, the computing device provided in the embodiment of the present application can be used to implement the integrated circuit design method described in the above method embodiment.

[0121] The computing device may include a processor 1001 and a memory 1002 storing computer program instructions.

[0122] Specifically, the processor 1001 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0123] The memory 1002 may include a large capacity memory for data or instructions. By way of example and not limitation, the memory 1002 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive or a combination of two or more of these. In appropriate cases, the memory 1002 may include a removable or non-removable (or fixed) medium. In appropriate cases, the memory 1002 may be inside or outside the integrated gateway disaster recovery device. In a specific embodiment, the memory 1002 is a non-volatile solid-state memory.

[0124] The memory may include read-only memory (ROM), random access memory (RAM), magnetic disk storage media devices, optical storage media devices, flash memory devices, electrical, optical or other physical / tangible memory storage devices. Thus, typically, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the methods in the present application.

[0125] The processor 1001 implements any one of the integrated circuit design methods in the above embodiments by reading and executing computer program instructions stored in the memory 1002 .

[0126] In one example, the electronic device may further include a communication interface 1010 and a bus 1010. Fig.10 As shown, the processor 1001, the memory 1002, and the communication interface 1010 are connected via a bus 1010 and communicate with each other.

[0127] The communication interface 1010 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0128] Bus 1010 includes hardware, software or both, and the parts of electronic equipment are coupled to each other.For example, but not limitation, bus may include accelerated graphics port (AGP) or other graphics bus, enhanced industrial standard architecture (EISA) bus, front side bus (FSB), hypertransport (HT) interconnection, industrial standard architecture (ISA) bus, infinite bandwidth interconnection, low pin count (LPC) bus, memory bus, micro channel architecture (MCA) bus, peripheral component interconnection (PCI) bus, PCI-Express (PCI-X) bus, serial advanced technology attachment (SATA) bus, video electronics standard association local (VLB) bus or other suitable bus or two or more of these combinations. In appropriate cases, bus 1010 may include one or more buses. Although the present application embodiment describes and shows a specific bus, the application considers any suitable bus or interconnection.

[0129] In addition, in combination with the above embodiments, the embodiments of the present application may provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when the computer program instructions are executed by a processor, any one of the integrated circuit design methods in the above embodiments is implemented.

[0130] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0131] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0132] The above reference is according to the method of the embodiment of the present application, the flow chart of the device (system) and the computer program product and / or the block diagram described various aspects of the present application.It should be understood that each square box in the flow chart and / or the block diagram and the combination of each square box in the flow chart and / or the block diagram can be realized by computer program instructions.These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the realization of the function / action specified in one or more square boxes of the flow chart and / or the block diagram.Such a processor can be but is not limited to a general-purpose processor, a special-purpose processor, a special application processor or a field programmable logic circuit.It can also be understood that each square box in the block diagram and / or the flow chart and the combination of the square boxes in the block diagram and / or the flow chart can also be realized by the dedicated hardware that performs the specified function or action, or can be realized by the combination of dedicated hardware and computer instructions.

[0133] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. A layout method for FPGA, It is characterized in that The method comprises: Acquire initial layout information of the FPGA, wherein the initial layout information includes a plurality of cell columns for placing target cells of the same type, position information of the plurality of target cells, and the number of wire nets connected to each target cell; Determining area information of at least one target area according to the plurality of unit columns; Determining the number of target units in each target area of ​​the at least one target area according to the location information of the plurality of target units and the area information of each of the at least one target area; Determining the position information of the legalization center point according to the number of target units in each target area; Determine the priority of each target unit in each target area according to the number of target units in each target area, the location information of the multiple target units, the location information of the legalization center point, and the number of wire nets connected to each target unit; According to the position information of the plurality of target cells, the target cells in each target area are sequentially placed in a cell column in descending order of priority of the target cells in each target area, so that the target cells in each target area meet the position constraint conditions of the FPGA layout; For a target cell with a priority of i, after placing the target cell with a priority of i in a cell column, adjust the position of the target cell in the cell column, and determine a target cell area for placing the target cell with a priority of i from the target cell column based on the position information of the multiple target cells and the position information of the target cells in the cell column after the adjustment.

2. The method according to claim 1, It is characterized in that Determining the priorities of the target units in each target area according to the number of target units in each target area, the location information of the multiple target units, the location information of the legalized center point, and the number of wire nets connected to each target unit includes: Determine the distance between the target unit in each target area and the legalization center point according to the position information of the target unit in each target area and the position information of the legalization center point in the position information of the multiple target units; Determining the priority of each target area according to the number of target units in each target area; The priority of the target unit in each target area is determined according to the priority of each target area, the distance between the target unit in each target area and the legalization center point, and the number of wire meshes connected to the target unit in each target area.

3. The method according to claim 1, It is characterized in that After placing the target cell with the priority i in the cell column, adjusting the position of the target cell in the cell column includes: Determine the number of cell regions in which the target cells are not placed in the plurality of cell columns after the target cells with priorities 1 to i-1 in the at least one target region are placed in the cell column; Determine, according to the number of cell regions in which the target cell is not placed in each of the plurality of cell columns, at least one cell column in which the target cell with the priority i can be placed; placing the target cell with priority i in a cell column of the at least one cell column; Adjust the position of the target cell within the cell column.

4. The method according to claim 3, It is characterized in that The determining, from the target cell column, a target cell area for placing the target cell with priority i according to the position information of the plurality of target cells and the position information of the target cells in the cell column after the positions are adjusted, comprises: Calculating a cost value of the unit column after adjusting the positions of the target units in the unit column according to the position information of the plurality of target units and the position information of the target units in the unit column after adjusting the positions; According to the cost value of at least one cell column, determining from the at least one cell column a target cell column in which the target cell with the priority i is placed and a target cell region in the target cell column for placing the target cell with the priority i; The target cell with the priority i is placed in the target cell area in the target cell column.

5. The method according to any one of claims 1 to 4, It is characterized in that The method further comprises: The location information of the target unit with the priority i is updated to the location information corresponding to the target unit area.

6. A layout device for FPGA, It is characterized in that The device comprises: An acquisition module is used to acquire initial layout information of the FPGA, wherein the initial layout information includes a plurality of cell columns for placing target cells of the same type, position information of the plurality of target cells, and the number of wire nets connected to each target cell; A first determination module, configured to determine area information of at least one target area according to the plurality of unit columns; A second determining module, configured to determine the number of target units in each target area of ​​the at least one target area according to the location information of the plurality of target units and the area information of each of the at least one target area; A third determination module is used to determine the position information of the legalization center point according to the number of target units in each target area; A fourth determination module, configured to determine the respective priorities of the target units in each target area according to the number of target units in each target area, the location information of the multiple target units, the location information of the legalization center point, and the number of wire nets connected to each target unit; A placement module, for placing the target cells in each target area in a cell column in order from large to small according to the position information of the plurality of target cells, so that the target cells in each target area meet the position constraint conditions of the FPGA layout; For a target cell with a priority of i, after placing the target cell with a priority of i in a cell column, adjust the position of the target cell in the cell column, and determine a target cell area for placing the target cell with a priority of i from the target cell column based on the position information of the multiple target cells and the position information of the target cells in the cell column after the adjustment.

7. The device according to claim 6, It is characterized in that The fourth determining module is used to: Determine the distance between the target unit in each target area and the legalization center point according to the position information of the target unit in each target area and the position information of the legalization center point in the position information of the multiple target units; Determining the priority of each target area according to the number of target units in each target area; The priority of the target unit in each target area is determined according to the priority of each target area, the distance between the target unit in each target area and the legalization center point, and the number of wire meshes connected to the target unit in each target area.

8. The device according to claim 6, It is characterized in that The placement module is used to: Determine the number of cell regions in which the target cells are not placed in the plurality of cell columns after the target cells with priorities 1 to i-1 in the at least one target region are placed in the cell column; Determine, according to the number of cell regions in which the target cell is not placed in each of the plurality of cell columns, at least one cell column in which the target cell with the priority i can be placed; placing the target cell with priority i in a cell column of the at least one cell column; Adjust the position of the target cell within the cell column.

9. The device according to claim 8, It is characterized in that The placement module is used to: Calculating a cost value of the unit column after adjusting the positions of the target units in the unit column according to the position information of the plurality of target units and the position information of the target units in the unit column after adjusting the positions; According to the cost value of at least one cell column, determining from the at least one cell column a target cell column in which the target cell with the priority i is placed and a target cell region in the target cell column for placing the target cell with the priority i; The target cell with the priority i is placed in the target cell area in the target cell column.

10. The device according to any one of claims 6 to 9, It is characterized in that The device also includes: An updating module is used to update the location information of the target unit with priority i to the location information corresponding to the target unit area.

Images