A digital-analog hybrid storage and computing integrated device

Abstract

The present invention provides a digital-analog hybrid storage and computing integrated device, comprising: a storage access interface, an analog in-memory computing array, a digital in-memory computing array, and a computing result synthesis unit; wherein: the storage access interface is respectively connected to the analog in-memory computing array and the digital in-memory computing array; the computing result synthesis unit is respectively connected to the analog in-memory computing array and the digital in-memory computing array; and is used to respectively receive a first computing result of the analog in-memory computing array and a second computing result of the digital in-memory computing array, and fuse the first computing result and the second computing result to obtain a fused computing result. The digital-analog hybrid storage and computing integrated device provided by the embodiment of the present invention can improve data computing efficiency.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a digital-analog hybrid storage and computing integrated device. Background Art

[0002] In recent years, in order to solve the challenges of device size miniaturization and the bottleneck of von Neumann computing architecture, in-memory computing (or also known as integrated storage and computing, memory computing, etc.) technology has received widespread attention. Its basic idea is to integrate storage and computing on the same chip, so as to directly use the memory for calculation, reduce data transmission between the memory and the processor, reduce power consumption and improve performance.

[0003] The storage-computing integrated computing technology is currently considered to be one of the efficient hardware solutions for solving the real-time intelligent processing of big data in the post-Moore era, and is also one of the current efficient implementation plans for deep learning neural networks. For deep learning neural network applications, the most frequent operation is the multiply-accumulate operation (MAC for short). Through in-memory computing, MAC operations can be efficiently implemented, thereby greatly improving performance while reducing power consumption. The existing technical solutions are mainly divided into analog storage-computing integrated and digital storage-computing integrated, which perform storage-computing integrated independently, making data calculation efficiency inefficient. Summary of the invention

[0004] In response to the problems in the prior art, an embodiment of the present invention provides an integrated digital-analog hybrid storage and computing device that can at least partially solve the problems in the prior art.

[0005] On the one hand, the present invention proposes a digital-analog hybrid storage and computing integrated device, comprising a storage access interface, an analog in-memory computing array, a digital in-memory computing array, and a computing result synthesis unit; wherein:

[0006] The storage access interface is connected to the analog in-memory computing array and the digital in-memory computing array respectively;

[0007] Used to receive input weight data, and split the weight data according to high bits and low bits respectively to obtain high bit group data and low bit group data;

[0008] The analog in-memory computing array is used to receive the digital input signal and the low-bit bit group data, perform data processing on the digital input signal and the low-bit bit group data, and obtain a first computing result;

[0009] The digital in-memory calculation array is used to receive the digital input signal and the high-bit bit group data, perform data processing on the digital input signal and the high-bit bit group data, and obtain a second calculation result;

[0010] The calculation result synthesis unit is connected to the analog in-memory calculation array and the digital in-memory calculation array respectively;

[0011] Used to receive the first calculation result and the second calculation result respectively, and fuse the first calculation result and the second calculation result to obtain a fused calculation result.

[0012] The analog in-memory computing array is specifically used for:

[0013] A digital input signal and the low bit group data are received, the digital input signal is converted into an analog input signal, analog calculation is performed on the analog input signal and the low bit group data, and the analog calculation result is digitally converted to obtain a first calculation result.

[0014] Wherein, the analog in-memory computing array has a built-in digital-to-analog signal converter and an analog-to-digital signal converter;

[0015] Correspondingly, the digital input signal is converted into an analog input signal by the digital-to-analog signal converter, and the analog calculation result is digitally converted by the analog-to-digital signal converter to obtain a first calculation result.

[0016] Wherein, the digital in-memory computing array has a built-in digital accumulator;

[0017] Correspondingly, the digital accumulator performs digital calculation on the digital input signal and the high-bit bit group data to obtain a second calculation result.

[0018] Wherein, the digital-analog hybrid storage and computing integrated device also includes a storage and computing integrated data interface;

[0019] The storage-computation integrated data interface is connected to the calculation result synthesis unit and is used to send the fused calculation result to the data receiver.

[0020] Wherein, the digital-analog hybrid storage and computing integrated device further includes a control circuit;

[0021] The control circuit is respectively connected to the storage access interface, the analog in-memory computing array, the digital in-memory computing array, the computing result synthesis unit and the storage-computation integrated data interface;

[0022] Used to receive control signals and control the storage access interface, the analog in-memory computing array, the digital in-memory computing array, the calculation result synthesis unit and the storage and computing integrated data interface according to the control signals.

[0023] The data processing method using the above-mentioned digital-analog hybrid storage and computing integrated device includes:

[0024] The weight data is split according to the high bit and the low bit respectively to obtain the high bit group data and the low bit group data;

[0025] Performing data processing on the digital input signal and the low bit group data to obtain a first calculation result; performing data processing on the digital input signal and the high bit group data to obtain a second calculation result;

[0026] The first calculation result and the second calculation result are fused to obtain a fused calculation result.

[0027] Wherein, the data processing method further includes:

[0028] The fusion calculation results are sent to the data receiver.

[0029] The weight data is split according to high bits and low bits respectively to obtain high bit group data and low bit group data, including:

[0030] The weight data is evenly divided according to the high bit and the low bit, respectively, to obtain high bit group data and low bit group data with equal number of bits.

[0031] Wherein, a multiplication and addition operation is performed between the weight data and the digital input signal.

[0032] The digital-analog hybrid storage and computing integrated device provided in an embodiment of the present invention comprises a storage access interface, an analog in-memory computing array, a digital in-memory computing array and a computing result synthesis unit; wherein: the storage access interface is respectively connected to the analog in-memory computing array and the digital in-memory computing array; used to receive input weight data, and split the weight data according to high bits and low bits respectively to obtain high bit group data and low bit group data; the analog in-memory computing array is used to receive a digital input signal and the low bit group data, perform data processing on the digital input signal and the low bit group data, and obtain a first computing result; the digital in-memory computing array is used to receive a digital input signal and the high bit group data, perform data processing on the digital input signal and the high bit group data, and obtain a second computing result; the computing result synthesis unit is respectively connected to the analog in-memory computing array and the digital in-memory computing array; used to respectively receive the first computing result and the second computing result, and fuse the first computing result and the second computing result to obtain a fused computing result, which can improve data computing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0034] Figure 1 It is a schematic diagram of the structure of a digital-analog hybrid storage and computing integrated device provided by an embodiment of the present invention.

[0035] Figure 2 It is a schematic diagram of the structure of an analog in-memory computing array provided by one embodiment of the present invention.

[0036] Figure 3 It is a schematic diagram of the structure of a digital-analog hybrid storage and computing integrated device provided by another embodiment of the present invention.

[0037] Figure 4 It is a schematic diagram of the digital in-memory computing array structure provided by one embodiment of the present invention.

[0038] Figure 5 It is a schematic diagram of the structure of a digital-analog hybrid storage and computing integrated device provided by another embodiment of the present invention.

[0039] Figure 6 It is a schematic diagram of the structure of a digital-analog hybrid storage and computing integrated device provided by another embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention more clear, the embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, in the absence of conflict, the embodiments in this application and the features in the embodiments can be combined with each other arbitrarily.

[0041] Figure 1 FIG. 1 is a schematic diagram of a structure of a digital-analog hybrid storage and computing integrated device provided by an embodiment of the present invention. Figure 1 As shown, the digital-analog hybrid storage and computing integrated device provided by the embodiment of the present invention includes: a storage access interface 1, an analog in-memory computing array 2, a digital in-memory computing array 3 and a computing result synthesis unit 4; wherein:

[0042] The storage access interface 1 is connected to the analog in-memory computing array 2 and the digital in-memory computing array 3 respectively;

[0043] Used to receive input weight data, and split the weight data according to high bits and low bits respectively to obtain high bit group data and low bit group data;

[0044] The analog in-memory computing array 2 is used to receive the digital input signal and the low-bit bit group data, perform data processing on the digital input signal and the low-bit bit group data, and obtain a first computing result;

[0045] The digital in-memory calculation array 3 is used to receive the digital input signal and the high-bit bit group data, perform data processing on the digital input signal and the high-bit bit group data, and obtain a second calculation result;

[0046] The calculation result synthesis unit 4 is connected to the analog in-memory calculation array and the digital in-memory calculation array respectively;

[0047] Used to receive the first calculation result and the second calculation result respectively, and fuse the first calculation result and the second calculation result to obtain a fused calculation result.

[0048] like Figure 2 As shown, the simulation memory computing array 2 is described as follows:

[0049] The analog in-memory computing array 2 implements computing tasks based on analog signal operations. Common storage media include RRAM, MRAM, SRAM, and Flash.

[0050] like Figure 2 As shown, the external digital input signal needs to be converted into an analog input signal by DAC first, and the analog input signal is used as the input of the analog in-memory calculation array 2. The analog in-memory calculation array 2 includes a storage calculation unit, and its medium and structure are various, which are not limited here. The analog in-memory calculation array 2 implements multiplication and addition calculations and outputs the calculation results of the analog quantity. Finally, the analog calculation results are converted into digital signals by ADC, and the first calculation result is obtained and output.

[0051] like Figure 3 As shown, the analog in-memory computing array 2 is specifically used for:

[0052] A digital input signal and the low bit group data are received, the digital input signal is converted into an analog input signal, analog calculation is performed on the analog input signal and the low bit group data, and the analog calculation result is digitally converted to obtain a first calculation result.

[0053] The analog in-memory computing array 2 has a built-in digital-to-analog signal converter and an analog-to-digital signal converter;

[0054] Correspondingly, the digital input signal is converted into an analog input signal by the digital-to-analog signal converter, and the analog calculation result is digitally converted by the analog-to-digital signal converter to obtain a first calculation result.

[0055] It should be noted that, refer to Figure 2 , you can Figure 2 The DACs and ADCs in the chip are built into the storage / computation array.

[0056] like Figure 4 As shown, the digital in-memory computing array 3 is described as follows:

[0057] The digital in-memory computing array 3 is mainly implemented by SRAM storage media, but other storage media are not limited here. Figure 4 As shown, the digital input signal is directly input into the digital in-memory calculation array 3 in the form of a digital signal, and the digital in-memory calculation array 3 also performs calculations in the form of digital signals. The digital in-memory calculation array 3 includes structures such as logic gates and addition trees to realize digital multiplication and addition operations. The calculation results are accumulated by the digital accumulator at the bottom to realize a complete multiplication and addition operation.

[0058] The digital in-memory computing array 3 has a built-in digital accumulator;

[0059] Correspondingly, the digital accumulator performs digital calculation on the digital input signal and the high-bit bit group data to obtain a second calculation result.

[0060] It should be noted that, refer to Figure 4 , you can Figure 4 The digital accumulator is built into the digital memory calculation array 3.

[0061] In low-precision computing scenarios, the analog storage and computing solution has a good performance advantage. However, in high-precision computing scenarios, only the digital storage and computing solution can be used for calculation.

[0062] However, the performance of the digital storage and computing solution is limited compared to the traditional digital processing solution, and the storage density is low. Therefore, the embodiment of the present invention combines digital and analog storage and computing technologies. The high-precision computing tasks are split and processed by digital and analog storage and computing respectively, taking into account both area overhead and power consumption overhead. Figure 5 shown.

[0063] like Figure 6 As shown, further, the digital-analog hybrid storage and computing integrated device also includes a storage and computing integrated data interface 5;

[0064] The storage and calculation integrated data interface 5 is connected to the calculation result synthesis unit 4, and is used to send the fusion calculation result to the data recipient, and the data recipient can be specified according to actual needs.

[0065] Furthermore, the digital-analog hybrid storage and computing integrated device further includes a control circuit;

[0066] The control circuit is respectively connected to the storage access interface 1, the analog in-memory computing array 2, the digital in-memory computing array 3, the calculation result synthesis unit 4 and the storage and computing integrated data interface 5;

[0067] Used to receive control signals and control the storage access interface 1, the analog in-memory computing array 2, the digital in-memory computing array 3, the calculation result synthesis unit 4 and the storage and computing integrated data interface 5 according to the control signals.

[0068] The digital-analog hybrid storage and computing integrated device provided in an embodiment of the present invention comprises a storage access interface, an analog in-memory computing array, a digital in-memory computing array and a computing result synthesis unit; wherein: the storage access interface is respectively connected to the analog in-memory computing array and the digital in-memory computing array; used to receive input weight data, and split the weight data according to high bits and low bits respectively to obtain high bit group data and low bit group data; the analog in-memory computing array is used to receive a digital input signal and the low bit group data, perform data processing on the digital input signal and the low bit group data, and obtain a first computing result; the digital in-memory computing array is used to receive a digital input signal and the high bit group data, perform data processing on the digital input signal and the high bit group data, and obtain a second computing result; the computing result synthesis unit is respectively connected to the analog in-memory computing array and the digital in-memory computing array; used to respectively receive the first computing result and the second computing result, and fuse the first computing result and the second computing result to obtain a fused computing result, which can improve data computing efficiency.

[0069] Furthermore, a data processing method using the above-mentioned digital-analog hybrid storage and computing integrated device includes:

[0070] Step S1: splitting the weight data according to the high bit and the low bit respectively to obtain the high bit group data and the low bit group data. The splitting of the weight data according to the high bit and the low bit respectively to obtain the high bit group data and the low bit group data includes:

[0071] The weight data is evenly divided according to the high bit and low bit, respectively, to obtain high bit group data and low bit group data with equal number of bits. An example is as follows:

[0072] like Figure 3As shown, when processing a computing task, a 12-bit precision multiplication operation is taken as an example. The digital input signal is a 12-bit signal, and the 12-bit weight parameter is divided into two parts. Assume that the 12-bit weight is divided into two groups of high and low bits with 6 bits and 6 bits. The high-bit group is calculated by the digital in-memory calculation array, that is, the 12-bit input is multiplied by the 6-bit high-bit weight. The low-bit group is calculated by the analog in-memory calculation array, that is, the 12-bit input is multiplied by the 6-bit low-bit weight, and the two calculation results are merged to obtain a fused calculation result.

[0073] Step S2: Process the digital input signal and the low bit group data to obtain a first calculation result; process the digital input signal and the high bit group data to obtain a second calculation result. Please refer to the above description and will not repeat it again.

[0074] Step S3: Fusing the first calculation result and the second calculation result to obtain a fused calculation result. Please refer to the above description and will not repeat it again.

[0075] Furthermore, the data processing method further includes:

[0076] The fusion calculation results are sent to the data receiver. Please refer to the above description and will not be repeated here.

[0077] Further, the weight data is split according to high bits and low bits respectively to obtain high bit group data and low bit group data, including:

[0078] The weight data is evenly divided according to the high bit and the low bit, respectively, to obtain high bit group data and low bit group data with equal bits. Please refer to the above description and do not repeat it again.

[0079] Further, the weight data and the digital input signal are multiplied and added. Please refer to the above description and no further details will be given.

[0080] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0081] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0082] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0083] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0084] In the description of this specification, the description with reference to the terms "one embodiment", "a specific embodiment", "some embodiments", "for example", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0085] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A digital-analog hybrid storage and computing integrated device, characterized in that: It includes a storage access interface, an analog in-memory computing array, a digital in-memory computing array and a computing result synthesis unit; wherein: The storage access interface is connected to the analog in-memory computing array and the digital in-memory computing array respectively; Used to receive input weight data, and split the weight data according to high bits and low bits respectively to obtain high bit group data and low bit group data; The analog in-memory computing array is used to receive the digital input signal and the low-bit bit group data, perform data processing on the digital input signal and the low-bit bit group data, and obtain a first computing result; The digital in-memory calculation array is used to receive the digital input signal and the high-bit bit group data, perform data processing on the digital input signal and the high-bit bit group data, and obtain a second calculation result; The calculation result synthesis unit is connected to the analog in-memory calculation array and the digital in-memory calculation array respectively; Used to receive the first calculation result and the second calculation result respectively, and fuse the first calculation result and the second calculation result to obtain a fused calculation result.

2. The digital-analog hybrid storage and computing integrated device according to claim 1, characterized in that: The analog in-memory computing array is specifically used for: A digital input signal and the low bit group data are received, the digital input signal is converted into an analog input signal, analog calculation is performed on the analog input signal and the low bit group data, and the analog calculation result is digitally converted to obtain a first calculation result.

3. The digital-analog hybrid storage and computing integrated device according to claim 2, characterized in that: The analog in-memory computing array has a built-in digital-to-analog signal converter and an analog-to-digital signal converter; Correspondingly, the digital input signal is converted into an analog input signal by the digital-to-analog signal converter, and the analog calculation result is digitally converted by the analog-to-digital signal converter to obtain a first calculation result.

4. The digital-analog hybrid storage and computing integrated device according to claim 3, characterized in that: The digital in-memory computing array has a built-in digital accumulator; Correspondingly, the digital accumulator performs digital calculation on the digital input signal and the high-bit bit group data to obtain a second calculation result.

5. The digital-analog hybrid storage and computing integrated device according to any one of claims 1 to 4, characterized in that: The digital-analog hybrid storage and computing integrated device also includes a storage and computing integrated data interface; The storage-computation integrated data interface is connected to the calculation result synthesis unit and is used to send the fused calculation result to the data receiver.

6. The digital-analog hybrid storage and computing integrated device according to claim 5, characterized in that: The digital-analog hybrid storage and computing integrated device also includes a control circuit; The control circuit is respectively connected to the storage access interface, the analog in-memory computing array, the digital in-memory computing array, the computing result synthesis unit and the storage-computation integrated data interface; Used to receive control signals and control the storage access interface, the analog in-memory computing array, the digital in-memory computing array, the calculation result synthesis unit and the storage and computing integrated data interface according to the control signals.

7. A data processing method using the digital-analog hybrid storage and computing integrated device as claimed in claim 1, characterized in that: include: The weight data is split according to the high bit and the low bit respectively to obtain the high bit group data and the low bit group data; Performing data processing on the digital input signal and the low bit group data to obtain a first calculation result; Performing data processing on the digital input signal and the high-bit bit group data to obtain a second calculation result; The first calculation result and the second calculation result are fused to obtain a fused calculation result.

8. The data processing method according to claim 7, characterized in that: The data processing method further includes: The fusion calculation results are sent to the data receiver.

9. The data processing method according to claim 7, characterized in that: The weight data is split according to high bits and low bits respectively to obtain high bit group data and low bit group data, including: The weight data is evenly divided according to the high bit and the low bit, respectively, to obtain high bit group data and low bit group data with equal number of bits.

10. The data processing method according to claim 7, characterized in that: The weight data and the digital input signal are multiplied and added.

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