Electrostatic discharge protection circuit structure

Abstract

The present invention discloses an electrostatic discharge protection circuit structure, which includes: a substrate; a first well region, having a first conductivity type, arranged in the substrate; a second well region, having a second conductivity type, arranged in the first well region; a first ring region, having a first conductivity type, arranged in the first well region, and coupled to a ground terminal; a plurality of first conductivity type doped regions, arranged in the second well region, and at least including a first, second and third region in sequence, wherein the first region and the third region are coupled to a high level terminal; and a plurality of second conductivity type doped regions, arranged in the first well region, and at least including a first, second and third region in sequence, wherein the first region and the third region are coupled to a ground terminal. At least the second regions of the plurality of first conductivity type doped regions and the second regions of the plurality of second conductivity type doped regions are electrically connected to each other.

Description

Technical Field

[0001] The invention relates to an electrostatic discharge protection circuit, and more particularly to an electrostatic discharge protection circuit with a high holding voltage. Background Art

[0002] In semiconductor integrated circuits (ICs), in order to prevent static electricity from damaging the internal circuits, an electrostatic discharge protection circuit is often set between the internal circuits and the input pads. Among them, the SCR circuit has excellent high current behavior and can provide good area gain, so it is often used as an electrostatic discharge protection circuit.

[0003] As is known to all, the SCR circuit is very robust, but due to its circuit characteristics, it has a deep snapback effect, which makes the SCR only have a low holding voltage. This problem will cause the latch-up (LU) effect. Therefore, if the SCR circuit is triggered by noise during the operation of the IC circuit, the SCR circuit will burn out, thereby affecting the protection function of electrostatic discharge.

[0004] In order to solve this problem, the known technology provides two solutions, one of which is as follows: Figure 1A The method shown is to increase the trigger current; that is, to prevent the SCR circuit from being easily triggered and causing malfunction. Figure 1B The method shown is to increase the holding voltage.

[0005] However, there is still a need in this field to provide an electrostatic discharge protection circuit that can increase the holding voltage and reduce the trigger voltage without causing malfunction. Summary of the invention

[0006] According to an embodiment of the present invention, an electrostatic discharge protection circuit is provided, which includes: a substrate; a first well region, having a first conductivity type, arranged in the substrate; a second well region, having a second conductivity type, arranged in the first well region; a first ring region, having the first conductivity type, arranged in the first well region, and coupled to a ground terminal; a plurality of first conductivity type doped regions, arranged in the second well region, and at least including a first, second and third region in sequence, wherein the first region and the third region are coupled to a high level terminal; and a plurality of second conductivity type doped regions, arranged in the first well region, and at least including a first, second and third region in sequence, wherein the first region and the third region are coupled to the ground terminal. At least the second region of the plurality of first conductivity type doped regions and the second region of the plurality of second conductivity type doped regions are electrically connected to each other. The first region, the second region and the second well region in the plurality of first conductivity type doped regions constitute a first parasitic transistor, and the second region, the third region and the first well region in the plurality of second conductivity type doped regions constitute a second parasitic transistor, thereby constituting a first electrostatic discharge path. The second well region, the substrate and the first well region constitute a third parasitic transistor, thereby constituting a second electrostatic discharge path. The second region, the third region and the second well region of the plurality of first conductive type doped regions constitute a fourth parasitic transistor, and the first region, the second region and the first well region of the plurality of second conductive type doped regions constitute a fifth parasitic transistor, thereby constituting a third electrostatic discharge path.

[0007] According to one embodiment of the present invention, the electrostatic discharge protection circuit may also include: a second ring area, having the second conductivity type, arranged in the second well area, surrounding the multiple first conductivity type doped areas, and coupled to the high level end; and a third ring area, having the first conductivity type, arranged in the first well area, surrounding the multiple second conductivity type doped areas, and connected to the ground end.

[0008] According to an embodiment of the present invention, in the electrostatic discharge protection circuit, the first conductivity type is P type, the second conductivity type is N type, and the substrate is P type.

[0009] According to an embodiment of the present invention, in the electrostatic discharge protection circuit, each of the plurality of first conductivity type doping regions is adjacently arranged at a certain interval in a first direction of the substrate and extends in a second direction perpendicular to the first direction.

[0010] According to an embodiment of the present invention, in the above-mentioned ESD protection circuit, the trigger voltage of the first ESD path is greater than the trigger voltage of the second ESD path, and the trigger voltage of the second ESD path is greater than the trigger voltage of the third ESD path.

[0011] According to an embodiment of the present invention, in the electrostatic discharge protection circuit, the first electrostatic discharge path, the second electrostatic discharge path, and the third electrostatic discharge path have corresponding holding voltages that are substantially equal.

[0012] According to an embodiment of the present invention, in the electrostatic discharge protection circuit, the fourth and fifth parasitic transistors of the third electrostatic discharge path constitute a silicon-controlled rectifier.

[0013] According to another embodiment of the present invention, an electrostatic discharge protection circuit structure is provided, which includes: a substrate; a first well region, having a first conductivity type, arranged in the substrate; a second well region, having a second conductivity type, arranged in the first well region; a first ring region, having the first conductivity type, arranged in the first well region, and coupled to a ground terminal; a plurality of first conductivity type doped regions, arranged in the second well region, and at least including first, second and third regions in sequence, wherein the first region and the third region are coupled to a high level terminal, and a gate is arranged on the substrate and between the first, second and third regions; and a plurality of second conductivity type doped regions, arranged in the first well region, and at least including first, second and third regions in sequence, wherein the first region and the third region are coupled to the ground terminal, and a gate is arranged on the substrate and between the first, second and third regions. At least the second regions of the plurality of first conductivity type doped regions and the second regions of the plurality of second conductivity type doped regions are electrically connected to each other. The first region, the second region and the second well region of the plurality of first conductive type doped regions constitute a first parasitic transistor, and the second region, the third region and the first well region of the plurality of second conductive type doped regions constitute a second parasitic transistor, thereby constituting a first electrostatic discharge path. The second well region, the substrate and the first well region constitute a third parasitic transistor, thereby constituting a second electrostatic discharge path. The second region, the third region and the second well region of the plurality of first conductive type doped regions constitute a fourth parasitic transistor, and the first region, the second region and the first well region of the plurality of second conductive type doped regions constitute a fifth parasitic transistor, thereby constituting a third electrostatic discharge path.

[0014] According to one embodiment of the present invention, the above-mentioned electrostatic discharge protection circuit may also include: a second ring area, having the second conductivity type, arranged in the second well area, surrounding the multiple first conductivity type doped areas, and connected to the high level end; and a third ring area, having the first conductivity type, arranged in the first well area, surrounding the multiple second conductivity type doped areas, and connected to the ground end.

[0015] According to an embodiment of the present invention, in the electrostatic discharge protection circuit, the first conductivity type is P type, the second conductivity type is N type, and the substrate is P type.

[0016] According to one embodiment of the present invention, in the above-mentioned electrostatic discharge protection circuit, the gates set between the first, the second and the third regions of the multiple first conductive type doping regions serve as PMOS trigger nodes, and the gates set between the first, the second and the third regions of the multiple second conductive type doping regions serve as NMOS trigger nodes.

[0017] According to an embodiment of the present invention, in the electrostatic discharge protection circuit, each of the plurality of first conductivity type doping regions is arranged at a certain interval in a first direction of the substrate and extends in a second direction perpendicular to the first direction.

[0018] According to an embodiment of the present invention, in the above-mentioned ESD protection circuit, the trigger voltage of the first ESD path is greater than the trigger voltage of the second ESD path, and the trigger voltage of the second ESD path is greater than the trigger voltage of the third ESD path.

[0019] According to an embodiment of the present invention, in the electrostatic discharge protection circuit, the first electrostatic discharge path, the second electrostatic discharge path, and the third electrostatic discharge path have corresponding holding voltages that are substantially equal.

[0020] According to an embodiment of the present invention, in the electrostatic discharge protection circuit, the fourth and fifth parasitic transistors of the third electrostatic discharge path constitute a silicon-controlled rectifier.

[0021] Based on the above, the electrostatic discharge protection circuit structure according to the embodiment of the present invention provides three electrostatic discharge paths with different trigger voltages, so that electrostatic discharge can be further effectively performed. In addition, the parasitic silicon-controlled rectifier part in the electrostatic discharge protection circuit structure is triggered by the secondary current, so the transistor spacing in the parasitic silicon-controlled rectifier can be increased, thereby further increasing the holding voltage. In addition, by improving the electrostatic discharge performance, the area of ​​the electrostatic discharge protection circuit structure can also be further reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1A and Figure 1B There are two known ways to solve the SCR circuit latch problem.

[0023] Figure 2 It is a top view of an electrostatic discharge protection circuit according to an embodiment of the present invention.

[0024] Figure 3Afrom Figure 2 A schematic cross-sectional doping diagram of an electrostatic discharge protection circuit cut along a section line AA'.

[0025] Figure 3B Draw Figure 3A A schematic diagram of a cross-sectional view of a doping example and a parasitic transistor.

[0026] Figure 4A According to the embodiment of the present invention, Figure 3B Schematic diagram of the equivalent circuit and discharge path.

[0027] Figure 4B FIG. 4 is a schematic diagram of a discharge path according to an embodiment of the present invention.

[0028] Figure 5 FIG. 4 is a transmission line pulse (TLP) current-voltage curve diagram of an electrostatic discharge protection circuit according to an embodiment of the present invention.

[0029] Fig. 6A A cross-sectional doping diagram of an electrostatic discharge protection circuit according to another embodiment of the present invention is shown.

[0030] Figure 6B Draw Fig. 6A A schematic diagram of a cross-sectional view of a doping example and a parasitic transistor.

[0031] Figure 6C Painted Figure 6B Schematic diagram of the equivalent circuit and discharge path.

[0032]

Explanation of symbols

[0033] 100, 200: substrate

[0034] 102, 202: first well region

[0035] 104, 204: Second well region

[0036] 110, 210: First Ring Area

[0037] 112, 212: Second Ring Area

[0038] 114, 214: a plurality of first conductivity type doping regions

[0039] 114a, 114b, 114c: First zone, second zone, third zone

[0040] 214a, 214b, 214c: Zone 1, Zone 2, Zone 3

[0041] 122, 224: multiple second conductivity type doping regions

[0042] 122a, 122b, 122c: First zone, second zone, third zone

[0043] 224a, 224b, 224c: Zone 1, Zone 2, Zone 3

[0044] 120, 210: Third Ring Area

[0045] 216a, 216b, 226a, 226b: Gate

[0046] P11, P12, P31, P32: Parasitic transistors

[0047] N11, N12, N31, N32: parasitic transistors

[0048] P2, P4: parasitic transistors

[0049] ESD1~ESD3: The first to third electrostatic discharge current

[0050] GND: Ground terminal DETAILED DESCRIPTION

[0051] Figure 2 It is a top view of an electrostatic discharge protection circuit according to an embodiment of the present invention. Figure 3A from Figure 2 The cross-sectional doping diagram of the electrostatic discharge protection circuit cut by the section line A-A' is shown below. Figure 2 and Figure 3A The semiconductor structure of the electrostatic discharge protection circuit of the present invention is described below.

[0052] like Figure 2 and 3A As shown, the electrostatic discharge protection circuit includes a substrate 100, a first well region 102, a second well region 104, a first ring region 110, a plurality of first conductive type doping regions 114, and a plurality of second conductive type doping regions 122. The substrate 100 may have a first conductive type, such as P-type doping. The first well region 102 has the same first conductive type as the substrate 100 and is disposed in the substrate 100. The second well region 104 has a second conductive type and is disposed in the first well region 102. Here, the second conductive type is, for example, N-type doping.

[0053] In addition, the first ring region 110 has a first conductivity type, is disposed in the first well region 102, and is coupled to the ground terminal GND. Here, the ground terminal GND may be the lowest level of the entire circuit system. Figure 2 The first ring area 110 shown is a slightly square or rectangular structure, but is not limited to this shape and can be designed according to actual needs.

[0054] In addition, the plurality of first conductive type doping regions 114 may include a plurality of regions separated by a certain interval and arranged in the first well region 102. In this embodiment, the first region 114a, the second region 114b and 114c in sequence are used as an illustrative example. Similarly, the plurality of second conductive type doping regions 122 may also include a plurality of regions separated by a certain interval and arranged in the first well region 102. In this embodiment, the first region 122a, the second region 122b and 122 in sequence are used as an illustrative example. With respect to the plurality of first conductive type doping regions 114 and the plurality of second conductive type doping regions 122, those skilled in the art may appropriately change or modify their number and electrical connection method based on the description of this embodiment, without departing from the protection scope of the present invention.

[0055] In addition, if Figure 2 As shown, each of the plurality of first conductive type doping regions 114 (e.g., 114a, 114b, 114c) is sequentially arranged in the first direction X of the substrate 100 at a certain interval, and extends in the second direction Y perpendicular to the first direction X. Similarly, each of the plurality of second conductive type doping regions 122 (e.g., 122a, 122b, 122c) is sequentially arranged in the first direction X of the substrate 100 at a certain interval, and extends in the second direction Y perpendicular to the first direction X.

[0056] In addition, if Figure 3A As shown, at least the second region 114b of the plurality of first conductivity type doping regions 114 and the second region 122b of the plurality of second conductivity type doping regions 122 are electrically connected to each other. In addition, the first region 114a and the third region 114c of the plurality of first conductivity type doping regions 114 are coupled to a high level end. Here, the so-called high level end can be an input pad, a power rail to be protected or a circuit power supply (power rail), etc. In short, it is an end with a relatively high level in the circuit. The first region 122a and the third region 122c of the plurality of second conductivity type doping regions 122 are coupled to the ground end GND.

[0057] In addition, according to an embodiment of the present invention, the electrostatic discharge protection circuit structure may further include a second ring area 112 and a third ring area 120. The second ring area 112 is of the second conductivity type, is disposed in the second well area 104, surrounds a plurality of first conductivity type doped areas 114, and is coupled to the high level terminal. The third ring area 120 is of the first conductivity type, is disposed in the first well area 102, surrounds a plurality of second conductivity type doped areas 122, and is coupled to the ground terminal GND. In addition, although Figure 2 The second ring area 112 and the third ring area 120 are shown as being in a square or rectangular structure, but are not limited to such shapes and can be designed according to actual needs.

[0058] Next, the circuit structure and operation mode of the electrostatic discharge protection circuit according to the embodiment of the present invention are described. Figure 3B Draw Figure 3A In the following examples, the first conductivity type and the second conductivity type will be described as P-type doping and N-type doping, respectively.

[0059] like Figure 3B As shown, although the figure shows an N-doped ring of the second ring area 112 and a P-doped ring of the third ring area 120, as mentioned above, the second ring area 112 and the third ring area 120 can still be selectively set. In addition, in this example, although the figure shows a P+ doped area and an N+ doped area, in practice, it is not necessary to use P+ or N+ doping, but only this type of doping is sufficient, for example, a lighter doping such as P- or N- can be used.

[0060] like Figure 3B As shown, the first region (in this example, P+ doping) 114a, the second region (in this example, P+ doping) 114b and the second well region (in this example, N well) 104 in the plurality of first conductive type doped regions 114 constitute a first parasitic transistor P11 (i.e., a parasitic PNP transistor), and the second region (in this example, N+ doping) 122b, the third region (in this example, N+ doping) 112c and the first well region (in this example, P well) 102 in the plurality of second conductive type doped regions 122 constitute a second parasitic transistor N11 (i.e., a parasitic NPN transistor), thereby constituting a first electrostatic discharge path ESD 1. The second well region 102, the substrate 100 and the first well region 102 constitute a third parasitic transistor P2 (i.e., a parasitic PNP transistor), thereby constituting a second electrostatic discharge path ESD 2. The second region, the third region of the plurality of first conductive type doped regions 114 and the second well region 104 constitute a fourth parasitic transistor P12 (i.e., a parasitic PNP transistor), and the first region 122a, the second region 122b of the plurality of second conductive type doped regions 122 and the first well region 102 constitute a fifth parasitic transistor N12, thereby constituting a third electrostatic discharge path ESD 3. The fourth parasitic transistor P12 and the fifth parasitic transistor N12 constitute a silicon controlled rectifier SCR.

[0061] Figure 4A According to the embodiment of the present invention, Figure 3B Schematic diagram of the equivalent circuit and discharge path. Figure 4B FIG. 4 is a schematic diagram of a discharge path according to an embodiment of the present invention. Figure 3B The circuit diagram of the electrostatic discharge protection circuit structure described is as follows Figure 4AAs shown. According to an embodiment of the present invention, three first to third electrostatic discharge paths ESD 1 to ESD 3 with different trigger voltages are provided between the high level end and the ground end GND. The first electrostatic discharge path ESD 1 is composed of a first parasitic transistor P11 and a second parasitic transistor N11 coupled between the high level end and the ground end GND, and is the earliest triggered discharge path. The second electrostatic discharge path ESD 2 is composed of a third parasitic transistor P2 coupled between the high level end and the ground end GND (PNP type), and is a subsequently triggered discharge path. The third electrostatic discharge path ESD 3 (SCR type) is composed of a fourth parasitic transistor P12 and a fifth parasitic transistor N12 coupled between the high level end and the ground end GND, and is the last triggered discharge path.

[0062] like Figure 4A and 4B As shown, when an electrostatic discharge event occurs at a high level terminal (such as an input pad), the first electrostatic discharge path ESD1 will be triggered to conduct first, and the conduction voltage at this time is the breakdown voltage of the first parasitic transistor P11 and the second parasitic transistor N12. In this way, the ESD current can be guided to the ground terminal GND through the first electrostatic discharge path ESD1. Figure 3A As shown, the ESD current enters from the first region 114a of the plurality of first conductivity type doped regions 114, passes through the second region 114b, enters the second region 122b of the plurality of second conductivity type doped regions 122 through electrical connection, and then discharges to the ground terminal GND through the third region 122c.

[0063] Next, after the first electrostatic discharge path ESD 1 is turned on, the secondary current will successively turn on the second electrostatic discharge path ESD 2 and the second electrostatic discharge path ESD 3. After the second electrostatic discharge path ESD 2 is triggered to turn on, the discharge current will enter the second well region 104 (or enter the second well region 104 from the N+ doping 112 of the second ring region), through the first well region 102, and discharge from the first ring region (P+ doping) 110 to the ground terminal GND. Next, after the third electrostatic discharge path ESD 3 is turned on, the discharge current will enter from the second region 114b of the plurality of first conductive type doped regions 114, through the third region 114c, and then enter the second region 122b of the plurality of second conductive type doped regions 122 through electrical connection, and then discharge to the ground terminal GND through the first region 122a.

[0064] As described above, according to the ESD protection circuit of the embodiment of the present invention, since the third ESD path ESD3 is triggered by the secondary current, the interval d (see Figure 3A , 3B) can be further increased, thereby obtaining a higher holding voltage characteristic.

[0065] Figure 5 FIG. 2 is a transmission line pulse (TLP) current-voltage curve diagram of an electrostatic discharge protection circuit according to an embodiment of the present invention. Figure 5 As shown, the electrostatic discharge protection circuit of this embodiment may have three triggering stages, which correspond to the first to third electrostatic discharge paths ESD1-ESD3 mentioned above respectively. Figure 5 It can be seen that the trigger voltage Vt of the first electrostatic discharge path ESD 1 is about 23.3V and the holding voltage Vh is about 18.3V, the trigger voltage Vt of the second electrostatic discharge path ESD 2 is about 18.88V and the holding voltage Vh is about 18V, and the trigger voltage Vt of the third electrostatic discharge path ESD 3 is about 19.66V and the holding voltage Vh is about 18.37V. It can be seen that the trigger voltage of the first electrostatic discharge path is greater than the trigger voltage of the second electrostatic discharge path, and the trigger voltage of the second electrostatic discharge path is less than the trigger voltage of the third electrostatic discharge path. In addition, the corresponding holding voltages of the first to third electrostatic discharge paths are approximately equal. From this result, it can be seen that the electrostatic discharge protection circuit of the embodiment of the present invention can be applied to operations with higher holding voltages.

[0066] In summary, in an experimental example of the electrostatic discharge protection circuit of the embodiment of the present invention, the breakdown voltage is about 23V, and can reach 1.953V / μm under the human body model (HBM) test. 2 Compared with the existing ESD protection circuit performance, the human body model (HBM) test is generally only 0.549V / μm 2 In terms of performance, the performance of the electrostatic discharge protection circuit of this embodiment can be improved by at least three times.

[0067] In addition, according to the experimental results of the electrostatic discharge protection circuit of the embodiment of the present invention, the area is only 4095 μm 2 Compared with the current general area size of at least 9000μm 2 , the area of ​​the electrostatic discharge protection circuit disclosed in this embodiment can be reduced by nearly half.

[0068] Next, another embodiment of the present invention will be described. Fig. 6A A cross-sectional doping diagram of an electrostatic discharge protection circuit according to another embodiment of the present invention is shown. Figure 6B Draw Fig. 6A A schematic diagram of a cross-sectional view of a doping example and a parasitic transistor. Figure 6C Painted Figure 6B Schematic diagram of the equivalent circuit and discharge path.

[0069] also, Figure 6A to Figure 6C The embodiment shown in the figure differs from the embodiment described above in that the structure of the gate is formed between two doping regions in the well region, and the structures of the rest of the parts are basically the same or similar. Figure 6A to Figure 6C To explain.

[0070] like Fig. 6A As shown, the electrostatic discharge protection circuit includes a substrate 200, a first well region 202, a second well region 204, a first ring region 210, a plurality of first conductive type doping regions 214, and a plurality of second conductive type doping regions 224. The substrate 200 may have a first conductive type, such as P-type doping. The first well region 202 has the same first conductive type as the substrate 200 and is disposed in the substrate 200. The second well region 204 has a second conductive type and is disposed in the first well region 202. Here, the second conductive type is, for example, N-type doping.

[0071] In addition, the first ring area 210 has a first conductivity type, is disposed in the first well area 202, and is coupled to the ground terminal GND. Here, the ground terminal GND may be the lowest level of the entire circuit system. As in the previous embodiment, the first ring area 210 here may be a slightly square or rectangular structure, but is not actually limited to this shape, and may be designed according to actual needs.

[0072] In addition, the plurality of first conductive type doping regions 214 may include a plurality of regions separated by a certain interval and arranged in the first well region 202. In this embodiment, the first region 214a, the second region 214b and 214c in sequence are used as an illustrative example. Similarly, the plurality of second conductive type doping regions 224 may also include a plurality of regions separated by a certain interval and arranged in the first well region 202. In this embodiment, the first region 224a, the second region 224b and 224c in sequence are used as an illustrative example. With respect to the plurality of first conductive type doping regions 214 and the plurality of second conductive type doping regions 224, those skilled in the art may appropriately change or modify their number and electrical connection method based on the description of this embodiment, without departing from the protection scope of the present invention.

[0073] In addition, if Fig. 6A As shown, gates 216a and 216b are disposed between the first region 214a, the second region 214b and the third region 214c of the plurality of first conductive type doped regions 214. Gates 226a and 226b are disposed between the first region 224a, the second region 224b and the third region 224c of the plurality of second conductive type doped regions 224.

[0074] In addition, if Fig. 6AAs shown, at least the second region 214b of the plurality of first conductive type doping regions 214 and the second region 224b of the plurality of second conductive type doping regions 224 are electrically connected to each other. In addition, the first region 214a and the third region 214c of the plurality of first conductive type doping regions 214 are coupled to the high level end. The first region 224a and the third region 224c of the plurality of second conductive type doping regions 224 are coupled to the ground end GND.

[0075] In addition, according to an embodiment of the present invention, the electrostatic discharge protection circuit structure may further include a second ring area 212 and a third ring area 222. The second ring area 212 of the second conductivity type is arranged in the second well area 204, surrounds a plurality of first conductivity type doped areas 214, and is coupled to the high level terminal. The third ring area 222 has the first conductivity type, is arranged in the first well area 202, surrounds a plurality of second conductivity type doped areas 224, and is coupled to the ground terminal GND. Similarly, the second ring area 112 and the third ring area 120 may be a slightly square or rectangular structure, but are not actually limited to this shape, and may be designed according to actual needs. In addition, as mentioned above, the second ring area 212 and the third ring area 222 may still be selectively arranged.

[0076] As an example, Figure 6B The first conductivity type and the second conductivity type are illustrated as P-type doping and N-type doping, respectively. In this example, the gates 216a and 216b can serve as trigger nodes of a PMOS transistor, and the gates 226a and 226b can serve as trigger nodes of an NMOS transistor. Figure 6BAs shown, the first region (P+ doped in this example) 214a, the second region (P+ doped in this example) 214b, the second well region (N well in this example) 204 and the gate 216a of the plurality of first conductive type doped regions 214 constitute a first parasitic transistor P31 (i.e., a parasitic PMOS transistor), and the second region (N+ doped in this example) 224b, the third region (N+ doped in this example) 224c, the gate 226b and the first well region (P well in this example) 202 of the plurality of second conductive type doped regions 224 constitute a second parasitic transistor N31 (i.e., a parasitic NMOS transistor), thereby constituting a first electrostatic discharge path ESD 1. The second well region 202, the substrate 200 and the first well region 202 constitute a third parasitic transistor P4 (i.e., a parasitic PNP transistor), thereby constituting a second electrostatic discharge path ESD 2. The second region 214b, the third region 214c, the gate 216b and the second well region 204 in the plurality of first conductive type doped regions 214 constitute a fourth parasitic transistor P32 (i.e., a parasitic PNP transistor), and the first region 224a, the second region 224b, the gate 226a and the first well region 202 in the plurality of second conductive type doped regions 224 constitute a fifth parasitic transistor N32, thereby constituting a third electrostatic discharge path ESD 3. The fourth parasitic transistor P32 and the fifth parasitic transistor N32 constitute a silicon controlled rectifier SCR.

[0077] also, Figure 6B The calibration circuit diagram of the electrostatic discharge protection circuit structure shown is Figure 6C As shown, except for adding gates 216a, 216b, 226a, 226c so that the parasitic transistor constituting the first electrostatic discharge path ESD1 is composed of a parasitic NMOS transistor N31 and a parasitic PMOS transistor P31, the remaining parasitic transistor components are the same. In addition, in this embodiment, the triggering method and operation method of the first to third electrostatic discharge paths ESD1-ESD3 are the same as those of the previous implementation, so they will not be described in detail here.

[0078] In summary, according to the electrostatic discharge protection circuit structure of the embodiment of the present invention, it provides three electrostatic discharge paths with different trigger voltages, so it can further achieve effective electrostatic discharge. In addition, the parasitic silicon-controlled rectifier part in the electrostatic discharge protection circuit structure is triggered by the secondary current, so the transistor spacing in the parasitic silicon-controlled rectifier can be increased, and the holding voltage can be further increased. In addition, by improving the electrostatic discharge performance, the area of ​​the electrostatic discharge protection circuit structure can also be further reduced.

[0079] So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings.

[0080] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An electrostatic discharge protection circuit structure, wherein: include: substrate; A first well region, having a first conductivity type, is disposed in the substrate; A second well region, having a second conductivity type, is disposed in the first well region; A first ring region, having the first conductivity type, is disposed in the first well region and is coupled to the ground terminal; a plurality of first conductivity type doped regions, disposed in the second well region, and at least including a first region, a second region and a third region in sequence, wherein the first region and the third region are coupled to a high level end; and A plurality of second conductive type doped regions are disposed in the first well region and at least include a first region, a second region and a third region in sequence, wherein the first region and the third region are coupled to the ground terminal, wherein at least the second regions of the plurality of first conductivity type doping regions and the second regions of the plurality of second conductivity type doping regions are electrically connected to each other, The first region, the second region and the second well region of the plurality of first conductive type doped regions constitute a first parasitic transistor, and the second region, the third region and the first well region of the plurality of second conductive type doped regions constitute a second parasitic transistor, thereby constituting a first electrostatic discharge path. The second well region, the substrate and the first well region constitute a third parasitic transistor, thereby constituting a second electrostatic discharge path, and The second region, the third region and the second well region of the multiple first conductive type doped regions constitute a fourth parasitic transistor, and the first region, the second region and the first well region of the multiple second conductive type doped regions constitute a fifth parasitic transistor, thereby forming a third electrostatic discharge path.

2. The electrostatic discharge protection circuit structure according to claim 1, wherein: Also includes: a second ring region, having the second conductivity type, disposed in the second well region, surrounding the plurality of first conductivity type doped regions, and connected to the high level end; and The third ring region has the first conductivity type, is disposed in the first well region, surrounds the plurality of second conductivity type doped regions, and is connected to the ground terminal.

3. The electrostatic discharge protection circuit structure according to claim 2, wherein: The first conductivity type is P type, the second conductivity type is N type, and the substrate is P type.

4. The electrostatic discharge protection circuit structure according to claim 1, wherein: Each of the plurality of first conductivity type doping regions is arranged at a certain interval in a first direction of the substrate and extends in a second direction perpendicular to the first direction.

5. The electrostatic discharge protection circuit structure according to claim 1, wherein: The trigger voltage of the first electrostatic discharge path is greater than the trigger voltage of the second electrostatic discharge path, and the trigger voltage of the second electrostatic discharge path is less than the trigger voltage of the third electrostatic discharge path.

6. The electrostatic discharge protection circuit structure according to claim 5, wherein: The first electrostatic discharge path, the second electrostatic discharge path and the third electrostatic discharge path respectively have corresponding maintaining voltages that are equal.

7. The electrostatic discharge protection circuit structure according to claim 1, wherein: The fourth parasitic transistor and the fifth parasitic transistor of the third electrostatic discharge path form a silicon-controlled rectifier.

8. An electrostatic discharge protection circuit structure, wherein: include: substrate; A first well region, having a first conductivity type, is disposed in the substrate; A second well region, having a second conductivity type, is disposed in the first well region; A first ring region, having the first conductivity type, is disposed in the first well region and is coupled to the ground terminal; A plurality of first conductivity type doped regions are arranged in the second well region and at least include a first region, a second region and a third region in sequence, wherein the first region and the third region are coupled to a high level end, and a gate is arranged on the substrate and between the first region, the second region and the third region; as well as A plurality of second conductive type doped regions are arranged in the first well region and at least include a first region, a second region and a third region in sequence, wherein the first region and the third region are coupled to the ground terminal, and a gate is arranged on the substrate and between the first region, the second region and the third region. wherein at least the second regions of the plurality of first conductivity type doping regions and the second regions of the plurality of second conductivity type doping regions are electrically connected to each other, The first region, the second region and the second well region of the plurality of first conductive type doped regions constitute a first parasitic transistor, and the second region, the third region and the first well region of the plurality of second conductive type doped regions constitute a second parasitic transistor, thereby constituting a first electrostatic discharge path. The second well region, the substrate and the first well region constitute a third parasitic transistor, thereby constituting a second electrostatic discharge path, and The second region, the third region and the second well region of the multiple first conductive type doped regions constitute a fourth parasitic transistor, and the first region, the second region and the first well region of the multiple second conductive type doped regions constitute a fifth parasitic transistor, thereby forming a third electrostatic discharge path.

9. The electrostatic discharge protection circuit structure according to claim 8, wherein: Also includes: a second ring region, having the second conductivity type, disposed in the second well region, surrounding the plurality of first conductivity type doped regions, and connected to the high level end; and The third ring region has the first conductivity type, is disposed in the first well region, surrounds the plurality of second conductivity type doped regions, and is connected to the ground terminal.

10. The electrostatic discharge protection circuit structure according to claim 9, wherein: The first conductivity type is P type, the second conductivity type is N type, and the substrate is P type.

11. The electrostatic discharge protection circuit structure according to claim 10, wherein: The gates set between the first region, the second region and the third region of the multiple first conductive type doping regions serve as PMOS trigger nodes, and the gates set between the first region, the second region and the third region of the multiple second conductive type doping regions serve as NMOS trigger nodes.

12. The electrostatic discharge protection circuit structure according to claim 8, wherein: Each of the plurality of first conductivity type doping regions is arranged at a certain interval in a first direction of the substrate and extends in a second direction perpendicular to the first direction.

13. The electrostatic discharge protection circuit structure according to claim 8, wherein: The trigger voltage of the first electrostatic discharge path is greater than the trigger voltage of the second electrostatic discharge path, and the trigger voltage of the second electrostatic discharge path is less than the trigger voltage of the third electrostatic discharge path.

14. The electrostatic discharge protection circuit structure according to claim 13, wherein: The first electrostatic discharge path, the second electrostatic discharge path and the third electrostatic discharge path respectively have corresponding maintaining voltages that are equal.

15. The electrostatic discharge protection circuit structure according to claim 8, wherein: The fourth parasitic transistor and the fifth parasitic transistor of the third electrostatic discharge path form a silicon-controlled rectifier.

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