Low EMI clock generation circuit for high-voltage integrated circuits

Abstract

The present invention relates to a low-EMI clock generation circuit for high-voltage integrated circuits, comprising a pseudo-random modulation power supply generation circuit and a clock generation and coupling output circuit. In the low-EMI clock generation circuit solution provided by the present invention, on the one hand, the oscillator power supply voltage VCC_OSC used by the clock generation circuit is only controlled by a reference signal and is not affected by PVT fluctuations, thereby ensuring the frequency stability of the reference clock signal OSC_out; on the other hand, a pseudo-random code with pseudo-random characteristics in both amplitude and time is used inside the pseudo-random modulation power supply generation circuit to modulate the oscillator power supply voltage, thereby making the frequency of the reference clock signal OSC_out have a random frequency jitter characteristic, thereby achieving the goal of reducing EMI interference. The implementation scheme of the present invention can be widely used in various types of high-voltage integrated circuit systems.

Description

Technical Field

[0001] The invention relates to a low EMI clock generating circuit for a high-voltage integrated circuit, belonging to the technical field of integrated circuits. Background Art

[0002] High-voltage integrated circuits (HVICs) serve as a bridge between the signal processing and execution components of a system, integrating high-voltage power devices with control circuits, peripheral interface circuits, and protection circuits. These high-voltage integrated circuits, acting as a bridge between strong and weak currents, must also achieve low power consumption and high efficiency. At the same time, harsh application environments demand excellent performance and reliability, requiring high-voltage and low-voltage compatibility, high performance, high efficiency, and high reliability within a limited chip area. From an application functional perspective, typical HVIC products include power management chips and various driver chips. As energy consumption and environmental requirements for electronic devices continue to increase, the market is fiercely competing for low power consumption, high precision, small size, and environmental friendliness, resulting in increasingly stringent performance requirements for HVICs.

[0003] Among the many technical specifications of high-voltage integrated circuits, electromagnetic interference (EMI) is a key concern. For controller chips using the commonly used PWM control method, EMI emissions typically peak at the chip's fundamental switching frequency. The radiation intensity of each higher harmonic gradually decreases, with the majority of the radiated energy confined to the fundamental and lower harmonics. To reduce EMI, the first consideration is to suppress the energy of the noise source. One method involves varying the switching frequency, or modulating it, to spread the spectrum at the switching frequency, thereby reducing radiated energy. Combining random modulation techniques with the oscillator clock signal within the high-voltage integrated circuit can achieve this EMI reduction goal.

[0004] Numerous solutions exist for oscillator generation circuits with random modulation characteristics. Patent CN201110259041 proposes a frequency-jittering oscillator controlled by a pseudo-random sequence, and patent CN201010602270 proposes a method for generating a spread-spectrum clock jitter signal. According to random signal theory, when frequency jittering is used, the periodic patterns inherent in the modulation scheme are inevitably reflected in certain electrical quantities in the system, influencing the spectrum of these quantities and resulting in a corresponding discrete spectrum. Therefore, the more dispersed the spectral components of the random modulation signal, the lower the secondary EMI impact, leading to better overall EMI suppression in the controller chip. Summary of the Invention

[0005] Building on existing technologies, this invention provides a low-EMI clock generation circuit for high-voltage integrated circuits, reducing the system's EMI emissions. To reduce EMI, the clock generation circuit uses a pseudo-random modulation technique with random characteristics in both time and amplitude.

[0006] According to the present invention, a low-EMI clock generation circuit for a high-voltage integrated circuit includes a frequency-jittering relative amplitude control circuit, a frequency-jittering reference voltage generation circuit, an error amplification and buffering circuit, and a clock generation and coupling output circuit. The input end of the frequency-jittering relative amplitude control circuit is connected to an externally input frequency-jittering amplitude control signal Set and a frequency-jittering control clock ck_dith fed back by the frequency-jittering reference voltage generation circuit, and outputs a frequency-jittering relative amplitude selection signal Sel to the frequency-jittering reference voltage generation circuit; the frequency-jittering reference voltage generation circuit obtains a frequency-jittering reference voltage Vrdith based on the frequency-jittering relative amplitude selection signal Sel generated by the frequency-jittering relative amplitude control circuit, and outputs the frequency-jittering reference voltage to the error amplification and buffering circuit; the input end of the error amplification and buffer circuit is connected to the frequency-jittering reference voltage Vrdith and a feedback clock CK_fb output by the clock generation and coupling output circuit, to generate an oscillator power supply voltage VCC_OSC, which is output to the clock generation and coupling output circuit; the clock generation and coupling output circuit generates X-channel output clocks CK1 to CKX and a feedback clock CK_fb based on the oscillator power supply voltage VCC_OSC.

[0007] Specifically, the error amplification and buffer circuit includes: a PMOS transistor M200, a PMOS transistor M201, a PMOS transistor M202, a PMOS transistor M203, a PMOS transistor M205, a PMOS transistor M206, a PMOS transistor M211, a PMOS transistor M221, an NMOS transistor M208, an NMOS transistor M209, an NMOS transistor M210, an NMOS transistor M222, a resistor R21 and a capacitor C21, a resistor R221, a resistor R222 and a capacitor C221; wherein the drain of the PMOS transistor M200 is connected to the upper end of the resistor R221, the lower end of the resistor R221 is connected to the upper end of the resistor R222, The source of the PMOS transistor M221 is connected to the gate of the PMOS transistor M205 as the output point of the clock feedback voltage Vckfb; the gate of the PMOS transistor M221 and the gate of the NMOS transistor M222 are connected to the feedback clock CK_fb; the drain of the PMOS transistor M221 and the drain of the NMOS transistor M222 are connected and connected to the upper end of the capacitor C221; the drain of the PMOS transistor M201 is connected to the source of the PMOS transistor M205 and the source of the PMOS transistor M206; the drain of the PMOS transistor M205 is connected to the gate of the NMOS transistor M208, the drain of the NMOS transistor M208, and the gate of the NMOS transistor M209; The gate of the S transistor M206 is connected to the frequency-jittering reference voltage Vrdith, the drain of the PMOS transistor M206 is connected to the drain of the NMOS transistor M209, the gate of the NMOS transistor M210, and the upper end of the resistor R21; the lower end of the resistor R21 is connected to the upper end of the capacitor C21; the drain of the NMOS transistor M210 is connected to the drain of the PMOS transistor M202 and the gate of the PMOS transistor M211; the source of the PMOS transistor M211 is connected to the lower end of the resistor R23 and the upper end of the capacitor C22, and serves as the oscillator power supply voltage VCC_OSC port; the upper end of the resistor R23 is connected to the drain of the PMOS transistor M203; the PMOS transistor The gates of M200, M201, M202, and M203 are all connected to a bias voltage Vbc21; the sources of the NMOS transistors M208, M209, and M222, the lower end of the capacitor C221, the lower end of the capacitor C21, the lower end of the resistor R222, the drain of the PMOS transistor M211, and the lower end of the capacitor C22 are all connected to the ground voltage GND; the sources of the PMOS transistors M200, M201, M202, and M203 are all connected to a power supply voltage VCC.

[0008] Specifically, the frequency-jittering reference voltage generating circuit includes Y+N voltage-dividing resistor strings, Y+N NMOS transistors, a coding conversion circuit and a pseudo-random code generating circuit connected in series, where Y=2 J , J is any positive integer; N = 2 K, K is an arbitrary positive integer; the first Y resistors are connected in series to form a frequency jitter relative amplitude adjustment resistor string, and the last N resistors are connected in series to form a frequency jitter absolute amplitude adjustment resistor string; the upper ends of the first Y resistors are connected to the reference voltage Vref; the connection point of the first Y resistors and the last N resistors generates a frequency jitter reference voltage Vrdith; the lower ends of the last N resistors are connected to the ground voltage GND; the drain and source of the Y NMOS tubes M311~M31Y are respectively connected to the upper and lower ends of the first Y resistors, and the drain of the N NMOS tubes M331~M33N is connected to the ground voltage GND. The electrode and source correspond to the upper and lower ends of the N resistors respectively; the input end of the code conversion circuit is connected to the frequency-jittering relative amplitude selection signal Sel, and the output ends of the code conversion circuit are Y-bit selection codes S1~SY, which are respectively connected to the gates of Y NMOS transistors M311~M31Y; the output ends of the pseudo-random code generation circuit are N-bit pseudo-random codes P1~PN and the frequency-jittering control clock ck_dith, and the N-bit pseudo-random codes P1~PN are respectively connected to the gates of N NMOS transistors M331~M33N.

[0009] The frequency-jittering reference voltage Vrdith generated by the frequency-jittering reference voltage generating circuit is obtained by dividing the total resistance Rs31 of the frequency-jittering relative amplitude adjustment resistor string and the total resistance Rs33 of the frequency-jittering absolute amplitude adjustment resistor string; the frequency-jittering reference voltage Vrdith has a pseudo-random characteristic on the one hand, and its relative amplitude relative to the reference voltage is also controlled by the frequency-jittering relative amplitude selection signal Sel on the other hand; the resistance values of any two resistors in the frequency-jittering absolute amplitude adjustment resistor string are different, and the ratio between any two resistors among the N resistors is different, thereby realizing the random characteristic of the amplitude of the frequency-jittering reference voltage Vrdith; the N-bit pseudo-random codes P1~PN generated by the pseudo-random code generating circuit, at any time only one pseudo-random code outputs a high level, and the remaining N-1 bits are all low levels; and the time length of the output high level of any one pseudo-random code among the N-bit pseudo-random codes P1~PN is different, thereby realizing the random characteristic of the frequency-jittering reference voltage Vrdith in time.

[0010] Specifically, the pseudo-random code generating circuit includes: a ring oscillator, a delay sequence generating circuit, a pseudo-random encoding circuit, a binary to thermometer encoding circuit and a buffer; the ring oscillator generates an initial control clock signal CLK and outputs it to the delay sequence generating circuit and the buffer; the delay sequence generating circuit generates 2 K+1 -1 clock signals Q1~Q(2 K+1 -1) is output to the pseudo-random coding circuit; the pseudo-random coding circuit converts 2 K+1 -1 clock signals Q1~Q(2 K+1-1) random coding is converted into K-bit binary data signals D1~DK and output to the binary to thermometer coding circuit; the binary to thermometer coding circuit converts the K-bit binary data signals D1~DK into codes to obtain 2 K Bit thermometer code P1~P2 K ; 2 K Bit thermometer code P1~P2 K That is, the N-bit pseudo-random code finally output by the pseudo-random code generating circuit; where N=2 K , K is a positive integer; the buffer isolates and buffers the received initial control clock signal CLK to obtain the frequency jitter control clock ck_dith, which is used to control the working state of the frequency jitter relative amplitude control circuit;

[0011] The delay sequence generating circuit includes 2 K+1 -1 cascaded identical delay unit and an XOR gate XOR51; the delay unit includes a clock input, a data input, and a data output; except for the first delay unit, the clock input of all other delay units is connected to the initial control clock signal CLK, the data input is connected to the data output of the previous delay unit, and the data output is connected to the data input of the next delay unit; 2 K +1 -1 cascaded delay unit generates 2 K+1 -1 clock data signal Q1~Q(2 K+1 -1); the last two clock data signals Q(2 K+1 -1) and Q(2 K+1 -2) After passing through the XOR gate XOR51, the feedback is connected to the data input terminal of the first delay unit.

[0012] Specifically, the frequency-jittering relative amplitude control circuit includes: an input interface circuit, a serial shift register, a serial-to-parallel conversion circuit and a clock frequency dividing circuit; the input interface circuit receives an external input frequency-jittering amplitude control signal Set and converts it into an input frequency-jittering amplitude control signal Set_in of an internal level standard and outputs it to the serial shift register; the serial shift register receives the input frequency-jittering amplitude control signal Set_in in chronological order under the control of the frequency-jittering relative amplitude control clock ck_sel and obtains a serial output J-bit input frequency-jittering amplitude control code Sel_ins and outputs it to the serial-to-parallel conversion circuit; the serial-to-parallel conversion circuit performs serial-to-parallel conversion on the J-bit serial output input frequency-jittering amplitude control code Sel_ins under the control of the frequency-jittering relative amplitude control clock ck_sel to obtain a J-bit frequency-jittering relative amplitude selection signal Sel; the clock frequency dividing circuit performs serial-to-parallel conversion on the frequency-jittering relative amplitude control clock ck_sel and converts the J-bit serial output input frequency-jittering amplitude control code Sel_ins to obtain a J-bit frequency-jittering relative amplitude selection signal Sel; the clock frequency dividing circuit performs serial-to-parallel conversion on the frequency-jittering relative amplitude control clock ck_sel The frequency-jittering control clock ck_dith fed back by the reference voltage generating circuit is divided to obtain the frequency-jittering relative amplitude control clock ck_sel, which is output to the control serial shift register and the serial-to-parallel conversion circuit respectively; the operation of the above circuits is controlled by the control signal Ctrl. When the Ctrl signal is 0, the input interface circuit, the serial shift register, the serial-to-parallel conversion circuit and the clock frequency dividing circuit do not receive external signals, and the J-bit frequency-jittering relative amplitude selection signal Sel output by the frequency-jittering relative amplitude control circuit remains locked unchanged; when the Ctrl signal is 1, the input interface circuit, the serial shift register, the serial-to-parallel conversion circuit and the clock frequency dividing circuit all work normally and start to receive external signal input signals. The J-bit frequency-jittering relative amplitude selection signal Sel output by the frequency-jittering relative amplitude control circuit changes according to the external input frequency-jittering amplitude control signal Set.

[0013] Specifically, the clock generation and coupling output circuit includes: an inverter Inv800, an inverter Inv801, an inverter Inv802, a buffer Buf80, a PMOS tube M81, a PMOS tube M82, an NMOS tube M83, an NMOS tube M84, a PMOS tube M85, an NMOS tube M86, a PMOS tube M87, an NMOS tube M88, X+1 output inverters, a capacitor C80, a resistor R80, a capacitor C81, a resistor R81, a capacitor C82 and a resistor R82, where X is any positive integer; wherein the inverter Inv800, the inverter Inv801, and the inverter Inv802 are connected in sequence. A reference clock ring oscillator is formed, where the output of the inverter Inv802 is connected to the input of the inverter Inv800. The output of the reference clock ring oscillator is the output of the inverter Inv902, which is connected to the input of the buffer Buf80. The output of the buffer Buf80 is the reference clock signal OSC_out. The power supply voltages of the inverters Inv800, Inv801, Inv802, and Buf80 are all connected to the oscillator power supply voltage VCC_OSC. The ground terminals of the inverters Inv800, Inv801, and Inv802 are all connected to the ground voltage GND.

[0014] The left side of capacitor C80 is connected to the reference clock signal OSC_out, and the right side of capacitor C80 is connected to the upper end of resistor R80, the lower end of capacitor C81, and the upper end of capacitor C82; the upper end of capacitor C81 is connected to the lower end of resistor R81 and the gate of PMOS transistor M85, and the lower end of capacitor C82 is connected to the upper end of resistor R82 and the gate of NMOS transistor M86; the upper end of resistor R81 is connected to the drain of PMOS transistor M82, the lower end of resistor R82 is connected to the drain of NMOS transistor M84, and the gate of PMOS transistor M82 is connected to the drain of PMOS transistor M81, the gate of PMOS transistor M81, the drain of NMOS transistor M83, the gate of NMOS transistor M83, and the gate of NMOS transistor M84; PMOS transistor M85 The drain of the transistor M87 is connected to the drain of the NMOS transistor M86, the gate of the PMOS transistor M87, and the gate of the NMOS transistor M88; the drain of the PMOS transistor M87 is connected to the drain of the NMOS transistor M88 and is also connected to the input ends of X+1 output inverters; the output ends of the X+1 output inverters respectively provide a feedback clock signal CK_fb and X output clock signals CK1 to CKX; the lower end of the resistor R80, the source of the NMOS transistor M83, the source of the NMOS transistor M84, the source of the NMOS transistor M86, and the source of the NMOS transistor M88 are all connected to the ground voltage GND; the source of the PMOS transistor M81, the source of the PMOS transistor M82, the source of the PMOS transistor M85, and the source of the PMOS transistor M87 are all connected to the power supply voltage VCC.

[0015] The advantages of the present invention are: on the one hand, the oscillator power supply voltage VCC_OSC used in the clock generation circuit is only controlled by the reference signal and is not affected by PVT fluctuations, thereby ensuring the frequency stability of the reference clock signal OSC_out; on the other hand, a pseudo-random code with pseudo-random characteristics in both amplitude and time is used inside the pseudo-random modulation power supply generation circuit to modulate VCC_OSC, so that the frequency of the reference clock signal OSC_out has a random frequency jitter characteristic, thereby achieving the goal of reducing EMI interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a circuit structure block diagram of the present invention.

[0017] Figure 2 This is an embodiment of the error amplification and buffer circuit of the present invention.

[0018] Figure 3 This is an embodiment of the frequency-jittering reference voltage generating circuit of the present invention.

[0019] Figure 4 A schematic diagram of the frequency-jittering reference voltage Vrdith generated by the present invention.

[0020] Figure 5 for Figure 3 An embodiment of a pseudo-random code generating circuit.

[0021] Figure 6 This is an embodiment of the frequency jitter relative amplitude control circuit of the present invention.

[0022] Figure 7 This is a schematic diagram of the working waveform of the frequency jitter relative amplitude control circuit.

[0023] Figure 8 This is an embodiment of the clock generation and coupling output circuit of the present invention.

[0024] Figure 9 This is a schematic diagram of the application of the present invention in an AC-DC controller circuit. DETAILED DESCRIPTION

[0025] The present invention will be further described in detail below with reference to the accompanying drawings and examples.

[0026] like Figure 1As shown, the low-EMI clock generation circuit for high-voltage integrated circuits according to the present invention includes: a frequency-jittering relative amplitude control circuit 10, a frequency-jittering reference voltage generation circuit 11, an error amplification and buffering circuit 12, and a clock generation and coupling output circuit 13. The frequency-jittering relative amplitude control circuit 10 generates a frequency-jittering relative amplitude selection signal Sel based on an external input frequency-jittering amplitude control signal Set and a frequency-jittering control clock ck_dith fed back by the frequency-jittering reference voltage generation circuit 11. The frequency-jittering reference voltage generation circuit 11 generates a frequency-jittering reference voltage Vrdith based on the frequency-jittering relative amplitude selection signal Sel generated by the frequency-jittering relative amplitude control circuit 10. The error amplification and buffering circuit 12 generates an oscillator power supply voltage VCC_OSC based on the frequency-jittering reference voltage Vrdith and a feedback clock CK_fb output by the clock generation and coupling output circuit 13. The clock generation and coupling output circuit 13 generates X-channel output clocks CK1 to CKX and a feedback clock CK_fb based on the oscillator power supply voltage VCC_OSC.

[0027] Because high-voltage integrated circuits typically need to provide large currents, both the chip supply voltage VCC and the chip temperature fluctuate significantly. Therefore, the output frequency of the on-chip clock signal within the chip is particularly susceptible to PVT fluctuations. The present invention provides a solution that limits the impact of PVT fluctuations on the frequency of the output clocks CK1 to CKX by using a feedback clock CK_fb to feedback-control the oscillator supply voltage VCC_OSC generated by the error amplification and buffering circuit 12, ultimately maintaining the stability of the output clocks CK1 to CKX. Assuming that a temperature increase causes the frequency of the feedback clock CK_fb to decrease, the error amplification and buffering circuit 12 will adjust the oscillator supply voltage VCC_OSC based on the changes in the feedback clock CK_fb, increasing the oscillator supply voltage VCC_OSC and ultimately compensating for the temperature fluctuations on the frequency of the output clocks CK1 to CKX.

[0028] The present invention implements a measure to reduce EMI by performing frequency jittering on the output frequency of the clock signal. By increasing the bandwidth of the switching frequency controlled by the switching power supply, the power spectrum density and energy of the switching frequency are reduced, ultimately reducing the EMI peak energy output by the entire switching power supply and reducing EMI interference. The present invention generates a frequency jittering reference voltage Vrdith through a frequency jittering relative amplitude control circuit 10 and a frequency jittering reference voltage generation circuit 11. The frequency jittering reference voltage Vrdith and the feedback clock CK_fb are then compensated for differences within an error amplification and buffer circuit 12 to generate an oscillator power supply voltage VCC_OSC. The frequency jittering reference voltage Vrdith is controlled by a pseudo-random code, so the generated oscillator power supply voltage VCC_OSC has a pseudo-random jitter characteristic, thereby converting the output clock signals CK1 to CKX into frequency jittering clocks, thereby achieving the goal of reducing EMI interference.

[0029] like Figure 2 As shown, an embodiment of the error amplification and buffer circuit 12 of the present invention includes: a PMOS transistor M200, a PMOS transistor M201, a PMOS transistor M202, a PMOS transistor M203, a PMOS transistor M205, a PMOS transistor M206, a PMOS transistor M211, a PMOS transistor M221, an NMOS transistor M208, an NMOS transistor M209, an NMOS transistor M210, an NMOS transistor M222, a resistor R21 and a capacitor C21, a resistor R221, a resistor R222 and a capacitor C221.

[0030] The drain of the PMOS transistor M200 is connected to the upper end of the resistor R221, the lower end of the resistor R221 is connected to the upper end of the resistor R222, the source of the PMOS transistor M221, and the gate of the PMOS transistor M205; the gate of the PMOS transistor M221 and the gate of the NMOS transistor M222 are connected to the feedback clock CK_fb; the drain of the PMOS transistor M221 and the drain of the NMOS transistor M222 are connected and connected to the upper end of the capacitor C221; the drain of the PMOS transistor M201 is connected to the PMOS transistor M205. The source of the S transistor M205 and the source of the PMOS transistor M206; the drain of the PMOS transistor M205 is connected to the gate and drain of the NMOS transistor M208, and the gate of the NMOS transistor M209; the gate of the PMOS transistor M206 is connected to the frequency-jittering reference voltage Vrdith, the drain of the PMOS transistor M206 is connected to the drain of the NMOS transistor M209, the gate of the NMOS transistor M210 and the upper end of the resistor R21; the lower end of the resistor R21 is connected to the upper end of the capacitor C21; NMOS The drain of the OS transistor M210 is connected to the drain of the PMOS transistor M202 and the gate of the PMOS transistor M211; the source of the PMOS transistor M211 is connected to the lower end of the resistor R23 and the upper end of the capacitor C22, and also serves as the oscillator power supply voltage VCC_OSC port; the upper end of the resistor R23 is connected to the drain of the PMOS transistor M203; the gates of the PMOS transistors M200, M201, M202, and M203 are all connected to The bias voltage Vbc21; the source of the NMOS transistor M208, the source of the NMOS transistor M209, the source of the NMOS transistor M222, the lower end of the capacitor C221, the lower end of the capacitor C21, the lower end of the resistor R222, the drain of the PMOS transistor M211, and the lower end of the capacitor C22 are all connected to the ground voltage GND; the source of the PMOS transistor M200, the source of the PMOS transistor M201, the source of the PMOS transistor M202, and the source of the PMOS transistor M203 are all connected to the power supply voltage VCC.

[0031] Figure 2In the circuit shown, the PMOS transistor M201, PMOS transistor M202, PMOS transistor M205, PMOS transistor M206, NMOS transistor M208, NMOS transistor M209, NMOS transistor M210, resistor R21, and capacitor C21 form a two-stage error amplifier; the PMOS transistor M203, PMOS transistor M211, resistor R23, and capacitor C22 form a follower buffer; and the PMOS transistor M200, PMOS transistor M221, NMOS transistor M222, resistor R221, resistor R222, and capacitor C221 form a feedback clock detection circuit. The input end of the feedback clock detection circuit is the feedback clock CK_fb, and the output end of the feedback clock detection circuit is the clock feedback voltage Vckfb, which is connected to the first differential input end of the two-stage error amplifier, that is, the gate of the PMOS tube M205; the second differential input end of the two-stage error amplifier is the gate of the PMOS tube M206, which is connected to the frequency-jittering reference voltage Vrdith; the amplified output end of the two-stage error amplifier is connected to the drain of the PMOS tube M202 and the drain of the NMOS tube M210, and is connected to the signal input end of the follower buffer, that is, the gate of the PMOS tube M211; the signal output end of the follower buffer is the oscillator power supply voltage VCC_OSC.

[0032] Figure 2 Under the control of the feedback clock CK_fb, the PMOS transistor M221 and NMOS transistor M222 charge and discharge capacitor C221, causing capacitor C221 to form an equivalent impedance RC221. The resistance formed by connecting RC221 in parallel with R222 divides the voltage with R221 to produce the final clock feedback voltage Vckfb. As the frequency of the feedback clock CK_fb increases, the equivalent impedance RC221 decreases; as the frequency of the feedback clock CK_fb decreases, the equivalent impedance RC221 increases. The voltage of Vckfb accurately reflects the frequency of the feedback clock CK_fb, and the frequency changes of the feedback clock CK_fb are accurately reflected in the oscillator power supply voltage VCC_OSC. When the frequency of the feedback clock CK_fb is too low, the oscillator power supply voltage VCC_OSC increases; when the frequency of the feedback clock CK_fb is too high, the oscillator power supply voltage VCC_OSC decreases.

[0033] like Figure 3 As shown, an embodiment of the frequency-jittering reference voltage generating circuit of the present invention includes: Y+N voltage-dividing resistor strings connected in series, Y+N NMOS transistors, a coding conversion circuit 31 and a pseudo-random code generating circuit 32, where Y=2 J , J is any positive integer; N = 2 K, K is an arbitrary positive integer. The first Y resistors (resistors R311 to R31Y) are connected in series to form a frequency-jittering relative amplitude adjustment resistor string, and the last N resistors (resistors R331 to R33N) are connected in series to form a frequency-jittering absolute amplitude adjustment resistor string. The upper end of the frequency-jittering relative amplitude adjustment resistor string is connected to the upper end of resistor R311 and is connected to the reference voltage Vref; the lower end of the frequency-jittering relative amplitude adjustment resistor string is connected to the upper end of the frequency-jittering absolute amplitude adjustment resistor string and generates the frequency-jittering reference voltage Vrdith; the lower end of the frequency-jittering absolute amplitude adjustment resistor string is connected to the lower end of resistor R33N and is connected to ground voltage GND. The drain and source of the Y NMOS transistors M311 to M31Y are connected to the upper and lower ends of the first Y resistors, respectively, and the drain and source of the N NMOS transistors M331 to M33N are connected to the upper and lower ends of the last N resistors, respectively.

[0034] The input end of the code conversion circuit 31 is connected to the frequency-jittering relative amplitude selection signal Sel, and the output end of the code conversion circuit 31 is the Y-bit selection codes S1~SY, which are respectively connected to the gates of Y NMOS transistors M311~M31Y; the output end of the pseudo-random code generation circuit 32 is the N-bit pseudo-random codes P1~PN and the frequency-jittering control clock ck_dith, and the N-bit pseudo-random codes P1~PN are respectively connected to the gates of N NMOS transistors M331~M33N. That is, the selection code S1 output by the code conversion circuit 31 is connected to the gate of the NMOS transistor M311, the selection code S2 output by the code conversion circuit 31 is connected to the gate of the NMOS transistor M312, and so on. The selection code SY output by the code conversion circuit 31 is connected to the gate of the NMOS transistor M31Y; the pseudo-random code P1 output by the pseudo-random code generation circuit 32 is connected to the gate of the NMOS transistor M331, the pseudo-random code P2 output by the pseudo-random code generation circuit 32 is connected to the gate of the NMOS transistor M332, and so on. The pseudo-random code PN output by the pseudo-random code generation circuit 32 is connected to the gate of the NMOS transistor M33N.

[0035] Figure 3In the embodiment of the present invention, the frequency-jittering reference voltage Vrdith is obtained by dividing the total resistance Rs31 of the frequency-jittering relative amplitude adjustment resistor string and the total resistance Rs33 of the frequency-jittering absolute amplitude adjustment resistor string. The total resistance Rs31 of the frequency-jittering relative amplitude adjustment resistor string is controlled by the frequency-jittering relative amplitude selection signal Sel, and the total resistance Rs33 of the frequency-jittering absolute amplitude adjustment resistor string is controlled by an N-bit pseudo-random code. Therefore, the frequency-jittering reference voltage Vrdith has a pseudo-random characteristic on the one hand, and its relative amplitude relative to the reference voltage is also controlled by the frequency-jittering relative amplitude selection signal Sel on the other hand. In the embodiment of the present invention, the resistance values of any two resistors in the N series resistors of the frequency-jittering absolute amplitude adjustment resistor string are different, and the resistance value of a single resistor in the N resistors is selected using a pseudo-random distribution, that is, the ratio between any two resistors is different. In this way, it is possible to ensure that the voltage amplitude differences between the frequency-jittering reference voltages Vrdith under the control of different pseudo-random codes are different, thereby realizing the random characteristics of the amplitude of the frequency-jittering reference voltage Vrdith. The pseudo-random code generation circuit 32 generates N bits of pseudo-random codes P1-PN. At any given moment, only one bit of the pseudo-random code outputs a high level, while the remaining N-1 bits are all low levels. Furthermore, the duration of time that any one of the N bits of pseudo-random codes P1-PN outputs a high level varies. This ensures that the effective duration of any voltage among the frequency-jittering reference voltages Vrdith controlled by different pseudo-random codes is different, thereby achieving a temporal random characteristic of the frequency-jittering reference voltage Vrdith. Figure 3 In the embodiment, the Y-bit selection code output by the code conversion circuit 31 adopts a thermometer code or other binary code. If the Y-bit selection code is a thermometer code and the frequency-jittering relative amplitude selection signal Sel is a binary code, the code conversion circuit 31 needs to convert the W-bit frequency-jittering relative amplitude selection signal Sel code into a Y-bit selection code, and Y=2 J , J is an arbitrary positive integer. Meanwhile, the Y resistors in the frequency jitter relative amplitude adjustment resistor string need to be formed by Y resistors with the same resistance value connected in series.

[0036] Figure 4 The present invention is shown Figure 3The waveform of the frequency-jittering reference voltage Vrdith formed by the frequency-jittering reference voltage generating circuit is shown in the figure. The figure shows a schematic diagram of 32 different frequency-jittering reference voltages Vrdith implemented by using an 8-bit pseudo-random code and a 2-bit frequency-jittering relative amplitude selection signal Sel code control. It can be seen that after adopting the 8-bit pseudo-random code, the frequency-jittering reference voltage Vrdith provided by the present invention not only has pseudo-random characteristics in amplitude, but also has pseudo-random characteristics in time, thereby being closer to the natural noise signal, and as the number of pseudo-random code bits increases, the frequency-jittering reference voltage Vrdith is closer to the natural noise signal. In addition, the 2-bit frequency-jittering relative amplitude selection signal Sel code adopts binary code, with a total of four states of 00 / 01 / 10 / 11. When the frequency-jittering relative amplitude selection signal Sel code = 00, the corresponding total resistance Rs31 of the frequency-jittering relative amplitude adjustment resistor string is the maximum value, and the adjustment amplitude (⊿Rs33) of Rs33 by the 8-bit pseudo-random code is the lowest relative to the total resistance Rs31+Rs33; when the frequency-jittering relative amplitude selection signal Sel code = 01, the corresponding total resistance Rs31 of the frequency-jittering relative amplitude adjustment resistor string is reduced to a certain extent, and the adjustment amplitude (⊿Rs33) of Rs33 by the 8-bit pseudo-random code is the lowest relative to the total resistance Rs31+Rs33. The ratio of the total resistance Rs31+Rs33 is relatively increased; when the frequency-jittering relative amplitude selection signal Sel code = 10, the total resistance Rs31 of the corresponding frequency-jittering relative amplitude adjustment resistor string is further reduced, and the adjustment amplitude (⊿Rs33) of Rs33 by the 8-bit pseudo-random code relative to the total resistance Rs31+Rs33 is further increased; when the frequency-jittering relative amplitude selection signal Sel code = 11, the total resistance Rs31 of the corresponding frequency-jittering relative amplitude adjustment resistor string is minimum, and the adjustment amplitude (⊿Rs33) of Rs33 by the 8-bit pseudo-random code relative to the total resistance Rs31+Rs33 reaches the maximum. By adjusting the frequency-jittering relative amplitude selection signal Sel code, the degree of deviation of the pseudo-random modulation signal amplitude from the average value of the frequency-jittering reference voltage Vrdith can be flexibly adjusted, thereby increasing the applicable scenarios of the frequency-jittering reference voltage generation circuit.

[0037] like Figure 5 As shown, an embodiment of the pseudo-random code generating circuit 32 of the present invention includes: a ring oscillator 50, a delay sequence generating circuit 51, a pseudo-random code circuit 52, a binary to thermometer code circuit 53 and a buffer 54 (Buf50); the ring oscillator 50 generates an initial control clock signal CLK and outputs it to the delay sequence generating circuit 51 and the buffer Buf50; the delay sequence generating circuit 51 generates 2 K+1 -1 clock signals Q1~Q(2 K+1 -1); the pseudo-random encoding circuit 52 will 2 K+1 -1 clock signals Q1~Q(2 K+1-1) random coding is converted into K-bit binary data signals D1~DK; the binary to thermometer coding circuit 53 converts the K-bit binary data signals D1~DK into codes to obtain 2 K Bit thermometer code P1~P2 K ; 2 K Bit thermometer code P1~P2 K That is, the N-bit pseudo-random code finally output by the pseudo-random code generating circuit 32; N=2 K , K is a positive integer. The buffer Buf50 isolates and buffers the received initial control clock signal CLK to obtain a frequency-jittering control clock ck_dith, which is used to control the working state of the frequency-jittering relative amplitude control circuit of the present invention.

[0038] The delay sequence generating circuit 51 includes 2 K+1 -1 cascaded identical delay unit and an XOR gate XOR51; the delay unit includes a clock input, a data input, and a data output; except for the first delay unit, the clock input of all other delay units is connected to the initial control clock signal CLK, the data input is connected to the data output of the previous delay unit, and the data output is connected to the data input of the next delay unit; 2 K +1 -1 cascaded delay unit generates 2 K+1 -1 clock data signal Q1~Q(2 K+1 -1); the last two clock data signals Q(2 K+1 -1) and Q(2 K+1 -2), and then fed back through the XOR gate XOR51 and connected to the data input terminal of the first delay unit.

[0039] Figure 5 The pseudo-random code generation circuit 32 generates a total of 8 bits of pseudo-random code, so K = 3. The delay sequence generation circuit 51 internally utilizes 15 cascaded delay units, which sequentially generate 15 clock data signals Q1 to Q15 with varying time delays. The pseudo-random encoding circuit 52 utilizes a total of 15 tapped clock signals, each tap exhibiting no autocorrelation, and taps exhibiting no correlation with each other. Encoding yields the 3-bit binary pseudo-random code DA0, DA1, and DA2. The 3-bit binary pseudo-random code is then decoded to yield the 8-bit output thermometer pseudo-random code P1 to P8. The delay unit can be implemented using a basic D flip-flop or other clock-controlled logic gates.

[0040] like Figure 6As shown, an embodiment of the frequency-jittering relative amplitude control circuit 10 of the present invention includes: an input interface circuit 60, a serial shift register 61, a serial-to-parallel conversion circuit 62 and a clock frequency dividing circuit 63; wherein the input interface circuit 60 receives an external input frequency-jittering amplitude control signal Set and converts it into an input frequency-jittering amplitude control signal Set_in of an internal level standard; under the control of the frequency-jittering relative amplitude control clock ck_sel, the serial shift register 61 receives the input frequency-jittering amplitude control signal Set_in in chronological order and obtains a serial output J-bit input frequency-jittering amplitude control code Sel_ins; under the control of the frequency-jittering relative amplitude control clock ck_sel, the serial-to-parallel conversion circuit 62 performs serial-to-parallel conversion on the J-bit serial output input frequency-jittering amplitude control code Sel_ins to obtain a J-bit frequency-jittering relative amplitude selection signal Sel; the clock frequency dividing circuit 63 performs serial-to-parallel conversion on the frequency-jittering reference voltage generating circuit 1 1 is fed back by the frequency-dividing control clock ck_dith to obtain the frequency-dividing relative amplitude control clock ck_sel, which is used to control the serial shift register 61 and the serial-to-parallel conversion circuit 62; the operation of the above circuits is controlled by the control signal Ctrl. When the Ctrl signal is 0, the input interface circuit 60, the serial shift register 61, the serial-to-parallel conversion circuit 62 and the clock frequency dividing circuit 63 do not receive external signals, and the J-bit frequency-dividing relative amplitude selection signal Sel output by the frequency-dividing relative amplitude control circuit remains locked; when the Ctrl signal is 1, the input interface circuit 60, the serial shift register 61, the serial-to-parallel conversion circuit 62 and the clock frequency dividing circuit 63 all operate normally and start to receive external signal input signals, and the J-bit frequency-dividing relative amplitude selection signal Sel output by the frequency-dividing relative amplitude control circuit changes according to the external input frequency-dividing amplitude control signal Set; J is an arbitrary positive integer.

[0041] Figure 6 The circuit's function is to receive an externally input frequency-jittering amplitude control signal Set and convert it into a J-bit frequency-jittering relative amplitude selection signal Sel at an internal chip level. The externally input frequency-jittering amplitude control signal Set is a J-bit serial signal, so only one control port is required for J-bit data transmission. This minimizes the number of off-chip control ports in the present invention, reducing chip area and costs. Figure 6The input interface circuit 60 described in the embodiment can be realized by using a conventional logic level receiving circuit, which usually includes an ESD circuit and a level comparison circuit; the serial shift register 61 and the serial-to-parallel conversion circuit 62 can also be realized by using various existing conventional circuits; the clock frequency dividing circuit 63 can be realized by using an L-level T trigger (L is any positive integer), and the output frequency-dividing relative amplitude control clock ck_sel is divided by a multiple relative to the frequency-dividing control clock ck_dith, which depends on the level L of the T trigger. The control signal Ctrl can be provided from inside the chip or from outside the chip. When the Ctrl signal is 1, the external input frequency-dividing amplitude control signal Set changes the frequency-dividing relative amplitude selection signal Sel, thereby controlling the present invention. Figure 3 The relative jitter amplitude of the frequency jittering reference voltage Vrdith shown in FIG is adjusted.

[0042] Figure 7 Figure 1 is a schematic diagram of the operating waveforms of the frequency-jitter relative amplitude control circuit 10 of the present invention. The operation of each functional module within the circuit is controlled by the control signal Ctrl. When the Ctrl signal is 0, the input interface circuit 60, serial shift register 61, serial-to-parallel conversion circuit 62, and clock frequency divider circuit 63 receive no external signals. The serial shift register 61 and serial-to-parallel conversion circuit 62 are in a data-holding state. The J-bit frequency-jitter relative amplitude selection signal Sel output by the frequency-jitter relative amplitude control circuit remains locked and unchanged, in a data-holding state. When the Ctrl signal is 1, the input interface circuit 60, serial shift register 61, serial-to-parallel conversion circuit 62, and clock divider circuit 63 all operate normally and begin receiving external input signals. The clock divider circuit 63 divides the frequency-jittering control clock ck_dith to generate the frequency-jittering relative amplitude control clock ck_sel. The division multiple is determined by the number of T-flip-flop stages within the circuit. The input interface circuit 60 receives the external input frequency-jittering amplitude control signal Set and converts it into an internal standard input frequency-jittering amplitude control signal Set_in. Under the control of the frequency-jittering relative amplitude control clock ck_sel, the serial shift register 61 sequentially receives the input frequency-jittering amplitude control signal Set_in in chronological order and generates a serial output of a J-bit input frequency-jittering amplitude control code Sel_ins, i.e., d1d2d3 to dJ-1dJ. The serial-to-parallel conversion circuit 62, under the control of the frequency-jittering relative amplitude control clock ck_sel, performs serial-to-parallel conversion on the J-bit serial output input frequency-jittering amplitude control code Sel_ins to generate a J-bit frequency-jittering relative amplitude selection signal Sel.

[0043] like Figure 8As shown, an embodiment of the clock generation and coupling output circuit 13 of the present invention includes: an inverter Inv800, an inverter Inv801, an inverter Inv802, a buffer Buf80, a PMOS transistor M81, a PMOS transistor M82, an NMOS transistor M83, an NMOS transistor M84, a PMOS transistor M85, an NMOS transistor M86, a PMOS transistor M87, an NMOS transistor M88, X+1 output inverters, a capacitor C80, a resistor R80, a capacitor C81, a resistor R81, a capacitor C82, and a resistor R82. X is any positive integer.

[0044] Among them, inverter Inv800, inverter Inv801, and inverter Inv802 constitute a reference clock ring oscillator, the output of the reference clock ring oscillator is connected to the input end of buffer Buf80, and the output end of buffer Buf80 is the reference clock signal OSC_out. The power supply voltage of inverter Inv800, inverter Inv801, inverter Inv802 and buffer Buf80 all use the oscillator power supply voltage VCC_OSC.

[0045] The left side of capacitor C80 is connected to the reference clock signal OSC_out, and the right side of capacitor C80 is simultaneously connected to the upper end of resistor R80, the lower end of capacitor C81, and the upper end of capacitor C82; the upper end of capacitor C81 is connected to the lower end of resistor R81 and the gate of PMOS tube M85, and the lower end of capacitor C82 is connected to the upper end of resistor R82 and the gate of NMOS tube M86; the upper end of resistor R81 is connected to the drain of PMOS tube M82, the lower end of resistor R82 is connected to the drain of NMOS tube M84, and the gate of PMOS tube M82 is simultaneously connected to the drain and gate of PMOS tube M81. The drain and gate of the NMOS transistor M83 and the gate of the NMOS transistor M84; the drain of the PMOS transistor M85 is connected to the drain of the NMOS transistor M86, and is also connected to the gates of the PMOS transistor M87 and the NMOS transistor M88; the drain of the PMOS transistor M87 is connected to the drain of the NMOS transistor M88, and is also connected to the input ends of X+1 output inverters Inv83 and Inv831 to Inv83X; the output end of the output inverter Inv83 provides a feedback clock signal CK_fb, and the output ends of Inv831 to Inv83X provide X output clock signals CK1 to CKX respectively. The lower end of the resistor R80, the source of the NMOS transistor M83, the source of the NMOS transistor M84, the source of the NMOS transistor M86, and the source of the NMOS transistor M88 are all connected to the ground voltage GND; the source of the PMOS transistor M81, the source of the PMOS transistor M82, the source of the PMOS transistor M85, and the source of the PMOS transistor M87 are all connected to the power supply voltage VCC.

[0046] Figure 8The reference clock ring oscillator and buffer Buf80 generate a reference clock signal OSC_out based on the oscillator power supply voltage VCC_OSC. PMOS transistors M81, M82, NMOS transistors M83, and M84 form a self-bias circuit, providing a bias to the upper end of resistor R81 and the lower end of resistor R82. Capacitor C80 and resistor R80 form a high-pass filter to block the high and low DC components of the input clock. Capacitor C81 and resistor R81 form a second high-pass filter, while capacitor C82 and resistor R82 form a third high-pass filter. The outputs of the second and third high-pass filters are connected to the gates of PMOS transistors M85 and NMOS transistors M86, respectively. After the reference clock signal OSC_out undergoes two high-pass filtering stages, the resulting AC signal is passed through a push-pull amplifier circuit formed by PMOS transistors M85 and NMOS transistors M86 to generate a new clock signal with high and low level conversion and shifting. This signal is then buffered and shaped by the output inverter to produce the final output clock.

[0047] Figure 8 In this circuit, the reference clock signal OSC_out undergoes two stages of high-pass filtering before being shaped and buffered by cascaded inverters to produce multiple output clocks. This circuit's function is to convert an input clock swing of VCC_OSC into an output clock swing of VCC through capacitive coupling through the high-pass filter, achieving level conversion. The output clocks are powered by VCC, preventing even significant interference from feeding back into the input clocks, thus ensuring the stability of the reference clock signal OSC_out.

[0048] Figure 9 The AC-DC control chip can be divided into four functional modules according to its function:

[0049] (a) Reference generation module. The reference generation module mainly includes: a high-voltage regulator circuit, which receives the high voltage (7.6V to 26.2V) from the chip's VDD pin and converts it into an internal 5V power supply voltage, providing a stable low-voltage power supply for all low-voltage modules within the chip; a bandgap reference voltage source circuit, which generates a bandgap reference voltage with a high power supply rejection ratio and a near-zero temperature coefficient at room temperature, providing a reference level for the chip's internal circuit voltage; a reference current source circuit, which provides a reliable current reference for the chip's internal circuits; and an overvoltage and undervoltage protection circuit, which is used to determine the chip's minimum operating voltage and maximum shutdown voltage.

[0050] (b) Constant voltage control module. The constant voltage loop can be broadly divided into a constant voltage on-signal and a constant voltage off-signal generation loop. In the on-signal control loop, the output voltage is sampled and passed through the FB sample / hold circuit. The error amplifier EA and the negative feedback resistor together form an inverting amplifier with a fixed gain of 40. The FB sampled voltage is connected to the inverting input of the error amplifier via a resistor, and the non-inverting input of the error amplifier is connected to a 2.5V reference voltage. The error amplifier output voltage is sent to the PWM comparator to generate the power tube on-signal (CV_ON). The compV signal is then processed by a resistor divider and a filter and sent to CV_OCP to generate the power tube off-signal (CV_OFF) in constant voltage mode.

[0051] (c) Constant current control module. In the constant current loop, the main components are the constant current on-signal and the constant current off-signal. The primary peak current sampling signal, CS, is compared with the reference voltage of the transconductance amplifier via the CS sample-and-hold circuit. After being scaled by a buffer, it is fed into the comparator. CMP2 compares the output of the preceding circuit with the corresponding reference voltage, CS, to generate the corresponding constant current loop off-signal. The constant current on-signal utilizes a quasi-resonant valley conduction mode, enabling the switch to complete switching when the voltage crosses zero (ZVS), achieving valley conduction and generating the corresponding constant current loop on-signal.

[0052] (d) Logic control module. The system starts in constant current mode and determines the current load condition based on the sampled signals from each port. The logic control circuit selects the required constant voltage or constant current on / off signal and generates the drive signal for the power transistor, ultimately maintaining a constant output voltage or current.

[0053] (e) Oscillating clock module. Mainly includes the low EMI clock signal generating circuit and frequency dividing circuit described in the present invention, which are used to provide various basic clock signals and other signals such as sawtooth waves required by other functions of the chip. On the one hand, the oscillator power supply voltage used in the clock generating circuit of the present invention is only controlled by the reference signal and is not affected by PVT fluctuations, thereby ensuring the frequency stability of the reference clock signal; on the other hand, a pseudo-random code with pseudo-random characteristics in amplitude and time is used inside the pseudo-random modulation power supply generating circuit to modulate the oscillator power supply voltage, so that the frequency of the reference clock signal OSC_out has a random frequency jitter characteristic, thereby reducing EMI interference.

[0054] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A low EMI clock generation circuit for a high voltage integrated circuit, characterized in that: The invention comprises a frequency-jitter relative amplitude control circuit (10), a frequency-jitter reference voltage generating circuit (11), an error amplification and buffering circuit (12) and a clock generating and coupling output circuit (13), wherein the input end of the frequency-jitter relative amplitude control circuit (10) is connected to an external input frequency-jitter amplitude control signal Set and a frequency-jitter control clock ck_dith fed back by the frequency-jitter reference voltage generating circuit (11), and outputs a frequency-jitter relative amplitude selection signal Sel to the frequency-jitter reference voltage generating circuit (11); the frequency-jitter reference voltage generating circuit (11) generates a frequency-jitter relative amplitude selection signal Sel according to the frequency-jitter relative amplitude control circuit (10). The frequency-relative amplitude selection signal Sel is used to obtain a frequency-jittering reference voltage Vrdith, which is output to the error amplification and buffer circuit (12); the input end of the error amplification and buffer circuit (12) is connected to the frequency-jittering reference voltage Vrdith and the feedback clock CK_fb output by the clock generation and coupling output circuit (13), and an oscillator power supply voltage VCC_OSC is generated and output to the clock generation and coupling output circuit (13); the clock generation and coupling output circuit (13) generates X-channel output clocks CK1~CKX and the feedback clock CK_fb according to the oscillator power supply voltage VCC_OSC; The frequency-jittering reference voltage generating circuit (11) comprises: Y+N voltage-dividing resistor strings, Y+N NMOS transistors, a coding conversion circuit (31) and a pseudo-random code generating circuit (32) connected in series, Y=2 J , J is any positive integer; N=2 K , K is an arbitrary positive integer; the first Y resistors are connected in series to form a frequency jitter relative amplitude adjustment resistor string, and the last N resistors are connected in series to form a frequency jitter absolute amplitude adjustment resistor string; the upper ends of the first Y resistors are connected to the reference voltage Vref; the connection point of the first Y resistors and the last N resistors generates a frequency jitter reference voltage Vrdith; the lower ends of the last N resistors are connected to the ground voltage GND; the drain and source of the Y NMOS tubes M311~M31Y are respectively connected to the upper and lower ends of the first Y resistors, and the drain and source of the N NMOS tubes M331~M33N are respectively connected to the upper and lower ends of the first Y resistors. The upper and lower ends of the N resistors are connected correspondingly; the input end of the encoding conversion circuit (31) is connected to the frequency jitter relative amplitude selection signal Sel, and the output end of the encoding conversion circuit (31) is respectively Y-bit selection codes S1~SY, which are respectively connected to the gates of Y NMOS tubes M311~M31Y; the output end of the pseudo-random code generation circuit (32) is respectively N-bit pseudo-random codes P1~PN and the frequency jitter control clock ck_dith, and the N-bit pseudo-random codes P1~PN are respectively connected to the gates of N NMOS tubes M331~M33N; The frequency-jittering reference voltage Vrdith generated in the frequency-jittering reference voltage generating circuit (11) is obtained by dividing the total resistance Rs31 of the frequency-jittering relative amplitude adjustment resistor string and the total resistance Rs33 of the frequency-jittering absolute amplitude adjustment resistor string; the frequency-jittering reference voltage Vrdith has a pseudo-random characteristic on the one hand, and its relative amplitude relative to the reference voltage is also controlled by the frequency-jittering relative amplitude selection signal Sel on the other hand; the resistance values of any two resistors in the frequency-jittering absolute amplitude adjustment resistor string are different, and the ratio between any two resistors in the N resistors is different, thereby realizing the random characteristic of the amplitude of the frequency-jittering reference voltage Vrdith; the N-bit pseudo-random codes P1~PN generated by the pseudo-random code generating circuit (32) have only one pseudo-random code outputting a high level at any time, and the remaining N-1 bits are all low levels; and the time length of any one pseudo-random code in the N-bit pseudo-random codes P1~PN outputting a high level is different, thereby realizing the random characteristic of the frequency-jittering reference voltage Vrdith in time.

2. The low EMI clock generation circuit for a high voltage integrated circuit according to claim 1, wherein: The error amplification and buffer circuit (12) includes: a PMOS tube M200, a PMOS tube M201, a PMOS tube M202, a PMOS tube M203, a PMOS tube M205, a PMOS tube M206, a PMOS tube M211, a PMOS tube M221, an NMOS tube M208, an NMOS tube M209, an NMOS tube M210, an NMOS tube M222, a resistor R21 and a capacitor C21, a resistor R221, a resistor R222 and a capacitor C221; The drain of the PMOS transistor M200 is connected to the upper end of the resistor R221, the lower end of the resistor R221 is connected to the upper end of the resistor R222 and the source of the PMOS transistor M221, and is connected to the gate of the PMOS transistor M205 as the output point of the clock feedback voltage Vckfb; the gate of the PMOS transistor M221 and the gate of the NMOS transistor M222 are connected to the feedback clock CK_fb; the drain of the PMOS transistor M221 and the drain of the NMOS transistor M222 are connected, and are connected to the upper end of the capacitor C221; the PMOS The drain of the transistor M201 is connected to the source of the PMOS transistor M205 and the source of the PMOS transistor M206; the drain of the PMOS transistor M205 is connected to the gate of the NMOS transistor M208, the drain of the NMOS transistor M208, and the gate of the NMOS transistor M209; the gate of the PMOS transistor M206 is connected to the frequency-jittering reference voltage Vrdith, the drain of the PMOS transistor M206 is connected to the drain of the NMOS transistor M209, the gate of the NMOS transistor M210, and the upper end of the resistor R21; the lower end of the resistor R21 is connected to Connected to the upper end of capacitor C21; the drain of NMOS tube M210 is connected to the drain of PMOS tube M202 and the gate of PMOS tube M211; the source of PMOS tube M211 is connected to the lower end of resistor R23 and the upper end of capacitor C22, and serves as the oscillator power supply voltage VCC_OSC port; the upper end of resistor R23 is connected to the drain of PMOS tube M203; the gate of PMOS tube M200, the gate of PMOS tube M201, the gate of PMOS tube M202 and the gate of PMOS tube M203 are all connected to the bias voltage Vbc21; the source of the NMOS transistor M208, the source of the NMOS transistor M209, the source of the NMOS transistor M222, the lower end of the capacitor C221, the lower end of the capacitor C21, the lower end of the resistor R222, the drain of the PMOS transistor M211 and the lower end of the capacitor C22 are all connected to the ground voltage GND; the source of the PMOS transistor M200, the source of the PMOS transistor M201, the source of the PMOS transistor M202 and the source of the PMOS transistor M203 are all connected to the power supply voltage VCC.

3. The low EMI clock generation circuit for a high voltage integrated circuit according to claim 1, wherein: The pseudo-random code generating circuit (32) comprises: a ring oscillator (50), a delay sequence generating circuit (51), a pseudo-random encoding circuit (52), a binary to thermometer encoding circuit (53) and a buffer (54); the ring oscillator (50) generates an initial control clock signal CLK and outputs it to the delay sequence generating circuit (51) and the buffer (54); the delay sequence generating circuit (51) generates 2 K+1 -1 clock signal Q1~Q(2 K+1 -1) is output to a pseudo-random encoding circuit (52); the pseudo-random encoding circuit (52) converts 2 K+1 -1 clock signal Q1~Q(2 K+1 -1) is randomly encoded and converted into K-bit binary data signals D1~DK and output to a binary to thermometer encoding circuit (53); the binary to thermometer encoding circuit (53) performs encoding conversion on the K-bit binary data signals D1~DK to obtain 2 K Bit thermometer code P1~P2 K ; 2 K Bit thermometer code P1~P2 K That is, the N-bit pseudo-random code finally output by the pseudo-random code generating circuit (32); wherein N=2 K , K is a positive integer; the buffer (54) isolates and buffers the received initial control clock signal CLK to obtain a frequency jitter control clock ck_dith, which is used to control the working state of the frequency jitter relative amplitude control circuit (10); The delay sequence generating circuit (51) internally includes 2 K+1 -1 cascaded identical delay unit and an XOR gate XOR51; the delay unit includes a clock input, a data input, and a data output; except for the first delay unit, the clock input of all other delay units is connected to the initial control clock signal CLK, the data input is connected to the data output of the previous delay unit, and the data output is connected to the data input of the next delay unit; 2 K +1 -1 cascaded delay unit generates 2 K+1 -1 clock data signal Q1~Q(2 K+1 -1); the last two clock data signals Q (2 K+1 -1) and Q(2 K+1 -2) After passing through the XOR gate XOR51, the feedback is connected to the data input terminal of the first delay unit.

4. The low EMI clock generation circuit for a high voltage integrated circuit according to claim 1, wherein: The frequency-jitter relative amplitude control circuit (10) comprises: an input interface circuit (60), a serial shift register (61), a serial-to-parallel conversion circuit (62) and a clock frequency dividing circuit (63); the input interface circuit (60) receives an external input frequency-jitter amplitude control signal Set and converts it into an input frequency-jitter amplitude control signal Set_in of an internal level standard and outputs it to the serial shift register (61); the serial shift register (61) receives the input frequency-jitter amplitude control signal Set_in in chronological order under the control of the frequency-jitter relative amplitude control clock ck_sel and obtains a serial output J-bit input frequency-jitter amplitude control code Sel_ins and outputs it to the serial-to-parallel conversion circuit (62); the serial-to-parallel conversion circuit (62) performs serial-to-parallel conversion on the J-bit serial output input frequency-jitter amplitude control code Sel_ins under the control of the frequency-jitter relative amplitude control clock ck_sel to obtain a J-bit frequency-jitter relative amplitude selection signal Sel; the clock frequency dividing circuit (63) generates a frequency-jitter reference voltage. The frequency-jittering control clock ck_dith fed back by the circuit (11) is divided to obtain the frequency-jittering relative amplitude control clock ck_sel, which is output to the control serial shift register (61) and the serial-to-parallel conversion circuit (62) respectively; the operation of the above circuits is controlled by the control signal Ctrl. When the Ctrl signal is 0, the input interface circuit (60), the serial shift register (61), the serial-to-parallel conversion circuit (62) and the clock frequency division circuit (63) do not receive external signals, and the J-bit frequency-jittering relative amplitude selection signal Sel output by the frequency-jittering relative amplitude control circuit (10) remains locked unchanged; when the Ctrl signal is 1, the input interface circuit (60), the serial shift register (61), the serial-to-parallel conversion circuit (62) and the clock frequency division circuit (63) all operate normally and start to receive external signal input signals, and the J-bit frequency-jittering relative amplitude selection signal Sel output by the frequency-jittering relative amplitude control circuit (10) changes according to the external input frequency-jittering amplitude control signal Set.

5. The low EMI clock generation circuit for a high voltage integrated circuit according to claim 1, wherein: The clock generation and coupling output circuit (13) includes: an inverter Inv800, an inverter Inv801, an inverter Inv802, a buffer Buf80, a PMOS tube M81, a PMOS tube M82, an NMOS tube M83, an NMOS tube M84, a PMOS tube M85, an NMOS tube M86, a PMOS tube M87, an NMOS tube M88, X+1 output inverters, a capacitor C80, a resistor R80, a capacitor C81, a resistor R81, a capacitor C82 and a resistor R82, where X is an arbitrary positive integer; wherein the inverter Inv800, the inverter Inv801 and the inverter Inv802 are connected in sequence A reference clock ring oscillator is formed, where the output of the inverter Inv802 is connected to the input of the inverter Inv800. The output of the reference clock ring oscillator is the output of the inverter Inv902, which is connected to the input of the buffer Buf80. The output of the buffer Buf80 is the reference clock signal OSC_out. The power supply voltages of the inverters Inv800, Inv801, Inv802, and Buf80 are all connected to the oscillator power supply voltage VCC_OSC. The ground terminals of the inverters Inv800, Inv801, and Inv802 are all connected to the ground voltage GND. The left side of capacitor C80 is connected to the reference clock signal OSC_out, and the right side of capacitor C80 is connected to the upper end of resistor R80, the lower end of capacitor C81, and the upper end of capacitor C82; the upper end of capacitor C81 is connected to the lower end of resistor R81 and the gate of PMOS transistor M85, and the lower end of capacitor C82 is connected to the upper end of resistor R82 and the gate of NMOS transistor M86; the upper end of resistor R81 is connected to the drain of PMOS transistor M82, the lower end of resistor R82 is connected to the drain of NMOS transistor M84, and the gate of PMOS transistor M82 is connected to the drain of PMOS transistor M81, the gate of PMOS transistor M81, the drain of NMOS transistor M83, the gate of NMOS transistor M83, and the gate of NMOS transistor M84; PMOS transistor M85 The drain of the transistor M81 is connected to the drain of the NMOS transistor M86, the gate of the PMOS transistor M87, and the gate of the NMOS transistor M88; the drain of the PMOS transistor M87 is connected to the drain of the NMOS transistor M88 and is also connected to the input ends of X+1 output inverters; the output ends of the X+1 output inverters respectively provide a feedback clock signal CK_fb and X output clock signals CK1 to CKX; the lower end of the resistor R80, the source of the NMOS transistor M83, the source of the NMOS transistor M84, the source of the NMOS transistor M86, and the source of the NMOS transistor M88 are all connected to the ground voltage GND; the source of the PMOS transistor M81, the source of the PMOS transistor M82, the source of the PMOS transistor M85, and the source of the PMOS transistor M87 are all connected to the power supply voltage VCC.

Images