Interleaved stacked vertical crystalline semiconductor channels

Abstract

A semiconductor structure (100) includes a first semiconductor channel having a plurality of vertical nanowires (106) and a second semiconductor channel having a plurality of vertical nanowires (106). The first semiconductor channel and the second semiconductor channel are configured in a stacked configuration. The plurality of vertical nanowires (106) of the first semiconductor channel are configured to be in alternating positions relative to the plurality of vertical nanowires (106) of the second semiconductor channel.

Description

Background Technology

[0001] Stacking field-effect transistors (FETs) in the vertical direction provides additional dimensions for scaling complementary metal-oxide-semiconductor (CMOS) regions. In a typical CMOS layout, the first transistor is connected to at least the second transistor 90% of the time. For example, the drain of an n-type transistor is connected to the drain of a p-type transistor to form an inverter. Other arrangements are also considered, such as connections between the drain of a first transistor connected to the source of a second transistor, the drain of a first transistor connected to the drain of a second transistor, or the source of a first transistor connected to the source of a second transistor, where the first and second transistors can be any combination of n-type or p-type transistors.

[0002] Vertical field-effect transistors (VFETs) have a unique structure that facilitates stacking processes. Unlike planar CMOS devices, VFETs are oriented with a vertical fin channel disposed on the bottom source / drain and a top source / drain disposed on the fin channel. The gate extends vertically alongside the vertical fin channel. VFETs have been promoted as a potential device option for scaling CMOS to 5 nanometer (nm) nodes and beyond. Summary of the Invention

[0003] Embodiments of the present invention include structures and methods for forming staggered stacked vertical semiconductor channels. For example, one exemplary embodiment includes a semiconductor structure comprising: a first semiconductor channel including a plurality of vertical nanowires; and a second semiconductor channel including a plurality of vertical nanowires. The first and second semiconductor channels are configured in a stacked configuration. The plurality of vertical nanowires of the first semiconductor channel are configured to be in alternating positions relative to the plurality of vertical nanowires of the second semiconductor channel.

[0004] Another exemplary embodiment includes a logic device comprising one or more semiconductor structures. At least one of the one or more semiconductor structures includes a first semiconductor channel comprising a plurality of vertical nanowires; and a second semiconductor channel comprising a plurality of vertical nanowires. The first semiconductor channel and the second semiconductor channel are configured in a stacked configuration. The plurality of vertical nanowires of the first semiconductor channel are configured to be in alternating positions relative to the plurality of vertical nanowires of the second semiconductor channel.

[0005] Another exemplary embodiment includes an integrated circuit logic device comprising one or more semiconductor structures. At least one of the one or more semiconductor structures includes a first semiconductor channel comprising a plurality of vertical nanowires; and a second semiconductor channel comprising a plurality of vertical nanowires. The first semiconductor channel and the second semiconductor channel are configured in a stacked configuration. The plurality of vertical nanowires of the first semiconductor channel are configured to be in alternating positions relative to the plurality of vertical nanowires of the second semiconductor channel.

[0006] Another exemplary embodiment includes a method comprising forming a first semiconductor channel comprising a plurality of vertical nanowires and a second semiconductor channel comprising a plurality of vertical nanowires on a semiconductor substrate. The first semiconductor channel and the second semiconductor channel are configured in a stacked configuration. The plurality of vertical nanowires of the first semiconductor channel are configured to be in alternating positions relative to the plurality of vertical nanowires of the second semiconductor channel.

[0007] Another exemplary embodiment includes a method comprising forming a plurality of layered silicon-insulator-silicon nanowires from a surface of a substrate. The plurality of nanowires include a hard mask on their top surface. The method further includes forming pads on the outer surfaces of the alternately layered silicon-insulator-silicon nanowires. The pads are formed on a portion of a bottom silicon layer of an insulating layer extending to the hard mask and exposing the layered silicon-insulator-silicon nanowires. The method further includes forming a first oxide layer on the outer surfaces of other alternately layered silicon-insulator-silicon nanowires. The first oxide layer is formed on a portion of a top silicon layer of an insulating layer extending to the top surface of the substrate and exposing the layered silicon-insulator-silicon nanowires. The method further includes thermally oxidizing the exposed bottom silicon layer of the layered silicon-insulator-silicon nanowires and the exposed top silicon layer of the layered silicon-insulator-silicon nanowire silicon layers.

[0008] These and other features, objects, and advantages of the invention will become apparent from the following detailed description of illustrative embodiments of the invention, which are read in conjunction with the accompanying drawings. Attached Figure Description

[0009] Figure 1 It is a schematic cross-sectional side view of a semiconductor structure in a first intermediate manufacturing stage according to one or more exemplary embodiments.

[0010] Figure 2 This is a schematic cross-sectional side view of a semiconductor structure in a second intermediate manufacturing stage according to one or more exemplary embodiments.

[0011] Figure 3 It is a schematic cross-sectional side view of a semiconductor structure in a third intermediate manufacturing stage according to one or more exemplary embodiments.

[0012] Figure 4 This is a schematic cross-sectional side view of a semiconductor structure in a fourth intermediate manufacturing stage according to one or more exemplary embodiments.

[0013] Figure 5 This is a schematic cross-sectional side view of a semiconductor structure in the fifth intermediate stage of manufacturing, according to one or more exemplary embodiments.

[0014] Figure 6 This is a schematic cross-sectional side view of a semiconductor structure in a sixth intermediate manufacturing stage according to one or more exemplary embodiments.

[0015] Figure 7 This is a schematic cross-sectional side view of a semiconductor structure in the seventh intermediate stage of manufacturing, according to one or more exemplary embodiments.

[0016] Figure 8 This is a schematic cross-sectional side view of a semiconductor structure in the eighth intermediate stage of manufacturing, according to one or more exemplary embodiments.

[0017] Figure 9 This is a schematic cross-sectional side view of a semiconductor structure in the ninth intermediate stage of manufacturing, according to one or more exemplary embodiments.

[0018] Figure 10 It is a schematic cross-sectional side view of a semiconductor structure in the tenth intermediate stage of manufacturing, according to one or more exemplary embodiments.

[0019] Figure 11 This is a schematic cross-sectional side view of a semiconductor structure in the eleventh intermediate stage of manufacturing, according to one or more exemplary embodiments.

[0020] Figure 12 This is a schematic cross-sectional side view of a semiconductor structure in the twelfth intermediate stage of manufacturing, according to one or more exemplary embodiments. Detailed Implementation

[0021] This disclosure generally relates to semiconductor manufacturing techniques, and more specifically to structures and methods for fabricating staggered stacked vertical semiconductor channels used in the fabrication of vertical field-effect transistor devices. Vertically stacked VFETs make connecting the source / drain (S / D) contacts of the bottom FET difficult because it would require fabricating an "L"-shaped conductive material. Exemplary embodiments of vertically stacked crystalline semiconductor structures (or vertical fin arrays) wherein the semiconductor fins are staggered in spacing allow for simple and direct connection of the S / D contacts of the final bottom FET.

[0022] It should be understood that the various layers, structures, and regions shown in the accompanying drawings are schematic diagrams not drawn to scale. Furthermore, for ease of interpretation, one or more layers, structures, and regions of types typically used to form semiconductor devices or structures may not be explicitly shown in a given drawing. This does not imply that any layers, structures, and regions not explicitly shown have been omitted from an actual semiconductor structure.

[0023] Furthermore, it should be understood that the embodiments discussed herein are not limited to the specific materials, features, and processing steps shown and described herein. In particular, regarding semiconductor processing steps, it is emphasized that the description provided herein is not intended to include all processing steps that may be necessary to form a functional semiconductor integrated circuit device. Rather, for the sake of economics, certain processing steps commonly used in forming semiconductor devices, such as wet cleaning and annealing steps, are intentionally omitted here.

[0024] Furthermore, the same or similar reference numerals are used in all the accompanying drawings to denote the same or similar features, elements, or structures; therefore, detailed explanations of the same or similar features, elements, or structures will not be repeated for each drawing. It should be understood that the terms "about" or "substantially" used herein with respect to thickness, width, percentage, range, etc., are intended to indicate approximation or approximation, not precision. For example, as used herein, the terms "about" or "substantially" imply that a small margin of error may exist, such as 1% or less compared to the stated amount.

[0025] The following will refer to Figure 1-12 Illustrative embodiments for forming semiconductor structures are discussed. Referring now to the accompanying drawings, Figure 1 This is a cross-sectional view of a semiconductor structure 100 including a semiconductor substrate 102 and a hard mask layer 104. The semiconductor substrate 102 may comprise a conventional type of silicon-on-insulator (SOI) substrate wafer, such as an extremely thin silicon-on-insulator (ETSOI) or an ultra-thin body and buried oxide (UTBB) silicon-on-insulator (SOI) known to those skilled in the art. Alternatively, the semiconductor substrate 102 may comprise a bulk semiconductor substrate wafer. As shown, the substrate 102 may initially comprise a base layer 102a, such as silicon. An insulating layer 102b, such as a buried oxide layer, may be formed on the base layer 102a. A silicon layer 102c is then formed on the insulating layer 102b, although the silicon layer 102c may also be any other suitable semiconductor layer. In one embodiment, the substrate 102 is a layered silicon-insulator-silicon substrate.

[0026] The semiconductor material of the top semiconductor layer or the bulk substrate of the SOI substrate can be doped to suit integrated circuit applications. In one illustrative embodiment of the SOI substrate, the top semiconductor layer may be in a fully depleted (FD) configuration. The bulk substrate may include, for example, multiple epitaxially grown semiconductor layers. The process techniques described herein are equally applicable to SOI and bulk substrates, as well as other types of substrates.

[0027] The hard mask layer 104 is deposited on the substrate 102 using any conventional deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or other similar processes. Suitable materials for the hard mask layer 104 include, for example, TiN, SiO2, TaN, SiN, AlOx, SiC, etc. The hard mask layer 104 can then be planarized using a planarization process, such as chemical mechanical planarization (CMP).

[0028] Figure 2 The diagram illustrates the next step in forming vertically stacked fins for the semiconductor structure 100, wherein the semiconductor structure 100 is patterned to form a set of vertical nanowires 106. The vertical nanowires 106 have substantially vertical sidewalls. Although... Figure 2 Four vertical nanowires 106 are shown, but the number of vertical nanowires 106 should not be considered limiting. To form the vertical nanowires 106, lithography and etching are performed using any type of patterning technique, such as direct printing lithography or sidewall image transfer (SIT) processes. Direct printing lithography can be either 193i lithography or extreme ultraviolet (EUV) lithography, as is well known to those skilled in the art. SIT processes can be referred to as self-aligned double patterning (SADP) processes. In some embodiments, SIT processes can be used to pattern narrow lines of a hard mask 104. For example, lithography may include forming a photoresist (not shown) on the hard mask layer 104, exposing the photoresist to a desired radiation pattern, and then developing the exposed photoresist using a resist developer to provide patterned photoresist on top of the hard mask layer 104.

[0029] The pattern is transferred from the patterned photoresist to the hard mask layer 104 and the substrate 102 using at least one etching operation. Vertical nanowires 106 are formed by deep etching into but not through the substrate 102. For example, etching is performed by etching through a portion of the hard mask layer 104, silicon layer 102c, insulating layer 102b, and base layer 102a to form the vertical nanowires 106. The etching process can be dry etching (e.g., reactive ion etching, plasma etching, ion beam etching, or laser ablation). The etching process can also be wet chemical etching (e.g., with potassium hydroxide, or sulfuric acid and hydrogen peroxide). Both dry etching and wet chemical etching processes can be used. After the pattern is transferred, the patterned photoresist is removed using a resist stripping process, such as ashing. Ashing is performed using a suitable reactive gas, such as O2, N2, H2 / N2, O3, CF4, or any combination thereof.

[0030] Figure 3 The diagram illustrates the next step in forming vertically stacked fins for a semiconductor structure 100, wherein a pad 108 is formed on a substrate 102, a hard mask 104, and vertical nanowires 106. The pad 108 can be a Y-pad material, such as a dielectric material. Suitable dielectric materials include, for example, silicon nitride, silicon oxide, silicon oxynitride, dielectric metal oxide, dielectric metal nitride, or combinations thereof. For example, the pad 108 can be formed by depositing a pad layer using an ALD process. The pad layer 108 can have a thickness ranging from about 1 to about 3 nanometers (nm).

[0031] Figure 4 The diagram illustrates the next step in forming vertically stacked fins for semiconductor structure 100, wherein etched regions are then filled with oxide 110 on pad 108 and over vertical nanowires 106. Suitable oxide materials include, for example, silicon dioxide. In one embodiment, the oxide filler 110 is formed by depositing a uniform-thickness layer of oxide on the vertical nanowires 106 and then planarizing the oxide by, for example, a CMP process.

[0032] Figure 5The diagram illustrates the next step in forming vertically stacked fins for a semiconductor structure 100, wherein photolithography is used to pattern a portion of oxide filler 110 to expose the top portions of alternating vertical nanowires 106 and pads 108. In one embodiment, the oxide filler 110 can be selectively removed using anisotropic etching. For example, in one illustrative embodiment, anisotropic etching can be performed using hydrofluoric acid, for example in the form of gaseous anhydrous HF along with ammonia. In another illustrative embodiment, anisotropic etching can be performed by hydrofluorocarbon plasma etching. For example, plasma etching can be performed using a hydrofluorocarbon plasma gas combined with an inert gas. Typically, the inert gas can be at least 90%. In one illustrative embodiment, the hydrofluorocarbon can be C5HF7, and the inert gas can be argon and oxygen, and a high-density plasma is generated when excited in the plasma etching chamber. In an illustrative embodiment, a radio frequency (RF) power source inductively couples power into the chamber, where the substrate being etched is supported on a pedestal. The pedestal is also biased by the RF power supply at a power higher than the inductively coupled power. Furthermore, the silicon-containing surface may be included in the chamber and maintained at at least 20°C to remove fluorine from the plasma. As a result, etching exhibits high selectivity for the oxide filler 110 (e.g., silicon oxide) on the pad 108 (e.g., silicon nitride) and the photolithographically patterned photoresist (not shown). Due to the high selectivity of plasma etching, the pad 108 remains unetched. Therefore, during this etching, the oxide filler 110 is selectively removed to expose the tops of the alternating vertical nanowires 106. In one embodiment, the oxide filler 110 is removed down to the top surface of the insulating layer 102b of each alternating vertical nanowire 106.

[0033] Figure 6 The diagram illustrates the next step in forming vertically stacked fins for semiconductor structure 100, wherein spacers 112 are deposited on the sidewalls of oxide fillers 110 and pads 108 on alternating vertical nanowires 106. Spacers 112 can be deposited using any conventional technique such as ALD and etched back and forth using an anisotropic dry etching process such as reactive ion etching (RIE). Suitable materials for spacers 112 include, for example, amorphous carbon (aC). If desired, any spacer material on the horizontal portions of structure 100 can be removed, for example, by RIE. Spacers 112 can have a thickness ranging from about 1 nm to about 3 nm.

[0034] Figure 7The following describes the next step in forming the vertically stacked fins for the semiconductor structure 100, wherein the oxide filler 110 between adjacent spacers 112 is further removed to expose the top surface of the pad 108. In one embodiment, the oxide filler 110 can be selectively removed using anisotropic etching. In one exemplary embodiment, this anisotropic etching can be performed by hydrofluorocarbon plasma etching. For example, plasma etching can be performed using a hydrofluorocarbon plasma gas combined with an inert gas. In one illustrative embodiment, the inert gas may be at least about 90% of the plasma etching. In one exemplary embodiment, the hydrofluorocarbon may be C5HF7, and the inert gas may be argon and oxygen, and a high-density plasma is generated when excited in the plasma etching chamber, as described above. As a result, the etching exhibits high selectivity for the oxide filler 110 on the pad 108 and spacers 112. Due to the high selectivity of the plasma etching, the pad 108 and spacers 112 remain unetched. In another illustrative embodiment, anisotropic etching can be performed by means of hydrofluoric acid, for example in the form of gaseous anhydrous HF with ammonia.

[0035] Therefore, during this etching, the oxide filler 110 is selectively removed to expose the top of the alternating vertical nanowires 106 and the top surface of the pad 108 between adjacent spacers 112. Furthermore, the oxide filler 110 remains below the spacers 112. In one embodiment, the oxide filler 110 is removed downwards to the top surface of the insulating layer 102b of each alternating vertical nanowire 106.

[0036] Figure 8The diagram illustrates the next step in forming vertically stacked fins for a semiconductor structure 100, wherein oxide filler 110 beneath each spacer 112 formed on the sidewalls of the pad layer 108 of each alternating vertical nanowire 106 is selectively removed by isotropic etching. In one embodiment, isotropic etching can be used to selectively remove the oxide filler 110. In one exemplary embodiment, this isotropic etching can be performed by hydrofluorocarbon plasma etching. For example, plasma etching can be performed using a hydrofluorocarbon plasma gas combined with an inert gas. Typically, the inert gas can be at least 90%. In an exemplary embodiment, the hydrofluorocarbon can be C5HF7, and the inert gas can be argon and oxygen, and a high-density plasma is generated when excited in the plasma etching chamber, as described above. As a result, the etching exhibits high selectivity for the oxide filler 110 on the pads 108 and spacers 112. Due to the high selectivity of the plasma etching, the pads 108 and spacers 112 remain unetched. In another illustrative embodiment, isotropic etching can be performed using, for example, hydrofluoric acid in the form of gaseous anhydrous HF with ammonia. As described above, the oxide filler 110 is selectively removed by isotropic etching through a wet etchant flow between the spacers 112. During this etching, a portion of the oxide filler 110 on the sidewalls of adjacent vertical nanowires 106 can be removed. Furthermore, a portion of the oxide filler 110 can be isotropically recessed under the spacers 112 of adjacent vertical nanowires 106.

[0037] Figure 9 The diagram illustrates the next step in forming vertically stacked fins for a semiconductor structure 100, wherein a portion of the exposed pads 108 above the oxide filler 110 on alternating vertical nanowires 106 and the exposed pads 108 on the hard mask 104 of each vertical nanowire 106 are selectively removed. In one exemplary embodiment, the exposed pads 108 are selectively removed by isotropic etching. In one exemplary embodiment, the isotropic etching can be performed by fluorocarbon plasma etching. For example, plasma etching can be performed using a fluorocarbon plasma gas combined with an inert gas. Typically, the inert gas can be at least 90%. In one illustrative embodiment, the fluorocarbon can be CF4, and the inert gas can be oxygen and nitrogen, and a high-density plasma is generated when excited in a plasma etching chamber, as described above. In another illustrative embodiment, the fluorocarbon can be CF4, and the inert gas can be argon, and a high-density plasma is generated when excited in a plasma etching chamber, as described above. As a result, the etching exhibits high selectivity for the exposed pads 108 on the oxide filler 110 and spacer 112.

[0038] exist Figure 10The diagram illustrates the next step in forming the vertically stacked fins for the semiconductor structure 100, wherein spacers 112 are removed. Spacers 112 can be removed by any suitable etching process (including, but not limited to, wet etching or dry etching). For example, etching can be performed using RIE or plasma etching processes and N2 / H2 chemicals or N2 / H2 chemicals in an inert gas such as argon.

[0039] Figure 11 The following describes the next step in forming vertically stacked fins for a semiconductor device 100, wherein exposed silicon portions 102a and 102c are subjected to thermal oxidation processes known in the art. The thermal oxidation process is performed to oxidize the exposed portions 102a and 102c of the alternating vertical nanowires 106. This process forms oxides within the exposed portions 102a and 102c of the alternating vertical nanowires 106. As shown, the formed oxide is identical to oxide filler 110.

[0040] Figure 12 The following describes the next step in forming vertically stacked fins for semiconductor structure 100, wherein the exposed portions of structure 100 are then filled with an oxide material. The oxide material may be the same as or different from oxide filler 110. In one illustrative embodiment, the oxide filler is the same as oxide filler 110. In one embodiment, oxide filler 110 is formed by depositing a uniform-thickness layer of oxide in the exposed portions of structure 100 and on vertical nanowires 106, and then planarizing the oxide by, for example, a CMP process. The resulting structure 100 comprises vertically crystalline nanowires 106 that are staggered in spacing between two layers comprising stacked vertical nanowires 106. The resulting structure 100 has staggered crystalline semiconductor channels 102a and 102c that have the same spacing but are moved or translated between the top and bottom layers of the vertical fin array.

[0041] In one embodiment, the fins at the bottom of the stack can form PFET transistors, while the fins at the top of the stack can form NFET transistors. However, the invention is not limited thereto and may include a structure in which the transistors at the bottom of the stack and the transistors at the top of the stack can be PFET and PFET, NFET and NFET, or NFET and PFET, respectively.

[0042] The vertically stacked, staggered semiconductor fins disclosed herein can undergo one or more additional processing steps. For example, the first field-effect transistor may further include source / drain regions and a gate structure including a gate dielectric layer and a metal gate layer. The second field-effect transistor stacked on the first field-effect transistor may further include source / drain regions and a gate structure including a gate dielectric layer and a metal gate layer. Furthermore, one or more conductive vias may communicate with the gate structure of the first FET device or the gate structure of the second FET device.

[0043] For example, the source / drain region can be formed by growing an epitaxial semiconductor material on the exposed top surface of the nanowire 106 of the first field-effect transistor. An epitaxial growth process is performed to deposit a crystalline layer onto the underlying crystalline substrate. The underlying substrate acts as a seed. The epitaxial layer can be grown from a gaseous or liquid precursor. The epitaxial silicon material can be grown using vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable processes. The type of epitaxial material and dopant used to form the source region 112 will vary depending on whether the FET device is a P-type or N-type device. Examples of semiconductor materials suitable for the epitaxial growth of the source / drain region include (but are not limited to) silicon (single crystal, polycrystalline, or amorphous), germanium (single crystal, polycrystalline, or amorphous), or combinations thereof.

[0044] After the semiconductor material is grown, it is atomically doped with dopant using methods such as in-situ doping, ion implantation, or external delay. In this illustrative embodiment, the semiconductor material is doped with a p-type dopant, such as boron, aluminum, gallium, indium, or alloys thereof, to form the PFET source region. In other embodiments described below, the semiconductor material may be doped with an n-type dopant, such as phosphorus, antimony, arsenic, or alloys thereof. After the doping process, the semiconductor material may have a dopant ranging from about 1 × 10⁻⁶. 19 atoms / cm 3 Approximately 5×10 21 atoms / cm 3 The dopant concentration.

[0045] It should be understood that the methods for manufacturing semiconductor structures discussed herein can be incorporated into semiconductor processing flows for manufacturing other types of semiconductor devices and integrated circuits having various analog and digital circuits or mixed-signal circuits. In particular, integrated circuit dies can be manufactured using various devices, such as transistors, diodes, capacitors, inductors, etc. Integrated circuits according to embodiments can be used in applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing embodiments of the invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., cellular phones), solid-state storage devices, functional circuits, etc. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein.

[0046] Furthermore, the various layers, regions, and / or structures described above can be implemented in an integrated circuit (chip). Manufacturers can distribute the resulting integrated circuit chips in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare chips, or in packages. In the latter case, the chip is mounted in a single-chip package (e.g., a plastic carrier with leads that are attached to a motherboard or other more advanced carrier) or a multi-chip package (e.g., a ceramic carrier with one or both surface-mount or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product that includes the integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0047] Although illustrative embodiments have been described herein with reference to the accompanying drawings, it should be understood that the invention is not limited to these precise embodiments, and that various other changes and modifications can be made by those skilled in the art without departing from the scope of the invention.

[0048] In a preferred embodiment of the present invention described above, a method is provided comprising: forming a plurality of layered silicon-insulator-silicon vertical nanowires from a surface of a substrate; wherein the plurality of nanowires have a hard mask on their top surfaces; forming a pad on the outer surfaces of the alternately layered silicon-insulator-silicon vertical nanowires, wherein the pad is formed on a portion of an insulating layer extending to the hard mask and exposing a bottom silicon layer of the layered silicon-insulator-silicon vertical nanowires; forming a first oxide layer on the outer surface of another alternately layered silicon-insulator-silicon vertical nanowire, wherein the first oxide layer is formed on a portion of the insulating layer extending to the top surface of the substrate and exposing a top silicon layer of the layered silicon-insulator-silicon vertical nanowires; and thermally oxidized exposed bottom and top silicon layers of the silicon-insulator-silicon nanowire layers. Preferably, the method further comprises depositing a second oxide layer on the outer surfaces of the substrate and the first oxide layer and on the pad.

Claims

1. A semiconductor structure, comprising: a substrate comprising a semiconductor material; a first semiconductor channel comprising a plurality of vertical nanowires, wherein each vertical nanowire of the first semiconductor channel comprises a first semiconductor layer derived from the semiconductor material, a first insulating layer disposed on the first semiconductor layer, and a first oxide layer disposed on the first insulating layer; and a second semiconductor channel comprising a plurality of vertical nanowires, wherein each vertical nanowire of the second semiconductor channel comprises a second oxide layer disposed on the substrate, a second insulating layer disposed on the second oxide layer, and a second semiconductor layer derived from the semiconductor material and disposed on the second insulating layer; wherein the first semiconductor channel and the second semiconductor channel are configured in a stacked configuration; and wherein each of the plurality of vertical nanowires of the first semiconductor channel is configured in an alternating position relative to each of the plurality of vertical nanowires of the second semiconductor channel.

2. The semiconductor structure of claim 1, wherein the substrate is a bulk substrate.

3. The semiconductor structure of claim 2, wherein the bulk substrate comprises silicon.

4. The semiconductor structure of claim 1, wherein the semiconductor material comprises silicon.

5. The semiconductor structure of claim 1, wherein the plurality of vertical nanowires of the first semiconductor channel and the plurality of vertical nanowires of the second semiconductor channel are disposed in a third oxide layer.

6. The semiconductor structure of claim 1, wherein the first semiconductor channel comprises a first vertical field effect transistor, the second semiconductor channel comprises a second vertical field effect transistor, the second vertical field effect transistor is configured to be stacked on the first vertical field effect transistor.

7. The semiconductor structure of claim 1, wherein, the first semiconductor channel is an n-channel, and the second semiconductor channel is a p-channel.

8. The semiconductor structure of claim 1, wherein, the first semiconductor channel is a p-channel, and the second semiconductor channel is an n-channel.

9. The semiconductor structure of claim 1, further comprising a first liner disposed on the substrate, the first semiconductor layer, and a portion of the first insulating layer of the plurality of vertical nanowires of the first semiconductor channel, and a second liner disposed on the second semiconductor layer, and a portion of the second insulating layer of the plurality of vertical nanowires of the second semiconductor channel.

10. A logic device comprising at least one semiconductor structure as claimed in any one of claims 1-9.

11. An integrated circuit comprising a logic device as claimed in claim 10.

12. A method of forming a semiconductor structure, comprising: forming a first semiconductor channel comprising a plurality of vertical nanowires and a second semiconductor channel comprising a plurality of vertical nanowires on a semiconductor substrate comprising a semiconductor material, wherein each vertical nanowire of the first semiconductor channel comprises a first semiconductor layer derived from the semiconductor material, a first insulating layer disposed on the first semiconductor layer, and a first oxide layer disposed on the first insulating layer, each vertical nanowire of the second semiconductor channel comprises a second oxide layer disposed on the substrate, a second insulating layer disposed on the second oxide layer, and a second semiconductor layer derived from the semiconductor material and disposed on the second insulating layer; wherein the first semiconductor channel and the second semiconductor channel are formed in a stacked configuration; and wherein each of the plurality of vertical nanowires of the first semiconductor channel is formed in an alternating position relative to each of the plurality of vertical nanowires of the second semiconductor channel.

13. The method of claim 12, wherein the semiconductor substrate comprises a layered silicon-insulator-silicon substrate.

Images