ESD event detection method, device, electronic device and storage medium

Abstract

Embodiments of the present invention relate to the field of digital circuit technology, and in particular to a method, device, electronic device and storage medium for detecting ESD events. The method includes: determining a target configuration register contained in a target chip; the target configuration register is a readable and writable register; calculating an initial check value corresponding to the target configuration register, and using the initial check value as the target check value in the next clock cycle; in each clock cycle, performing: obtaining the target check value in the current clock cycle, and determining whether the target chip generates a valid write enable signal in the current clock cycle; determining whether an ESD event is detected based on the result of the write enable signal and the target check value in the current clock cycle. The technical solution provided by the present invention can expand the scope of the ESD event detection register and improve the detection accuracy of ESD events.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of digital circuit technology, and in particular to an ESD event detection method, device, electronic device and storage medium. Background Art

[0002] ESD (Electrostatic Discharge) refers to the situation in which static electricity generated by clothing friction, electromagnetic induction, etc. in daily life inadvertently forms a discharge path, causing instantaneous high voltage (> several thousand volts) discharge. When the chip is working, encountering an ESD event of high voltage instantaneous discharge may cause abnormal flipping of the chip's internal registers, resulting in chip operation errors.

[0003] At present, the existing method for detecting ESD events is to calculate the check value of the configuration register in the chip at regular intervals and compare it with the fixed check value stored before. If the two are different, it is considered that the ESD event caused the abnormal flipping of the register in the chip. However, the configuration registers include at least two categories. The first category of configuration registers are those that will never change after the startup configuration, and the second category of configuration registers are readable and writable registers. The above-mentioned method of detecting ESD events using fixed check value comparison can only be used for detection of the first category of configuration registers, and the second category of configuration registers cannot be detected using fixed check values. Therefore, the detection accuracy of the existing ESD event detection method is low.

[0004] Therefore, a new method for detecting ESD events is urgently needed. Summary of the invention

[0005] In order to solve the problem that the existing ESD event detection method only detects the first type of configuration registers, resulting in low detection accuracy, the embodiments of the present invention provide an ESD event detection method, device, electronic device and storage medium.

[0006] In a first aspect, an embodiment of the present invention provides a method for detecting an ESD event, comprising:

[0007] Determine a target configuration register included in the target chip; the target configuration register is a readable and writable register;

[0008] Calculating an initial check value corresponding to the target configuration register, and using the initial check value as a target check value in a next clock cycle;

[0009] In each clock cycle, the following are executed:

[0010] Obtaining a target check value in a current clock cycle, and determining whether the target chip generates a valid write enable signal in the current clock cycle;

[0011] Whether an ESD event is detected is determined according to the generation result of the write enable signal and the target check value in the current clock cycle.

[0012] In one possible design, calculating the initial check value corresponding to the target configuration register includes:

[0013] Determining the number of clock cycles required to calculate the initial check value according to the number of the target configuration registers;

[0014] grouping the target configuration registers according to the determined number of clock cycles;

[0015] An initial check value of the target configuration register is determined according to the grouping result and the number of clock cycles.

[0016] In a possible design, the number of clock cycles is one, and the grouping result is that all the target configuration registers are grouped into one group;

[0017] Determining the initial check value of the target configuration register according to the grouping result and the number of clock cycles includes: performing a check operation on the target configuration register in the group within the one clock cycle to obtain the initial check value.

[0018] In a possible design, the number of clock cycles is multiple, and the grouping result is that all the target configuration registers are divided into multiple groups;

[0019] Determining the initial check value of the target configuration register according to the grouping result and the number of clock cycles includes:

[0020] S1. In the current clock cycle, for each group, the following operations are performed: a verification operation is performed on the target configuration register in the group to obtain an intermediate verification value of the group;

[0021] S2. Determine whether the number of obtained intermediate check values ​​is one;

[0022] If yes, the intermediate check value is determined as the initial check value, and the process ends;

[0023] If not, the obtained multiple intermediate check values ​​are stored one by one in multiple intermediate registers, and it is determined whether the next clock cycle is the last clock cycle. If so, the multiple intermediate registers are grouped into one group; if not, the multiple intermediate registers are grouped into multiple groups; and after grouping, the next clock cycle is entered to execute S1.

[0024] In a possible design, determining whether an ESD event is detected according to a generation result of a write enable signal and a target check value in a current clock cycle includes:

[0025] If the result of generating the write enable signal is that a valid write enable signal is generated in the current clock cycle, it is determined that no ESD event is detected;

[0026] If the result of generating the write enable signal is that no valid write enable signal is generated in the current clock cycle, the check value of the target configuration register in the current clock cycle is calculated, and it is determined whether the check value is the same as the target check value in the current clock cycle. If they are the same, it is determined that no ESD event is detected; if they are not the same, it is determined that an ESD event is detected.

[0027] In a possible design, after determining that the generation result of the write enable signal is that a valid write enable signal is generated in the current clock cycle, the method further includes:

[0028] The check value of the target configuration register in the current clock cycle after the write enable signal generated by the calculation changes the configuration value of the target configuration register;

[0029] The check value replaces the target check value in the current clock cycle to serve as the target check value in the next clock cycle.

[0030] In one possible design, the check operation is an XOR operation.

[0031] In a second aspect, an embodiment of the present invention further provides a detection device for an ESD event, comprising:

[0032] A determination unit, used to determine a target configuration register included in a target chip; the target configuration register is a readable and writable register;

[0033] A calculation unit, used to calculate an initial check value corresponding to the target configuration register, and use the initial check value as a target check value in a next clock cycle;

[0034] The detection unit is used to perform the following in each clock cycle:

[0035] Obtaining a target check value in a current clock cycle, and determining whether the target chip generates a valid write enable signal in the current clock cycle;

[0036] Whether an ESD event is detected is determined according to the generation result of the write enable signal and the target check value in the current clock cycle.

[0037] In a third aspect, an embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the method described in any embodiment of this specification is implemented.

[0038] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon, which, when executed in a computer, enables the computer to execute the method described in any embodiment of this specification.

[0039] The embodiment of the present invention provides a detection method, device, electronic device and storage medium for ESD events. First, all readable and writable registers in the target chip are determined as target configuration registers, and a single initial check value is calculated using all target configuration registers, and the initial check value is used as the target check value in the next clock cycle. In each of the following clock cycles, it is necessary to determine whether the target chip generates a valid write enable signal in the current clock cycle, and determine whether an ESD event is detected based on the generation result of the write enable signal and the target check value in the current clock cycle. In this way, ESD event detection of readable and writable registers is completed, thereby expanding the range of ESD event detection registers and improving the detection accuracy of ESD events. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 is a flow chart of a method for detecting an ESD event provided by an embodiment of the present invention;

[0042] Figure 2 is a hardware architecture diagram of an electronic device provided by an embodiment of the present invention;

[0043] Figure 3 It is a structural diagram of an ESD event detection device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0045] As mentioned above, the existing ESD event detection method is to detect ESD events by comparing fixed check values, which can only be used for the first type of configuration registers. This is because the internal configuration value of the first type of configuration register will never change after the configuration is started. Therefore, as long as the fixed check value is used for comparison, it can be known whether the first type of configuration register has an abnormal flip. However, during the operation of the chip, the readable and writable configuration register will change the configuration value through a valid wr_en write enable signal. This is a normal operation flip of the readable and writable configuration register. If a fixed check value is used for comparison, the normal operation flip of the readable and writable configuration register will also be detected as an ESD event. Therefore, the existing ESD event detection method cannot detect the readable and writable configuration register, so the detection accuracy of the existing ESD event detection method is low.

[0046] In order to solve the above technical problems, the inventor may consider first determining the readable and writable configuration register contained in the target chip as the target configuration register, and using the initial check value corresponding to the target configuration register as the target check value in the next clock cycle, so that in each subsequent clock cycle, the target check value in the current clock cycle will be obtained instead of the fixed target check value, and whether the ESD event is detected is determined based on the judgment result of whether the target chip generates a valid write enable signal in the current clock cycle and the target check value in the current clock cycle. This scheme can determine whether the flip of the readable and writable register is due to the ESD event or the normal operation of the chip by judging whether a valid write enable signal is generated and the target check value in the current clock cycle, so as to detect ESD events on the readable and writable register, thereby expanding the range of the ESD event detection register to increase the probability of detecting ESD events.

[0047] The specific implementation of the above concept is described below.

[0048] Please refer to Figure 1 , an embodiment of the present invention provides a method for detecting an ESD event, the method comprising:

[0049] Step 100: Determine a target configuration register contained in a target chip; the target configuration register is a readable and writable register;

[0050] Step 102: Calculate an initial check value corresponding to the target configuration register, and use the initial check value as a target check value in the next clock cycle;

[0051] Step 104: In each clock cycle, the following are performed: obtaining the target check value in the current clock cycle, and determining whether the target chip generates a valid write enable signal in the current clock cycle; and determining whether an ESD event is detected based on the generation result of the write enable signal and the target check value in the current clock cycle.

[0052] In the embodiment of the present invention, firstly, all the readable and writable configuration registers in the target chip are determined as the target configuration registers, and a single initial check value is calculated using all the target configuration registers, and the initial check value is used as the target check value in the next clock cycle. In each of the following clock cycles, it is necessary to determine whether the target chip generates a valid write enable signal in the current clock cycle, and determine whether an ESD event is detected based on the generation result of the write enable signal and the target check value in the current clock cycle. In this way, the ESD event detection of the readable and writable registers is completed, so that the range of the ESD event detection register can be expanded and the detection accuracy of the ESD event can be improved.

[0053] Described below Figure 1 How the various steps are performed.

[0054] For step 100:

[0055] The common configuration registers in the chip can be roughly divided into three types according to the reading and writing methods: readable and writable configuration registers, configuration registers that are automatically cleared when writing 1, and read-only registers.

[0056] In this embodiment, all readable and writable configuration registers contained in the target chip are used as target configuration registers. The readable and writable configuration registers account for the majority of the common configuration registers, and their contents may be rewritten many times during the operation of the chip, but the contents of the readable and writable configuration registers change regularly, and they will only be rewritten when the special wr_en write enable signal is valid, and the contents of these configuration registers will not be changed at other times.

[0057] Regarding step 102:

[0058] In this embodiment, an initial check value needs to be calculated according to the configuration values ​​of all target configuration registers, and the initial check value is stored in a register specifically for storing target check values ​​as the target check value in the next clock cycle.

[0059] Next, the method of calculating the initial check value is described.

[0060] In some implementations, calculating an initial check value corresponding to a target configuration register includes:

[0061] Determining the number of clock cycles required to calculate the initial check value based on the number of target configuration registers;

[0062] grouping target configuration registers according to a determined number of clock cycles;

[0063] An initial check value of a target configuration register is determined based on the grouping result and the number of clock cycles.

[0064] It should be noted that in order to reduce the complexity of the verification operation and avoid reducing the overall clock rate of the chip due to the complexity of the operation performed by one clock, the number of clock cycles required to calculate the initial verification value can be determined in advance based on the number of target configuration registers. Then, the target configuration registers can be grouped according to the determined number of clock cycles, and then the initial verification value of the target configuration register can be determined based on the grouping result and the number of clock cycles.

[0065] For example, when the number of target configuration registers is determined to be 512, the number of clock cycles required to calculate the initial check value can be determined to be 3 clock cycles. Then, in the first clock cycle, the 512 target configuration registers are divided into 64 groups, each with 8 target configuration registers. In the second clock cycle, the 64 groups of intermediate registers in the first clock cycle are divided into 8 groups. In the third clock cycle, the 8 groups of intermediate registers in the second clock cycle are divided into 1 group, so that the initial check value is calculated within 3 clock cycles.

[0066] Of course, the number of clock cycles required to calculate the initial check value may be one or more, so it is not specifically limited here.

[0067] In some implementations, the number of clock cycles is one, and the grouping result is that all target configuration registers are grouped into one group;

[0068] Determining an initial check value of a target configuration register according to the grouping result and the number of clock cycles includes: performing a check operation on the target configuration register in the group within the one clock cycle to obtain an initial check value.

[0069] In this embodiment, when the number of clock cycles required to calculate the initial check value is 1, within this clock cycle, a check operation is performed on all target configuration registers to calculate and obtain the initial check value.

[0070] It should be noted that in the embodiment of the present invention, the check operation is an XOR operation, and the check value is calculated using the XOR operation. Of course, other check methods can also be used, such as accumulation operation, CRC operation, etc., so no specific limitation is made here.

[0071] In some implementations, if the number of clock cycles is multiple, the grouping result is that all target configuration registers are divided into multiple groups;

[0072] According to the grouping result and the number of clock cycles, determine the initial check value of the target configuration register, including:

[0073] S1. In the current clock cycle, for each group, the following operations are performed: a verification operation is performed on the target configuration register in the group to obtain an intermediate verification value of the group;

[0074] S2. Determine whether the number of obtained intermediate check values ​​is one;

[0075] If yes, the intermediate check value is determined as the initial check value, and the process ends;

[0076] If not, the obtained multiple intermediate check values ​​are stored one by one in multiple intermediate registers, and it is determined whether the next clock cycle is the last clock cycle. If so, the multiple intermediate registers are grouped into one group; if not, the multiple intermediate registers are grouped into multiple groups; and after grouping, the next clock cycle is entered to execute S1.

[0077] For example, to calculate the initial check values ​​corresponding to 512 target configuration registers, the number of required clock cycles is determined to be 3. In the first clock cycle, the 512 target configuration registers are divided into 64 groups, each with 8 target configuration registers, and the target configuration registers in each group are XORed. Then, each group can calculate 1 intermediate check value, that is, the XOR check value, so a total of 64 intermediate check values ​​are calculated in the first clock cycle; then the 64 intermediate check values ​​are stored in 64 intermediate registers respectively. Because the next clock cycle is not the last clock cycle, the 64 intermediate check values ​​are stored in the 64 intermediate registers. The intermediate registers are divided into 8 groups. In the second clock cycle, an XOR operation is performed on the intermediate check values ​​in each group, so a total of 8 intermediate check values ​​are calculated in the second clock cycle; finally, the 8 intermediate check values ​​are stored in 8 new intermediate registers respectively. Because the next clock cycle is the last clock cycle, the 8 intermediate registers are divided into 1 group. In the third clock cycle, an XOR operation is performed on the intermediate check values ​​in the group, so 1 intermediate check value can be calculated in the third clock cycle. Since the number of intermediate check values ​​is one, the intermediate check value is determined as the initial check value.

[0078] In this embodiment, the calculation of the initial verification value is performed using multiple clock cycles, which can reduce the complexity of the verification operation and avoid reducing the overall clock rate of the chip due to the complexity of the operation performed by one clock.

[0079] Regarding step 104:

[0080] In some implementations, determining whether an ESD event is detected according to a generation result of a write enable signal and a target check value in a current clock cycle may include:

[0081] If the result of generating the write enable signal is that a valid write enable signal is generated in the current clock cycle, it is determined that no ESD event is detected;

[0082] If the result of generating the write enable signal is that no valid write enable signal is generated in the current clock cycle, the check value of the target configuration register in the current clock cycle is calculated, and it is determined whether the check value is the same as the target check value in the current clock cycle. If they are the same, it is determined that no ESD event is detected; if they are not the same, it is determined that an ESD event is detected.

[0083] For example, after the initial check value is obtained, it is stored in a register dedicated to storing the target check value, that is, the initial check value is used as the target check value. Then, in the next clock cycle after the initial check value is obtained, if a valid wr_en write enable signal is generated, the detection result in the clock cycle is output as 0, that is, no ESD event is detected; if no valid wr_en write enable signal is generated, the check value of the target configuration register in the current clock cycle is calculated, and it is determined whether the check value is the same as the target check value (that is, the initial check value) in the current clock cycle. If they are the same, the output detection result is 0, that is, no ESD event is detected. If they are different, the output detection result is 1, and it is considered that all target configuration registers have caused abnormal flipping due to ESD time, and it is considered that an ESD event is detected.

[0084] In addition, after determining that the generation result of the write enable signal is that a valid write enable signal is generated in the current clock cycle, the method further includes:

[0085] The check value of the target configuration register in the current clock cycle after the write enable signal generated by the calculation changes the configuration value of the target configuration register;

[0086] The check value replaces the target check value in the current clock cycle to serve as the target check value in the next clock cycle.

[0087] Continuing with the example of the next clock cycle after the initial check value is obtained, when a valid wr_en write enable signal is generated in this clock cycle, while the detection result in this clock cycle is output as 0, the check value of the target configuration register in the current clock cycle is calculated after the valid wr_en write enable signal changes the configuration value of the target configuration register, and the check value replaces the initial check value in the register specifically storing the target check value as the new target check value.

[0088] Although the readable and writable configuration register in the ordinary configuration register can be rewritten when the wr_en write enable signal is valid, the configuration attribute of the configuration register determines that it will only be rewritten occasionally, not frequently. Although the embodiment of the present invention performs a verification operation in each beat, because the configuration value of the configuration register is unchanged most of the time, the verification value will not change, and it will not cause the configuration register and the gate circuit to flip, and will not increase power consumption a lot. Although the change of the configuration register caused by the wr_en write enable signal and the ESD event will cause the change of the verification value and the flipping of the verification register, because the configuration register is not often rewritten and the ESD event does not occur frequently, the detection method in the embodiment of the present invention will not increase the power consumption of the chip too much.

[0089] Therefore, the embodiment of the present invention proposes a method for detecting ESD events by monitoring abnormal flipping of readable and writable configuration registers in common configuration registers, with respect to the flipping rule of readable and writable configuration registers. Compared with the previous inability to detect abnormal flipping of ESD events of readable and writable configuration registers, this solution expands the scope of ESD event detection registers and increases the probability of discovering ESD events. At the same time, during the implementation process, this solution also takes into account the reaction speed of the ESD event detection circuit and the power consumption of the detection circuit, striving to increase the reaction speed without increasing the power consumption of the chip too much.

[0090] like Figure 2 , Figure 3 As shown, an embodiment of the present invention provides a detection device for ESD events. The device embodiment can be implemented by software, or by hardware or a combination of software and hardware. From the hardware level, Figure 2 As shown, it is a hardware architecture diagram of an electronic device in which an ESD event detection device provided by an embodiment of the present invention is located. Figure 2 In addition to the processor, memory, network interface, and non-volatile memory shown, the electronic device in the embodiment may also include other hardware, such as a forwarding chip responsible for processing messages, etc. Taking software implementation as an example, Figure 3 As shown, as a device in a logical sense, the CPU of the electronic device in which it is located reads the corresponding computer program in the non-volatile memory into the internal memory and runs it.

[0091] like Figure 3 As shown, this embodiment provides an ESD event detection device, including:

[0092] A determination unit 301 is used to determine a target configuration register included in a target chip; the target configuration register is a readable and writable configuration register;

[0093] A calculation unit 302 is used to calculate an initial check value corresponding to the target configuration register, and use the initial check value as a target check value in a next clock cycle;

[0094] The detection unit 303 is used to perform the following in each clock cycle: obtaining a target check value in the current clock cycle, and determining whether the target chip generates a valid write enable signal in the current clock cycle; and determining whether an ESD event is detected based on the generation result of the write enable signal and the target check value in the current clock cycle.

[0095] In one embodiment of the present invention, when the calculation unit 302 executes calculation of the initial check value corresponding to the target configuration register, it is used to: determine the number of clock cycles required to calculate the initial check value according to the number of the target configuration registers; group the target configuration registers according to the determined number of clock cycles; and determine the initial check value of the target configuration register according to the grouping result and the number of clock cycles.

[0096] In one embodiment of the present invention, in the calculation unit 302, the number of clock cycles is one, and the grouping result is that all the target configuration registers are grouped into one group;

[0097] When the initial check value of the target configuration register is determined according to the grouping result and the number of clock cycles, it is used to perform a check operation on the target configuration register in the group within the one clock cycle to obtain the initial check value.

[0098] In one embodiment of the present invention, in the calculation unit 302, the number of clock cycles is multiple, and the grouping result is that all the target configuration registers are divided into multiple groups;

[0099] When determining the initial check value of the target configuration register according to the grouping result and the number of clock cycles, the method is used to perform the following operations:

[0100] S1. In the current clock cycle, for each group, the following operations are performed: a verification operation is performed on the target configuration register in the group to obtain an intermediate verification value of the group;

[0101] S2. Determine whether the number of obtained intermediate check values ​​is one;

[0102] If yes, the intermediate check value is determined as the initial check value, and the process ends;

[0103] If not, the obtained multiple intermediate check values ​​are stored one by one in multiple intermediate registers, and it is determined whether the next clock cycle is the last clock cycle. If so, the multiple intermediate registers are grouped into one group; if not, the multiple intermediate registers are grouped into multiple groups; and after grouping, the next clock cycle is entered to execute S1.

[0104] In one embodiment of the present invention, when the detection unit 303 determines whether an ESD event is detected according to the generation result of the write enable signal and the target check value in the current clock cycle, it is used to perform the following operations:

[0105] If the result of generating the write enable signal is that a valid write enable signal is generated in the current clock cycle, it is determined that no ESD event is detected;

[0106] If the result of generating the write enable signal is that no valid write enable signal is generated in the current clock cycle, the check value of the target configuration register in the current clock cycle is calculated, and it is determined whether the check value is the same as the target check value in the current clock cycle. If they are the same, it is determined that no ESD event is detected; if they are not the same, it is determined that an ESD event is detected.

[0107] In one embodiment of the present invention, after determining that the generation result of the write enable signal is that a valid write enable signal is generated in the current clock cycle, the detection unit 303 is configured to perform the following operations:

[0108] The check value of the target configuration register in the current clock cycle after the write enable signal generated by the calculation changes the configuration value of the target configuration register;

[0109] The check value replaces the target check value in the current clock cycle to serve as the target check value in the next clock cycle.

[0110] In one embodiment of the present invention, in the calculation unit 302, the check operation is an exclusive-OR operation.

[0111] It is to be understood that the structure illustrated in the embodiment of the present invention does not constitute a specific limitation on a detection device for an ESD event. In other embodiments of the present invention, a detection device for an ESD event may include more or fewer components than shown in the figure, or combine certain components, or split certain components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0112] The information interaction, execution process and other contents between the modules in the above-mentioned device are based on the same concept as the embodiment of the method of the present invention. For the specific contents, please refer to the description in the embodiment of the method of the present invention, and no further description is given here.

[0113] An embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, an ESD event detection method in any embodiment of the present invention is implemented.

[0114] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the processor executes an ESD event detection method in any embodiment of the present invention.

[0115] Specifically, a system or device equipped with a storage medium can be provided, on which software program code that implements the functions of any of the above-mentioned embodiments is stored, and a computer (or CPU or MPU) of the system or device can be enabled to read and execute the program code stored in the storage medium.

[0116] In this case, the program code itself read from the storage medium can realize the function of any one of the above-mentioned embodiments, and thus the program code and the storage medium storing the program code constitute a part of the present invention.

[0117] The storage medium embodiments for providing the program code include a floppy disk, a hard disk, a magneto-optical disk, an optical disk (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), a magnetic tape, a non-volatile memory card, and a ROM. Alternatively, the program code can be downloaded from a server computer by a communication network.

[0118] In addition, it should be clear that the functions of any of the above embodiments can be implemented not only by executing the program code read by the computer, but also by enabling an operating system operating on the computer to complete part or all of the actual operations based on instructions from the program code.

[0119] In addition, it can be understood that the program code read from the storage medium is written to a memory provided in an expansion board inserted into the computer or to a memory provided in an expansion module connected to the computer, and then based on the instructions of the program code, a CPU installed on the expansion board or expansion module is enabled to perform part or all of the actual operations, thereby realizing the functions of any of the above-mentioned embodiments.

[0120] It should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical factors in the process, method, article or device including the elements.

[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for detecting an ESD event, characterized in that: include: Determine a target configuration register included in the target chip; the target configuration register is a readable and writable register; Calculating an initial check value corresponding to the target configuration register, and using the initial check value as a target check value in a next clock cycle; In each clock cycle, the following are executed: Obtaining a target check value in a current clock cycle, and determining whether the target chip generates a valid write enable signal in the current clock cycle; Determine whether an ESD event is detected according to the generation result of the write enable signal and the target check value in the current clock cycle; The calculating the initial check value corresponding to the target configuration register includes: Determining the number of clock cycles required to calculate the initial check value according to the number of the target configuration registers; grouping the target configuration registers according to the determined number of clock cycles; An initial check value of the target configuration register is determined according to the grouping result and the number of clock cycles.

2. The method according to claim 1, characterized in that If the number of clock cycles is one, the grouping result is that all the target configuration registers are grouped into one group; Determining the initial check value of the target configuration register according to the grouping result and the number of clock cycles includes: performing a check operation on the target configuration register in the group within the one clock cycle to obtain the initial check value.

3. The method according to claim 1, characterized in that If the number of the clock cycles is multiple, the grouping result is that all the target configuration registers are divided into multiple groups; Determining the initial check value of the target configuration register according to the grouping result and the number of clock cycles includes: S1. In the current clock cycle, for each group, the following operations are performed: a verification operation is performed on the target configuration register in the group to obtain an intermediate verification value of the group; S2. Determine whether the number of obtained intermediate check values ​​is one; If yes, the intermediate check value is determined as the initial check value, and the process ends; If not, the obtained multiple intermediate check values ​​are stored one by one in multiple intermediate registers, and it is determined whether the next clock cycle is the last clock cycle. If so, the multiple intermediate registers are grouped into one group; if not, the multiple intermediate registers are grouped into multiple groups; and after grouping, the next clock cycle is entered to execute S1.

4. The method according to claim 1, characterized in that The step of determining whether an ESD event is detected according to a generation result of a write enable signal and a target check value in a current clock cycle includes: If the result of generating the write enable signal is that a valid write enable signal is generated in the current clock cycle, it is determined that no ESD event is detected; If the result of generating the write enable signal is that no valid write enable signal is generated in the current clock cycle, the check value of the target configuration register in the current clock cycle is calculated, and it is determined whether the check value is the same as the target check value in the current clock cycle. If they are the same, it is determined that no ESD event is detected; if they are not the same, it is determined that an ESD event is detected.

5. The method according to claim 4, characterized in that After determining that the generation result of the write enable signal is that a valid write enable signal is generated in the current clock cycle, the method further includes: The check value of the target configuration register in the current clock cycle after the write enable signal generated by the calculation changes the configuration value of the target configuration register; The check value replaces the target check value in the current clock cycle to serve as the target check value in the next clock cycle.

6. The method according to claim 2 or 3, characterized in that: The verification operation is an exclusive OR operation.

7. A detection device for ESD events, characterized in that: include: A determination unit, used for determining a target configuration register included in a target chip; The target configuration register is a readable and writable register; A calculation unit, used to calculate an initial check value corresponding to the target configuration register, and use the initial check value as a target check value in a next clock cycle; The detection unit is used to perform the following in each clock cycle: Obtaining a target check value in a current clock cycle, and determining whether the target chip generates a valid write enable signal in the current clock cycle; Determine whether an ESD event is detected according to the generation result of the write enable signal and the target check value in the current clock cycle; When the calculation unit executes calculation of the initial check value corresponding to the target configuration register, it is used to: determine the number of clock cycles required to calculate the initial check value according to the number of the target configuration registers; group the target configuration registers according to the determined number of clock cycles; and determine the initial check value of the target configuration register according to the grouping result and the number of clock cycles.

8. An electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the method according to any one of claims 1 to 6 is implemented.

9. A computer-readable storage medium having a computer program stored thereon, which, when executed in a computer, causes the computer to execute the method according to any one of claims 1 to 6.

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