Chip heat dissipation structure and its fabrication method

Abstract

This invention relates to a chip heat dissipation structure and its fabrication method. The fabrication method includes: thinning a cooling chip to make the cold side of the cooling chip adhere to the chip; forming a mounting groove through a substrate; wherein the substrate is disposed on a heat sink; mounting the cooling chip in the mounting groove to make the hot side adhere to the heat sink; wherein the cold side of the cooling chip is flush with the surface of the substrate facing away from the heat sink; and encapsulating the chip and the cooling chip. Thinning the cooling chip allows the cold side to directly adhere to the chip, improving cooling efficiency. It also reduces the thickness of the cooling chip, allowing it to be flush with the substrate surface after mounting in the groove, thus reducing the overall volume of the chip heat dissipation structure and increasing the integration of the chip heat dissipation structure and related devices. Simultaneously, the adherence of the hot side of the cooling chip to the heat sink further improves the heat dissipation effect and efficiency of the chip heat dissipation structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to chip heat dissipation structures and their fabrication methods. Background Technology

[0002] Currently, semiconductor cooling chips have a wide range of applications, including medicine, military, optics, and cosmetics, to effectively cool and dissipate heat in electronic products, ensuring that the product's operating temperature remains constant. The current methods of using cooling chips primarily involve fixing them to the heat-generating element using screws, resin adhesive, welding, or by using pads or other materials. The cold side of the cooling chip is in close contact with the heat-generating side of the element, allowing heat to be conducted and balanced. Simultaneously, a heat sink is installed on the hot side to conduct heat to the outside. However, the cooling chips currently used are relatively large. The cooling chip attached to the device surface increases the device's thickness to some extent, and the ceramic-encapsulated cooling chip's cold side cannot directly contact the chip's hot spot, reducing cooling efficiency. Summary of the Invention

[0003] Therefore, it is necessary to provide a chip heat dissipation structure and its fabrication method that can improve the chip heat dissipation efficiency in order to address the above problems.

[0004] A method for fabricating a chip heat dissipation structure includes:

[0005] The cooling chip is thinned to allow the cold side of the cooling chip to adhere to the chip; wherein, the two opposite sides of the cooling chip are the cold side and the hot side, respectively.

[0006] A mounting groove is formed through the substrate; wherein the substrate is mounted on a heat sink.

[0007] The cooling chip is installed in the mounting slot so that the hot surface and the heat sink are in contact; wherein the cold surface of the cooling chip is flush with the surface of the substrate facing away from the heat sink.

[0008] The chip and the cooling chip are packaged.

[0009] In one embodiment, the thinning process of the cooling chip includes:

[0010] The refrigeration chip is unsealed and the ceramic layer of the refrigeration chip is removed; the initial state of the refrigeration chip is a sealed state, and the refrigeration chip has a ceramic layer, which is disposed on the cold surface.

[0011] In one embodiment, installing the cooling chip in the mounting slot includes:

[0012] The electrode leads of the cooling chip and the electrode leads of the chip are both connected to the substrate.

[0013] In one embodiment, installing the cooling chip in the mounting slot further includes:

[0014] The cooling element is integrally formed on the substrate and located in the mounting groove.

[0015] In one embodiment, the cooling chip is thinned, and prior to this, the following steps are also included:

[0016] A first substrate is provided, and a conductive structure is provided on the first substrate;

[0017] A semiconductor component is disposed on the conductive structure, and the conductive structure is etched.

[0018] A second substrate is deposited on the semiconductor component to form the cooling chip.

[0019] In one embodiment, a conductive structure is formed on a first substrate, a semiconductor component is formed on the conductive structure, the conductive structure is etched, and a second substrate is deposited on the semiconductor component to form the cooling chip, comprising:

[0020] The conductive structure includes a first conductive layer and a second conductive layer, and the semiconductor component includes an N-type semiconductor and a P-type semiconductor;

[0021] The first conductive layer is disposed on the first substrate;

[0022] A thermoelectric arm is grown on the first conductive layer and particle doping is performed to form the N-type semiconductor and the P-type semiconductor;

[0023] The first conductive layer is etched according to the structures of the N-type semiconductor and the P-type semiconductor.

[0024] The second conductive layer is deposited on the N-type semiconductor and the P-type semiconductor, and the second conductive layer is etched according to the structure of the N-type semiconductor and the P-type semiconductor;

[0025] The second substrate is deposited on the N-type semiconductor and the P-type semiconductor to form the cooling chip.

[0026] In one embodiment, the number of N-type semiconductors and P-type semiconductors is at least two, with adjacent P-type semiconductors spaced apart, and each N-type semiconductor is disposed between adjacent P-type semiconductors. An electrical signal on one P-type semiconductor passes sequentially through the second conductive layer, the N-type semiconductor, and the first conductive layer to reach the other P-type semiconductor.

[0027] In one embodiment, the cooling chip is thinned, and prior to this, the following steps are also included:

[0028] A third substrate is disposed and a p-GaN layer is formed on the third substrate;

[0029] The p-GaN layer is etched, and a passivation structure is formed on the p-GaN layer;

[0030] The passivation structure is etched, and an electrode structure is formed on the passivation structure to form the body of the chip.

[0031] In one embodiment, a passivation structure is formed on the p-GaN layer, the passivation structure is etched, and an electrode structure is formed on the passivation structure to form the body of the chip, comprising:

[0032] The passivation structure includes a first passivation layer and a second passivation layer; the electrode structure includes a gate, a drain, and a source.

[0033] The first passivation layer is formed on the p-GaN layer;

[0034] The first passivation layer is etched, and the drain and the source are disposed on the first passivation layer to form an ohmic contact, and the gate is disposed to form a gate metal contact;

[0035] A second passivation layer is formed on the first passivation layer;

[0036] The second passivation layer is etched to form a metallized interconnect between the drain, the source, and the gate, thus forming the body of the chip.

[0037] A chip heat dissipation structure includes a heat sink, a substrate, and a cooling chip. The substrate is disposed on the heat sink and has a through-hole through it. The cooling chip has two opposite sides, a cold side and a hot side, respectively. The cold side of the cooling chip is used to adhere to the chip. When the cooling chip is installed in the mounting slot, the hot side of the cooling chip can adhere to the heat sink, and the cold side is flush with the surface of the substrate facing away from the heat sink.

[0038] The aforementioned chip heat dissipation structure and its fabrication method, by thinning the cooling chip, allow the cold side of the cooling chip to directly contact the chip, improving cooling efficiency. This also reduces the thickness of the cooling chip, enabling it to be flush with the substrate surface after installation in the mounting slot, thus reducing the overall volume of the chip heat dissipation structure and increasing the integration of the chip heat dissipation structure and related equipment. Simultaneously, the hot side of the cooling chip is in contact with the heat sink, further improving the heat dissipation effect and efficiency of the chip heat dissipation structure. Attached Figure Description

[0039] The accompanying drawings, which form part of this application, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of the chip heat dissipation structure in one embodiment;

[0042] Figure 2 for Figure 1 A schematic diagram of the chip and cooling chip packaging in the embodiment;

[0043] Figure 3 for Figure 1 A schematic diagram of the structure of the cooling chip in the embodiment;

[0044] Figure 4 for Figure 1 A schematic diagram of the main structure of the chip in the embodiment.

[0045] The components in the diagram are labeled as follows:

[0046] 10. Chip heat dissipation structure; 100. Cooling chip; 110. First substrate; 120. Conductive structure; 121. First conductive layer; 122. Second conductive layer; 130. Semiconductor component; 131. N-type semiconductor; 132. P-type semiconductor; 140. Second substrate; 150. Electrode component; 151. Negative electrode; 152. Positive electrode; 200. Chip body; 210. Third substrate; 220. p-GaN layer; 230. Passivation structure; 231. First passivation layer; 232. Second passivation layer; 240. Electrode structure; 241. Drain; 242. Source; 243. Gate; 300. Substrate; 400. Heat sink. Detailed Implementation

[0047] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0048] See Figure 1 and Figure 2 A chip heat dissipation structure 10 in one embodiment includes a substrate 300, a heat sink 400, and a cooling element. In this embodiment, the cooling element is a cooling chip 100. The substrate 300 is disposed on the heat sink 400, and a mounting groove is formed through the substrate 300. The two opposite sides of the cooling chip 100 are a cold surface and a hot surface, respectively. The cold surface of the cooling chip 100 is used to adhere to the chip. When the cooling chip 100 is installed in the mounting groove, the hot surface of the cooling chip 100 can adhere to the heat sink 400, and the cold surface is flush with the surface of the substrate 300 facing away from the heat sink 400. The chip heat dissipation structure 10 is applied in various fields such as medicine, military, optics, and beauty, and effectively cools and dissipates heat for electronic products in related fields.

[0049] A method for fabricating the chip heat dissipation structure 10 in one embodiment includes:

[0050] The cooling chip 100 is thinned so that the cold side of the cooling chip 100 is attached to the chip; wherein, the two opposite sides of the cooling chip 100 are the cold side and the hot side, respectively.

[0051] A mounting groove is formed through the substrate 300; wherein, the substrate 300 is disposed on the heat sink 400;

[0052] The cooling chip 100 is installed in the mounting groove so that the hot surface and the heat sink 400 are in contact; wherein the cold surface of the cooling chip 100 is flush with the surface of the substrate 300 facing away from the heat sink 400.

[0053] The chip and the cooling chip 100 are packaged.

[0054] The aforementioned chip heat dissipation structure 10 and its fabrication method, by thinning the cooling chip 100, allow the cold surface of the cooling chip 100 to directly contact the chip, improving cooling efficiency. This also reduces the thickness of the cooling chip 100, enabling it to be flush with the surface of the substrate 300 after installation in the mounting slot. This reduces the overall volume of the chip heat dissipation structure 10 and increases the integration of the chip heat dissipation structure 10 and related devices. Simultaneously, the hot surface of the cooling chip 100 is in contact with the heat sink 400, further improving the heat dissipation effect and efficiency of the chip heat dissipation structure 10.

[0055] In one embodiment, the thinning process of the cooling chip 100 includes:

[0056] The refrigeration chip 100 is unsealed and the ceramic layer of the refrigeration chip 100 is removed; the initial state of the refrigeration chip 100 is a sealed state, and the refrigeration chip 100 has a ceramic layer, which is disposed on the cold surface.

[0057] Typically, the cooling chip 100 is integrated with the chip in a packaged state. The packaged cooling chip 100 is relatively thick, resulting in a large overall structure after integration with the chip, which hinders the miniaturization of electronic products. However, by unpacking the cooling chip 100 and removing the ceramic layer, the thickness of the cooling chip 100 is reduced, effectively lowering the overall structural thickness. This allows direct contact between the chip and the cold surface of the cooling chip 100, ensuring the heat dissipation efficiency of the chip heat dissipation structure 10.

[0058] In one embodiment, mounting the cooling chip 100 within the mounting slot includes:

[0059] The electrode leads of the cooling chip 100 and the electrode leads of the chip are both connected to the substrate 300.

[0060] Currently, thermal coolers require additional power supply wiring design during operation, which complicates the circuit structure of electronic products. However, by making the thermal cooler 100 directly contact the chip, the electrode leads on the thermal cooler 100 and the electrode leads on the chip can be connected to the same substrate 300, reducing the complexity of the electronic product's circuit structure, ensuring the reliability of the chip heat dissipation structure 10, and improving cooling efficiency.

[0061] In one embodiment, mounting the cooling chip 100 in the mounting slot further includes:

[0062] The cooling chip 100 is integrally formed on the substrate 300 and located in the mounting groove.

[0063] The current method of using a cooling chip mainly involves fixing it with screws, adhesive, welding, or using pads or other materials to tightly attach it to the heating element. The cold side of the cooling chip is in close contact with the heating side of the element, allowing heat to be conducted in equilibrium. Simultaneously, a heat sink 400 is installed on the hot side to conduct heat to the outside. However, this connection method results in a relatively thick chip heat dissipation structure, leading to a larger component size and hindering the miniaturization of the instrument structure. In this embodiment, the cooling chip 100 is integrally formed on the substrate 300, allowing the hot side of the cooling chip 100 to directly contact the heat sink 400, quickly dissipating heat and improving the cooling efficiency of the cooling chip 100. The chip can also directly contact the cold side of the cooling chip 100, further improving the cooling efficiency of the cooling chip 100 on the chip, ensuring the practicality and reliability of the chip heat dissipation structure 10, and improving the overall integration of the structure.

[0064] See Figure 2 and Figure 3 In one embodiment, the cooling chip 100 is thinned, prior to which the following steps are included:

[0065] A first substrate 110 is provided, and a conductive structure 120 is provided on the first substrate 110;

[0066] A semiconductor component 130 is disposed on the conductive structure 120, and the conductive structure 120 is etched.

[0067] A second substrate 140 is disposed on the semiconductor component 130 to form the cooling chip 100.

[0068] In one embodiment, a conductive structure 120 is formed on a first substrate 110, a semiconductor component 130 is formed on the conductive structure 120, the conductive structure 120 is etched, and a second substrate 140 is deposited on the semiconductor component 130 to form the cooling chip 100, comprising:

[0069] The conductive structure 120 includes a first conductive layer 121 and a second conductive layer 122, and the semiconductor component 130 includes an N-type semiconductor 131 and a P-type semiconductor 132.

[0070] The first conductive layer 121 is disposed on the first substrate 110;

[0071] A thermoelectric arm is grown on the first conductive layer 121 and particle doping is performed to form the N-type semiconductor 131 and the P-type semiconductor 132.

[0072] The first conductive layer 121 is etched according to the structure of the N-type semiconductor 131 and the P-type semiconductor 132;

[0073] The second conductive layer 122 is deposited on the N-type semiconductor 131 and the P-type semiconductor 132, and the second conductive layer 122 is etched according to the structure of the N-type semiconductor 131 and the P-type semiconductor 132.

[0074] The second substrate 140 is disposed on the N-type semiconductor 131 and the P-type semiconductor 132 to form the cooling chip 100.

[0075] In one embodiment, the second substrate 140 is deposited over the N-type semiconductor 131 and the P-type semiconductor 132, and the process further includes:

[0076] An electrode assembly 150 of the cooling chip 100 is disposed on the first conductive layer 121; wherein, the negative electrode 151 of the electrode assembly 150 is connected to the P-type semiconductor 132, and the positive electrode 152 of the electrode assembly 150 is connected to the N-type semiconductor 131. The electrode assembly 150 is used to connect to the substrate 300 and supply power to the cooling chip 100 through the substrate 300.

[0077] In one embodiment, the second substrate 140 is disposed over the N-type semiconductor 131 and the P-type semiconductor 132, and then the process further includes:

[0078] The first substrate 110 and the second substrate 140 are thinned.

[0079] In one embodiment, there are at least two N-type semiconductors 131 and at least two P-type semiconductors 132. Two adjacent P-type semiconductors 132 are spaced apart, and each N-type semiconductor 131 is disposed between two adjacent P-type semiconductors 132. An electrical signal on one P-type semiconductor 132 passes through the second conductive layer 122, the N-type semiconductor 131, and the first conductive layer 121 in sequence to reach another P-type semiconductor 132.

[0080] See Figure 2 and Figure 4 In one embodiment, the cooling chip 100 is thinned, prior to which the following steps are included:

[0081] A third substrate 210 is provided, and a p-GaN layer 220 is formed on the third substrate 210;

[0082] The p-GaN layer 220 is etched, and a passivation structure 230 is formed on the p-GaN layer 220;

[0083] The passivation structure 230 is etched, and an electrode structure 240 is disposed on the passivation structure 230 to form the main body 200 of the chip.

[0084] In one embodiment, a passivation structure 230 is formed on the p-GaN layer 220, the passivation structure 230 is etched, and an electrode structure 240 is formed on the passivation structure 230 to form the body 200 of the chip, including:

[0085] The passivation structure 230 includes a first passivation layer 231 and a second passivation layer 232; the electrode structure 240 includes a gate 243, a drain 241 and a source 242;

[0086] The first passivation layer 231 is formed on the p-GaN layer 220;

[0087] The first passivation layer 231 is etched, and the drain 241 and the source 242 are disposed on the first passivation layer 231 to form an ohmic contact. The gate 243 is disposed to form a gate 243 metal contact.

[0088] The second passivation layer 232 is formed on the first passivation layer 231;

[0089] The second passivation layer 232 is etched to form a metallized interconnect of the drain 241, the source 242 and the gate 243, forming the body 200 of the chip.

[0090] Specifically, the main body 200 of the chip is a gallium nitride high electron mobility transistor (GaN transistor). As a representative of wide-bandgap power semiconductor devices, GaN transistors have enormous potential in high-frequency power applications. Furthermore, GaN materials exhibit higher electron mobility, saturation electron velocity, and breakdown electric field compared to Si and SiC.

[0091] When semiconductors come into contact with metals, a potential barrier layer is usually formed. However, when the semiconductor doping concentration is very high, electrons can tunnel through the barrier, thus forming a low-resistance ohmic contact. Ohmic contacts are very important for semiconductor devices. Forming a good ohmic contact is beneficial for current input and output. For different semiconductor materials, alloys with different formulations are often selected as ohmic contact materials.

[0092] In one embodiment, the drain 241, the source 242, and the gate 243 form a metallized interconnect, and then the following is further included:

[0093] The third substrate 210 is thinned.

[0094] In one embodiment, the process of forming the cooling chip 100 and the body 200 forming the chip includes:

[0095] The cooling chip 100 and the main body 200 of the chip are packaged together.

[0096] To ensure the stability of the connection between the cooling chip 100 and the chip. Simultaneously, during packaging, the electrode leads of both the chip and the cooling chip 100 are connected to the substrate 300.

[0097] In one embodiment, thermal grease is applied between the hot side of the cooling chip 100 and the heat sink 400. This further improves thermal conductivity. Since the cooling chip and the chip can be in direct contact, the cooling efficiency is improved, eliminating the need for thermal grease between them.

[0098] In one embodiment, encapsulating the cooling chip 100 and the chip body 200 includes:

[0099] Remove or thin the second substrate 140;

[0100] The third substrate 210 and the second conductive layer 122 are bonded together;

[0101] Complete packaging.

[0102] Since the third substrate 210 of the chip 200 is close to the second conductive layer 122 at the top of the cooling chip, the second substrate 140 at the top of the cooling chip 100 can be thinned or completely removed, and the second conductive layer 122 at the top of the cooling chip 100 can be directly bonded to the third substrate 210 of the chip, and finally the two parts are packaged together.

[0103] As the integration of electronic components continues to increase, the heat generated during component operation cannot be dissipated to the outside in a timely manner, leading to excessively high internal temperatures and hot spots. This reduces the device's performance and, in severe cases, damages the entire device. To address this issue, thermal management technology has been proposed and applied in many fields to solve various heat dissipation problems. Currently, numerous heat dissipation technologies exist in the chip and packaging fields alone, including external heat sinks, heat pipes, air cooling, and water cooling solutions.

[0104] The Peltier effect in semiconductors can be used as a heat dissipation method in solid-state refrigeration. Semiconductor refrigeration, also known as thermoelectric refrigeration, utilizes the Peltier effect of semiconductor materials. When direct current passes through a thermocouple composed of two different semiconductor materials (P-type and N-type semiconductors) connected in series, heat can be absorbed and released at the two ends of the thermocouple, achieving the purpose of cooling. This method is a refrigeration technology that generates negative thermal resistance. Its main characteristics are no moving parts, no noise, small size, convenient operation and maintenance, compact structure, and no need for coolant. The cooling efficiency can be adjusted by changing the magnitude and direction of the current, and it has high reliability. Specifically, doping a semiconductor with acceptor impurities so that the hole concentration is greater than the electron concentration yields a P-type semiconductor. Doping a semiconductor with donor impurities so that the electron concentration is greater than the hole concentration yields an N-type semiconductor.

[0105] When electrons flow from a low-energy P-type material to a high-energy N-type material, they jump from a lower energy level to a higher energy level. This requires heat absorption, creating a cold surface (the cold surface of the thermoelectric cooler) at this point. Conversely, when electrons flow from a high-energy N-type material to a low-energy P-type material, they jump from a higher energy level to a lower energy level. This requires heat release, creating a hot surface (the hot surface of the thermoelectric cooler) at this point. In fact, most closed loops formed by different metals exhibit this phenomenon; the Peltier effect is more pronounced in commercially available bismuth telluride-based thermoelectric materials, meaning the electron energy level jumps are higher, resulting in higher cooling efficiency.

[0106] This application effectively reduces the thickness of the cooling chip 100 by opening the package and removing the surface ceramic layer. After bonding the cooling chip 100 to the chip, the electrode leads of the cooling chip 100 and the electrode leads of the chip are bonded to the same substrate 300, eliminating the need to provide additional wires for power supply to the cooling chip 100. At the same time, integrating the cooling chip 100 integrally onto the substrate 300 can significantly improve the integration density.

[0107] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0108] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0109] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0110] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first and second features directly abut each other, or that the first and second features indirectly abut each other through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0111] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0112] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0113] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for fabricating a chip heat dissipation structure, characterized in that, The method for preparing the chip heat dissipation structure includes: A first substrate is provided, and a conductive structure is formed on the first substrate; a semiconductor component is formed on the conductive structure, and the conductive structure is etched; a second substrate is placed on the semiconductor component to form a cooling chip; the initial state of the cooling chip is a packaged state, and the cooling chip has a ceramic layer; a third substrate is provided, and a p-GaN layer is formed on the third substrate; the p-GaN layer is etched, and a passivation structure is formed on the p-GaN layer; the passivation structure is etched, and an electrode structure is formed on the passivation structure to form the main body of the chip; The cooling chip is thinned to allow the cold side of the cooling chip to adhere to the chip; wherein, the two opposite sides of the cooling chip are the cold side and the hot side, respectively, and the ceramic layer is disposed on the cold side; the cooling chip is unpacked and the ceramic layer of the cooling chip is removed; A mounting groove is formed through the substrate; wherein the substrate is mounted on a heat sink. The cooling chip is installed in the mounting groove so that the hot surface and the heat sink are in contact; wherein, the cold surface of the cooling chip is flush with the surface of the substrate facing away from the heat sink; the cooling chip is integrally formed on the substrate and located in the mounting groove; The chip and the cooling chip are packaged.

2. The method for preparing the chip heat dissipation structure according to claim 1, characterized in that, Installing the cooling chip in the mounting slot includes: The electrode leads of the cooling chip and the electrode leads of the chip are both connected to the substrate.

3. The method for preparing the chip heat dissipation structure according to claim 1 or 2, characterized in that, A second substrate is deposited on the semiconductor assembly, and the assembly further includes: The first substrate and the second substrate are thinned.

4. The method for preparing the chip heat dissipation structure according to claim 3, characterized in that, A conductive structure is formed on a first substrate, a semiconductor component is formed on the conductive structure, the conductive structure is etched, and a second substrate is deposited on the semiconductor component to form the cooling chip, comprising: The conductive structure includes a first conductive layer and a second conductive layer, and the semiconductor component includes an N-type semiconductor and a P-type semiconductor; The first conductive layer is disposed on the first substrate; A thermoelectric arm is grown on the first conductive layer and particle doping is performed to form the N-type semiconductor and the P-type semiconductor; The first conductive layer is etched according to the structures of the N-type semiconductor and the P-type semiconductor. The second conductive layer is deposited on the N-type semiconductor and the P-type semiconductor, and the second conductive layer is etched according to the structure of the N-type semiconductor and the P-type semiconductor; The second substrate is deposited on the N-type semiconductor and the P-type semiconductor to form the cooling chip.

5. The method for preparing the chip heat dissipation structure according to claim 4, characterized in that, The number of N-type semiconductors and P-type semiconductors is at least two. Adjacent P-type semiconductors are spaced apart, and each N-type semiconductor is disposed between two adjacent P-type semiconductors. An electrical signal on one P-type semiconductor passes through the second conductive layer, the N-type semiconductor, and the first conductive layer in sequence to reach the other P-type semiconductor.

6. The method for preparing the chip heat dissipation structure according to claim 1 or 2, characterized in that, A passivation structure is formed on the p-GaN layer, the passivation structure is etched, and an electrode structure is formed on the passivation structure to form the main body of the chip, comprising: The passivation structure includes a first passivation layer and a second passivation layer; the electrode structure includes a gate, a drain, and a source. The first passivation layer is formed on the p-GaN layer; The first passivation layer is etched, and the drain and the source are disposed on the first passivation layer to form an ohmic contact, and the gate is disposed to form a gate metal contact; A second passivation layer is formed on the first passivation layer; The second passivation layer is etched to form a metallized interconnect between the drain, the source, and the gate, thus forming the body of the chip.

7. The method for preparing the chip heat dissipation structure according to claim 6, characterized in that, The drain, the source, and the gate form a metallized interconnect, and then the system further includes: The third substrate is thinned.

8. The method for preparing the chip heat dissipation structure according to claim 6, characterized in that, After forming the cooling chip and the body forming the chip, the process includes: Remove or thin the second substrate; Bond the third substrate and the second conductive layer together; Complete packaging.

9. The method for preparing the chip heat dissipation structure according to claim 6, characterized in that, The main body of the chip is a gallium nitride high electron mobility transistor.

10. A chip heat dissipation structure, prepared using the method for preparing a chip heat dissipation structure according to any one of claims 1-9, characterized in that, The chip heat dissipation structure includes: Heat dissipation components; A substrate, wherein the substrate is disposed on the heat sink, and a mounting groove is formed through the substrate; and The cooling chip has a cold side and a hot side on opposite sides. The cold side of the cooling chip is used to bond with the chip. When the cooling chip is installed in the mounting slot, the hot side of the cooling chip can bond with the heat sink, and the cold side is flush with the surface of the substrate facing away from the heat sink.

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