Through Silicon Via Test Structure and Test Method

Abstract

This application relates to a TSV substrate noise test structure. In this test structure, a first excitation TSV and a second excitation TSV are embedded in the front surface of a test wafer substrate. The first and second excitation TSVs are electrically connected to form an excitation TSV pair. Test contact areas are formed around the excitation TSVs. A pulse signal is applied to the excitation TSV pair, and the TSV substrate noise is determined by measuring the ground response signals of each test contact area. This test structure simplifies the test structure for obtaining excitation TSV substrate noise and can effectively obtain excitation TSV substrate noise.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a through silicon via test structure and test method. Background Art

[0002] With the rapid development of the integrated circuit and semiconductor industries, Moore's Law, which it follows, has been challenged by the limitations of chip physics, processing technology, and manufacturing costs. To address this challenge, three-dimensional (3D) integration technology has emerged.

[0003] For example, taking Through Silicon Via (TSV) technology as an example, TSV technology is a 3D integration process that can expand the integration dimension of the chip from 2D to the vertical direction of 3D, realizing 3D stacking of chips. This technology not only greatly improves the chip integration, but also shortens the length of the interconnection lines between chips.

[0004] However, when the chips are 3D stacked using the through-silicon via technology, the substrate noise introduced has a significant impact on chip performance. Summary of the Invention

[0005] The embodiments of the present application provide a through-silicon via (TSV) test structure and test method, which can effectively determine the substrate noise introduced by the TSV to the surrounding area through a TSV test structure with simplified process.

[0006] In a first aspect, an embodiment of the present application provides a test structure for through-silicon via substrate noise, the test structure comprising: a first excitation through-silicon via, a second excitation through-silicon via, and at least one set of test contact areas;

[0007] The first excitation through silicon via and the second excitation through silicon via are both embedded in the front surface of the test wafer substrate. The first excitation through silicon via and the second excitation through silicon via are electrically connected to form an excitation through silicon via pair. Each test contact area is located around the excitation through silicon via.

[0008] A pulse signal is applied to the pair of stimulated TSVs, and the ground response signal of each test contact area is measured to determine the TSV substrate noise.

[0009] In one embodiment, the pulse signal is a square wave pulse.

[0010] In one embodiment, each group of test contact areas includes: front test contact areas and / or back test contact areas; the front test contact areas are prepared on the front side of the test wafer substrate; and the back test contact areas are prepared on the back side of the test wafer substrate at a position corresponding to the front test contact areas.

[0011] In one embodiment, the test structure further includes: at least one through-silicon-via cluster embedded in the front side of the test wafer substrate; any one of the at least one through-silicon-via clusters includes at least two parallel through-silicon-vias; the tops of the at least two parallel through-silicon-vias are connected via a metal extension electrode, and the bottoms of the at least two parallel through-silicon-vias are connected to the back side test contact area via the metal extension electrode.

[0012] In one embodiment, the tops of the at least two parallel TSVs are connected via a metal extension electrode, and then connected to the front test contact region via the metal extension electrode.

[0013] In one embodiment, each TSV cluster is prepared at a different position on the front side of the test wafer substrate, and each TSV cluster has a different distance from the front side of the test wafer substrate to the stimulation TSV pair.

[0014] In one embodiment, the distances between the locations of the TSV clusters on the front side of the test wafer substrate and the stimulated TSV pairs are gradually increased.

[0015] In one embodiment, the test wafer substrate and the carrier wafer are bonded together by a temporary bonding adhesive layer.

[0016] In a second aspect, an embodiment of the present application provides a method for testing through-silicon via substrate noise, the method comprising:

[0017] Applying a pulse signal to a first excitation through silicon via and a second excitation through silicon via, wherein the first excitation through silicon via and the second excitation through silicon via are both embedded in the front surface of the test wafer substrate, and the first excitation through silicon via and the second excitation through silicon via are electrically connected to form an excitation through silicon via pair;

[0018] Acquiring a ground response pulse signal of at least one group of test contact areas formed around the excitation through silicon via;

[0019] The TSV substrate noise is determined based on the ground response signal of each test contact area.

[0020] In one embodiment, each set of test contact areas includes: a front test contact area and / or a back test contact area;

[0021] The TSV substrate noise is determined based on the ground response signals of each test contact area, including:

[0022] The TSV substrate noise is determined by measuring the ground response signals of the backside test contact region and / or the frontside test contact region when the TSV pair is stimulated by a square wave pulse.

[0023] In a third aspect, an embodiment of the present application provides a through-silicon via substrate noise testing device, the device comprising:

[0024] a signal applying module, configured to apply a pulse signal to a first excitation TSV and a second excitation TSV; wherein the first excitation TSV and the second excitation TSV are both embedded in the front surface of the test wafer substrate, and the first excitation TSV and the second excitation TSV are electrically connected to form an excitation TSV pair;

[0025] A signal acquisition module, configured to acquire a ground response pulse signal of at least one group of test contact areas formed around the excitation through silicon via;

[0026] The noise determination module is used to determine the through silicon via substrate noise according to the ground response signal of each test contact area.

[0027] In a fourth aspect, an embodiment of the present application provides a computer device comprising a memory and a processor, wherein a computer program is stored in the memory. When the computer program is executed by the processor, the processor executes the method steps in any one of the embodiments provided in the second aspect above.

[0028] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method steps in any one of the embodiments provided in the second aspect are implemented.

[0029] An embodiment of the present application provides a test structure for TSV substrate noise, wherein a first excitation TSV and a second excitation TSV are both embedded in the front surface of a test wafer substrate, and the first excitation TSV and the second excitation TSV are electrically connected to form an excitation TSV pair; each test contact area is located around the excitation TSV; a pulse signal is applied to the excitation TSV pair, and the TSV substrate noise is determined by measuring the ground response signals of each test contact area when the excitation TSV pair passes through the pulse signal. In this test structure, the manufacturing process of the structure is compatible with conventional TSV processes, and deep silicon etching of all TSVs is completed in one step. The overall test structure process is simple, simplifying the test structure for obtaining the substrate noise of the excitation TSV. Based on this test structure, the substrate noise of the excitation TSV pair can be obtained by measuring the ground response signals of at least one group of adjacent test contact areas when the excitation TSV pair passes through the pulse signal, effectively obtaining the substrate noise of the excitation TSV. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Schematic diagram of a test structure for through silicon via substrate noise in one embodiment of the present application;

[0031] Figure 2 Schematic diagram of a test structure for through silicon via substrate noise in another embodiment of the present application;

[0032] Figure 3 Schematic diagram of a test structure for through silicon via substrate noise in another embodiment of the present application;

[0033] Figure 4 Schematic diagram of a test structure for through-silicon via substrate noise in another embodiment of the present application;

[0034] Figure 5 Schematic diagram of a test structure for through-silicon via substrate noise in another embodiment of the present application;

[0035] Figure 6 Schematic diagram of a test structure for through-silicon via substrate noise in another embodiment of the present application;

[0036] Figure 7 Schematic diagram of a test structure for through-silicon via substrate noise in another embodiment of the present application;

[0037] Figure 8 Schematic diagram of a test structure for through-silicon via substrate noise in another embodiment of the present application;

[0038] Figure 9 FIG. 1 is a flow chart of a method for testing through silicon via substrate noise in an embodiment of the present application.

[0039] Description of reference numerals:

[0040] 101: a first excitation through silicon via; 102: a second excitation through silicon via;

[0041] 103: test contact area; 104: test wafer substrate;

[0042] 105: exciting through-silicon via pair; 106: carrier wafer;

[0043] 107; Temporary bonding adhesive layer; 108: Grounding through silicon via;

[0044] 109: etch stop layer; 110: insulating layer;

[0045] 111: a first metal pad; 112: a second metal pad;

[0046] 113: a metal pad for a grounded through silicon via; 114: a third metal pad;

[0047] 115: a fourth metal pad; 116: a through-silicon via cluster;

[0048] 1031: front test contact area; 1032: back test contact area;

[0049] 1161: Through Silicon Via in a Through Silicon Via Cluster. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0051] It should be understood that the terms "first," "second," and the like in the claims, specification, and drawings of this application are used to distinguish between different objects, rather than to describe a specific order. The term "comprising" as used in the specification and claims of this application indicates the presence of the described features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0052] It should also be understood that the terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this application. As used in this specification and claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" as used in this specification and claims refers to any and all possible combinations of one or more of the associated listed items, including and including these combinations.

[0053] Next, the test structure for TSV substrate noise provided by the present application will be described in detail with reference to the accompanying drawings.

[0054] In one embodiment, Figure 1 As shown, an embodiment of the present application provides a test structure for TSV substrate noise, which includes: a first excitation TSV 101, a second excitation TSV 102 and at least one group of test contact areas 103; the first excitation TSV 101 and the second excitation TSV 102 are both embedded in the front side of a test wafer substrate 104, and the first excitation TSV 101 and the second excitation TSV 102 are electrically connected to form an excitation TSV pair 105; each test contact area 103 is prepared around the excitation TSV; a pulse signal is applied to the excitation TSV pair 105, and the TSV substrate noise is determined by measuring the ground response signal of each test contact area 103 when the excitation TSV pair 105 passes the pulse signal.

[0055] In the embodiment of the present application, the test structure is mainly based on the test wafer substrate 104 and the carrier wafer 106. Figure 1, the carrier wafer 106 is located below the test wafer substrate 104. Optionally, the test wafer substrate 104 can be silicon (Si), or can be other semiconductor materials, such as germanium, gallium arsenide, etc.; the material of the carrier wafer 106 can be glass, or semiconductor materials such as silicon, and the embodiment of the present application does not limit the materials of the test wafer substrate 104 and the carrier wafer 106. It should be noted that, for the sake of convenience, the embodiment of the present application uses silicon vias to describe the device structure of "making vertical conductions between chips and chips, between wafers and wafers, and realizing interconnection between chips", but those skilled in the art should know that the materials of the method in the embodiment of the present application are not limited to silicon wafers, and the shape and doping conditions of the silicon vias are not limited; any other devices with silicon via structures and functions, such as germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium nitride (GaN), graphene materials, etc., can also be tested using the method provided in the embodiment of the present application.

[0056] Optionally, the test wafer substrate 104 and the carrier wafer 106 are adhered to each other by a temporary bonding adhesive layer 107, that is, the test wafer substrate 104 and the carrier wafer 106 are temporarily bonded by the temporary bonding adhesive layer 107, so that the carrier wafer 106 added to the lower part of the test wafer substrate 104 can be untied or released. In this way, the carrier wafer 106 on the back side of the test wafer substrate 104 can be released through the unbinding process, which facilitates the failure and reliability analysis of the bottom structure of the silicon via prepared in the test wafer substrate 104.

[0057] Optionally, the temporary binding adhesive layer between the test wafer substrate 104 and the carrier wafer 106 can be removed by any method such as light, solvent, dissolution, or mechanical means, which is not limited in this embodiment of the present application.

[0058] Embedded within the upper portion (i.e., the front surface) of the test wafer substrate 104 are a first excitation TSV 101, a second excitation TSV 102, and at least one set of test contact areas 103. The first excitation TSV 101 and the second excitation TSV 102 are electrically connected to form an excitation TSV pair 105. Each test contact area is formed around the excitation TSV pair. Optionally, each test contact area is formed within a predetermined range around the excitation TSV pair, for example, within a range of 20 to 300 μm from the excitation TSV pair.

[0059] For example, the front side of the test wafer substrate 104 may be thinned and polished to a thickness of 100-300 μm, and then deep silicon etching may be performed to form the first excitation through-silicon via 101 and the second excitation through-silicon via 102. Alternatively, the front side of the test wafer substrate 104 may be thinned and polished to a thickness of 50-100 μm, and then deep silicon etching may be performed to form the first excitation through-silicon via 101 and the second excitation through-silicon via 102. The embodiment of the present application does not limit the thickness to which the front side of the test wafer substrate 104 is thinned and polished.

[0060] Please continue to see Figure 1 The test structure also includes a grounded TSV 108, which is also embedded in the front surface of the test wafer substrate 104. The sidewalls of the grounded TSV 108 contact the entire depth of the test wafer substrate 104, penetrating the test wafer substrate 104 and completely connecting to the ground. An etch stop layer 109 is formed at the bottom of the grounded TSV 108, and this etch stop layer 109 is also formed on the back surface of the test wafer substrate 104 to prevent overetching during the simultaneous etching process with other TSV structures.

[0061] In actual applications, an insulating layer 110 is further provided at the bottom of the test wafer substrate 104. This insulating layer 110 electrically isolates the embedded excitation TSV pair and each test contact area from the test wafer substrate 104. The first excitation TSV 101 and the second excitation TSV 102 are electrically connected via a redistribution layer (RDL) metal electrode L fabricated beneath the insulating layer 110 and are insulated from the test wafer substrate 104.

[0062] For example, the insulating layer 110 is prepared as follows: based on the first and second excitation through-silicon vias 101 and 102 prepared as described above, the insulating layer 110 is deposited on the bottoms, sidewalls, and surface of the test wafer substrate 104 of the first and second excitation through-silicon vias 101 and 102, and then the insulating layer 110 is removed from the bottom and sidewalls of the grounded through-silicon via 108 by wet etching, and the insulating layer 110 is removed from the bottoms of the other through-silicon vias by dry etching, while retaining the sidewall insulating layer 110. It should be understood that the insulating layer 110 on the sidewalls of the grounded through-silicon via 108 is removed by wet etching in order to form an electrical connection between the grounded through-silicon via 108 and the test wafer substrate 104.

[0063] Multiple groups of test contact areas 103 can be prepared within a preset range near the excitation TSV pair 105, and each group of test contact areas 103 is also connected to the metal pad by preparing an extended electrode. In this way, the test combination structure composed of each group of test contact areas, their extended electrodes and metal pads can be arranged and prepared at different positions around the excitation TSV pair to obtain the noise conditions at different positions in the substrate area around the excitation TSV pair. It should be noted that Figure 1FIG. 1 is a schematic diagram of the structure of only one group of test contact areas 103 . In practical applications, the configuration is not limited to one group of test contact areas 103 .

[0064] Furthermore, after the insulating layer 110 is prepared, a metal layer is deposited inside the through silicon via and on the surface of the test wafer substrate 104 , and then the extended electrodes and metal pads of the above-mentioned parts are prepared.

[0065] In one embodiment, see Figure 2 As shown, Figure 2 This is a schematic diagram of the test structure when viewed from the front, and the test structure also includes: a first metal pad 111 and a second metal pad 112 on the front side of the test wafer substrate 104; a first excitation silicon via 101 is connected to the first metal pad 111 through a metal extension electrode, and a second excitation silicon via 102 is connected to the second metal pad 112 through a metal extension electrode; a pulse signal is applied to the excitation silicon via pair 105 through the first metal pad 111 and the second metal pad 112.

[0066] See Figure 2 The bottom, sidewalls and openings of the excitation through silicon via pair 105 and the grounding through silicon via 108 are covered with a metal electrode layer, and are connected to the corresponding metal pads through extension leads prepared on the insulating layer 110 of the test wafer substrate 104. Figure 2 In the figure, it is 113. It should be noted that Figure 2 The metal pads corresponding to each group of test contact areas are not shown in the figure, but each group of test contact areas may also have corresponding metal pads when being prepared in the test structure, so that the probe can pass through the metal pads to perform substrate noise testing.

[0067] Based on this test structure, in actual application, when performing substrate noise test, a pulse signal is applied to both ends of the excitation silicon via through the first metal pad 111 and the second metal pad 112, and then the metal pads of each group of test contact areas 103 ( Figure 2 The ground level disturbance signal of each group of measurement contact areas 103 to the ground, i.e., the ground response signal, can be read. The substrate noise that excites the through-silicon via pair 105 can be determined by the measured ground response signal.

[0068] For example, the specific process of determining the substrate noise can be: after applying a pulse signal to both ends of the stimulated silicon via pair, a noise glitch signal to the ground at the test contact area position (i.e., a level disturbance signal to the ground or a response signal to the ground) is obtained, and then the glitch signal is analyzed by calculating the amplitude and integrated area of ​​the glitch signal, so as to determine the substrate noise level and action period or time generated by the stimulated silicon via pair 10.

[0069] In this embodiment, a test structure for TSV substrate noise is provided. In this test structure, a first excitation TSV 101 and a second excitation TSV 102 are embedded in the front surface of a test wafer substrate 104. The first excitation TSV 101 and the second excitation TSV 102 are electrically connected to form an excitation TSV pair 105. Test contact areas 103 are formed around the excitation TSVs. A pulse signal is applied to the excitation TSV pair 105, and the TSV substrate noise is determined by measuring the ground response signals of each test contact area 103 when the excitation TSV pair 105 passes through the pulse signal. This test structure is compatible with conventional TSV fabrication processes, allowing deep silicon etching of all TSVs to be completed in a single step. The overall test structure is simple to fabricate, simplifying the test structure for obtaining excitation TSV substrate noise. Furthermore, based on this test structure, the substrate noise of the excitation TSV pair can be obtained by measuring the ground response signals of at least one adjacent set of test contact areas when the excitation TSV pair passes through the pulse signal, effectively acquiring the excitation TSV substrate noise.

[0070] Optionally, in the above embodiment, the pulse signal applied at both ends of the excitation silicon via pair through the first metal pad 111 and the second metal pad 112 is a square wave pulse, for example, a square wave step signal, that is, when the square wave pulse is applied to the excitation silicon via 105 pair, the ground response signal of each test contact area 103 is measured to determine the silicon via substrate noise.

[0071] Specifically, when performing a substrate noise test, a square wave pulse or pulse voltage (current) signal is applied to both ends of the excitation silicon via through the first metal pad 111 and the second metal pad 112, and at the same time, the metal pad of the test contact area 103 and the metal pad 113 of the ground silicon via 108 are connected to an oscilloscope. The oscilloscope is used to measure the level disturbance signal of the test contact area 103 to the ground to obtain the substrate noise of the excitation silicon via.

[0072] For example, taking the pulse signal as a pulse voltage, the amplitude of the pulse voltage in the embodiment of the present application can be 1-3V, and the frequency is 100-1kHz; or, the amplitude of the pulse voltage can also be 0.2-1.25V, and the frequency is 1k-10kHz, or, the amplitude of the pulse voltage can be 1.8-3.5V, and the frequency is 10-1kHz. The embodiment of the present application does not limit the parameters of the applied pulse voltage.

[0073] Optionally, the pulse signal applied to both ends of the stimulating silicon through-hole pair may be a sine, triangular or other pulse signal in addition to the above-mentioned square wave pulse signal. However, when analyzing the glitch signal to obtain noise glitches, the square wave pulse signal can better obtain the noise glitches of the effective test contact area position to the ground than the sine wave pulse signal or the triangular pulse signal.

[0074] Optionally, when testing substrate noise, a signal amplifier may be connected between the metal pad of the test contact area 103 and the oscilloscope, and between the metal pad 113 of the grounded silicon via 108 and the oscilloscope. For example, the signal amplifier may be a preamplifier with an amplification factor of 10. 4 -10 6 .

[0075] In this embodiment, since the amplitude of the noise glitch signal from the metal pad of test contact region 103 to grounded TSV 108 is relatively small, a preamplifier can be connected to amplify the signal, facilitating identification of the voltage signal by an oscilloscope. Thus, by using the signal amplifier to amplify the ground response pulse signal of test contact region 103, the ground response pulse signal of test contact region 103 read on the oscilloscope is clearer and more accurate, thereby enabling more accurate and effective detection of substrate noise that excites the TSV.

[0076] Based on the above embodiment, the test contact area 103 is further described.

[0077] In one embodiment, Figure 3 As shown, each group of test contact areas 103 includes: front test contact areas 1031 and / or back test contact areas 1032; the front test contact areas 1031 are prepared on the front side of the test wafer substrate 104; and the back test contact areas 1032 are prepared on the back side of the test wafer substrate 104 at a position corresponding to the front test contact areas 1031.

[0078] In practical applications, each group of test contact areas 103 may include only front test contact areas 1031, only back test contact areas 1032, or both. Front test contact areas 1031 refer to test areas for testing substrate noise from the front side of the test wafer substrate 104. Therefore, front test contact areas 1031 are fabricated on the front side of the test wafer substrate 104 and are located within a preset range surrounding the pair of stimulated through-silicon vias 105. Back test contact areas 1032 refer to test areas for testing substrate noise from the back side of the test wafer substrate 104. Therefore, back test contact areas 1032 are fabricated on the back side of the test wafer substrate 104 at locations corresponding to the front test contact areas 1031.

[0079] The specific preparation process is to deposit an insulating layer 110 on the test wafer substrate 104, etch a back test contact area 1032 on the insulating layer 110, and then etch a front test contact area 1031 corresponding to the position of the back test contact area 1032 in an area adjacent to the excitation silicon through-hole 105 on the upper surface of the test wafer substrate 104.

[0080] As mentioned above, each group of test contact areas 103 is also connected to the metal pad by preparing a metal extension electrode. In one embodiment, Figure 4 As shown, Figure 4 The test contact area 103 shown as a top view of the test structure is also connected to the metal pad by preparing a metal extension electrode. Specifically, Figure 4 The front test contact area 1031 is connected to the third metal pad 114 through the metal extension electrode S, and the back test contact area 1032 is connected to the fourth metal pad 115 through the metal extension electrode S. In this way, the front test contact area 1031 measures the surface area ground noise of the test wafer substrate 104 through the third metal pad 114, and the back test contact area 1032 measures the back area ground noise of the test wafer substrate 104 through the fourth metal pad 115.

[0081] In one embodiment, when preparing the test structure, the third metal pad 114 and the fourth metal pad 115 can also be connected into one metal pad by extending the electrode. For example, the front test contact area 1031 can be connected to the fourth metal pad 115 by extending the electrode. In this way, the two test contact areas are measured with the same metal pad, which can achieve synchronous measurement of the ground noise of the surface and back areas.

[0082] In this embodiment, the noise signal can be monitored simultaneously from the back side, front side, or front side and back side of the test wafer substrate 104 to obtain the noise conditions of the stimulated silicon via 105 at different positions of the surrounding substrate area, and the substrate-to-ground noise can be tested from multiple dimensions to improve the accuracy and effectiveness of the substrate noise of the stimulated silicon via.

[0083] In addition, from the above Figure 4 It can also be seen that three TSVs are prepared around the test contact area. The structure formed by these three TSVs is called a TSV cluster. Figure 5 , Figure 5 The side view and top view of the test structure are combined to show Figure 5 The TSV clusters in the test structure are described in

[15] . In one embodiment, the test structure further includes: at least one TSV cluster 116 embedded in the front surface of the test wafer substrate 104; any one of the at least one TSV cluster 116 includes at least two parallel TSVs 1161; the tops of the at least two parallel TSVs 1161 are connected via a metal extension electrode, and the bottoms of the at least two parallel TSVs 1161 are connected to the backside test contact area 1032 via a metal extension electrode.

[0084] The test structure may include one or more TSV clusters 116, each TSV cluster 116 including two or more TSVs 1161 connected in parallel. For example, the test structure may include three TSVs connected in parallel. Figure 4 and Figure 5 In the figure, three TSVs connected in parallel are used as an example to form the TSV cluster 116. It can also be composed of four or five TSVs connected in parallel, etc. This embodiment of the present application is not limited to this.

[0085] For any TSV cluster 116, all of the TSVs 1161 included therein are connected at their tops via RDL metal extension electrodes and then to the fourth metal pad 115, while the bottoms of all TSVs are connected to the backside test contact area 1032 via RDL metal extension electrodes. A metal electrode layer is also formed on the TSV cluster, and the metal electrode layer of the TSV cluster can be electrically isolated from the test wafer substrate 104 by the insulating layer 110 formed on the bottom of the test wafer substrate 104.

[0086] For example, take TSV cluster 116 including two parallel TSVs 1161. The top layers of the two TSVs 1161 are connected to a fourth metal pad 115 via a metal extension electrode, and the bottom layers of the two TSVs are connected to backside test contact area 1032 via a metal extension electrode. Grounded TSV 108 is connected to metal pad 113 via a metal extension electrode. Therefore, the ground response pulse signal of backside test contact area 1032 can be measured via fourth metal pad 115 and metal pad 113 of grounded TSV 108 when a square wave pulse passes through the stimulated TSV pair.

[0087] For another example, the front test contact area 1031 is connected to the third metal pad 114 prepared on the front side of the test wafer substrate 104 through a metal extension electrode, and the ground response pulse signal of the front test contact area 1031 when the square wave pulse passes through the stimulated silicon via is measured through the third metal pad 114 and the metal pad 113 of the grounded silicon via 108.

[0088] For another example, the front test contact area 1031 can also be connected to the above-mentioned fourth metal pad 115 through a metal extension electrode. In this way, it is equivalent to connecting the front test contact area 1031 and the back test contact area 1032 together. The fourth metal pad 115 and the metal pad 113 of the grounded silicon via 108 can be used to measure the common ground response pulse signal of the front test contact area and the back test contact area when the square wave pulse passes through the stimulated silicon via.

[0089] The aforementioned excitation of the TSVs through the square wave pulse is achieved by applying a pulse signal at both ends of the excitation TSVs 105 through the first metal pad 111 and the second metal pad 112 .

[0090] Furthermore, using the signal amplifier in the aforementioned embodiment as an example, a signal amplifier can be connected after the third metal pad, the fourth metal pad, and the metal pad 113 of the grounded through-silicon via 108 to amplify the ground response pulse signal of the front test contact area and / or the back test contact area. It should be understood that each metal pad is used to measure the ground response pulse signal of a different contact area. Connecting a preamplifier after these metal pads not only amplifies the measured ground response pulse signal but also saves hardware resources.

[0091] It should be noted that in the embodiment of the present application, the distance between the extended electrode of the test contact area and the extended electrode of the excitation silicon via can be determined according to the chip active area layout design requirements. For example, the distance can be in the range of 20 to 300 um, which is not specifically limited here.

[0092] In addition, if Figure 6 As shown, in one embodiment, each TSV cluster 116 is formed at a different location on the front side of the test wafer substrate 104, and the distance d between each TSV cluster 116 on the front side of the test wafer substrate 104 and the stimulated TSV pairs 105 is different. Optionally, the distance d between each TSV cluster on the front side of the test wafer substrate 104 and the stimulated TSV pairs 105 increases.

[0093] Optionally, the distances gradually increase in a preset direction, wherein the preset direction may be clockwise or counterclockwise. Figure 6 In the figure, the test structure includes four TSV clusters 116 as an example, wherein the distances from the four TSV clusters 116 to the excitation TSV pair 105 are d1, d2, d3, and d4, respectively, and d1, d2, d3, and d4 increase gradually. In the test structure, the excitation TSV pair 105, four groups of test contact areas leading to four TSV clusters 116 and a ground TSV 108 are electrically connected.

[0094] When conducting a substrate noise test, taking a pulse voltage amplitude of 1.8-3.5V and a frequency of 10-1kHz as an example, a square wave or pulse voltage (current) signal is applied to both ends of the excitation silicon via pair 105 through the first metal pad 111 and the second metal pad 112. At the same time, the level disturbance signals of the test contact areas at different positions to the ground can be measured in groups through the metal pads 1151, 1152, 1153, 1154 and the metal pad 113 of the ground silicon via 108, thereby obtaining multiple groups of measurement data. The functional relationship between the substrate noise and the silicon via distance can be obtained with the multiple groups of measurement data. The substrate noise can further be calculated based on the functional relationship. In this way, the substrate noise is obtained by using multiple groups of data, which further ensures the accuracy and effectiveness of the obtained substrate noise.

[0095] It should be noted that in the test structure shown in the above example, the number of test contact areas, the number of TSV clusters, and the number of TSVs in each TSV cluster can all be adjusted according to actual applications. It is understandable that although a larger number is theoretically more accurate, it sacrifices chip area. Therefore, considering the accuracy of substrate noise and chip area, the number of TSVs in each TSV cluster can be 3-4. Of course, this is only an example, and the specific number can be determined according to actual conditions, and this embodiment of the application is not limited to this.

[0096] The present application also proposes a through silicon via substrate noise test structure, such as Figure 7 As shown, Figure 7 The area A framed by the dotted line is a schematic diagram of the test structure viewed from the front, which includes metal pads, through-silicon vias (first excitation through-silicon via 101, second excitation through-silicon via 102, multiple through-silicon vias 1161 in the through-silicon via cluster 116, and grounding through-silicon via 108). The area B framed by the dotted line is a side cross-sectional diagram of the test structure, including the metal extension electrode prepared inside, the back test contact area 1032, the front test contact area 1031, and the structure visible inside the temporary bonding adhesive layer 107. And in Figure 7 In the figure, the structures in the top view of area A and the side view of area B are jointly labeled.

[0097] See Figure 7 In this test structure, an etch stop layer 109 for grounded through-silicon vias 108 is prepared on the back side of the test wafer substrate 104. The material can be amorphous silicon. Then, an insulating layer 110 is deposited. Then, a back test contact area 1032 is etched on the insulating layer 110. Finally, a bottom extension electrode L for the excitation through-silicon via pair 105 and a metal extension electrode for the back test contact area 1032 are prepared.

[0098] The test wafer substrate 104 and the carrier wafer 106 are temporarily bonded together using a temporary bonding adhesive layer 107. The intermediate temporary bonding adhesive layer 107 can be removed when necessary by means of light exposure, solvent dissolution, etc., to unbundle or release the carrier wafer 106 at the bottom, thereby facilitating reliability and failure analysis of the bottom structure of the through-silicon via.

[0099] Specifically, the front side of the test wafer substrate 104 is thinned and polished to a thickness of 100-300 μm, and deep silicon etching is performed to prepare through-silicon vias (all through-silicon vias in the test structure). Then, an insulating layer 110 is deposited on the bottom and sidewalls of the through-silicon vias and on the surface of the test wafer substrate 104. Then, the insulating layer 110 at the bottom and sidewalls of the grounded through-silicon via 108 is removed by wet etching, and the insulating layer 110 at the bottom of other through-silicon vias (other through-silicon vias in the test structure except the grounded through-silicon via 108) is removed by dry etching, while the sidewall insulating layer 110 is retained. Finally, a metal layer is deposited in each through-silicon via and on the surface of the test wafer substrate 104, and a metal extension electrode and a metal pad are prepared.

[0100] The metal electrodes of the excitation TSV pair 105 are electrically connected through the RDL metal electrode L prepared under the insulating layer 110 ; the sidewalls of the grounded TSV 108 contact the entire depth of the test wafer substrate 104 , thereby achieving complete grounding of the grounded TSV 108 .

[0101] Among them, in this embodiment, the silicon via cluster 116 is composed of three silicon vias 1161 in parallel, the top of which is connected through the RDL metal extension electrode, and the bottom is connected to the back test contact area 1032 adjacent to the excitation silicon via pair 105 through the RDL metal extension electrode; the distance between the back test contact area 1032 and the extension electrode of the excitation silicon via can be determined according to the chip active area layout design requirements.

[0102] When performing noise testing, a square wave or pulse voltage (current) signal is applied to both ends of the excitation silicon vias 101 and 102 through the first metal pads 111 and 112. In this embodiment, the pulse voltage amplitude can be 1-3V and the frequency is 100-1000Hz as an example. Then, the fourth metal pad 115 of the back test contact area 1032 and the metal pad 113 of the ground silicon via 108 are connected to the oscilloscope to measure the level disturbance signal of the back test contact area 1032 to the ground.

[0103] The test structure of this embodiment only includes the back test contact area 1032 as an example for illustration, that is, in the test structure of this embodiment, after applying square wave signals to both ends of the first excitation silicon via 101 and the second excitation silicon via 102, the level disturbance signal of the back test contact area 1032 to the ground is obtained by measuring the fourth metal pad 115 of the back test contact area 1032 and the metal pad 113 of the ground silicon via 108, and the substrate noise is determined based on the level disturbance signal of the back test contact area 1032 to the ground.

[0104] The present application also proposes a through silicon via substrate noise test structure, such as Figure 8 As shown, Figure 8 Same as above Figure 7Similarly, the dotted-line framed area A is a schematic diagram of the test structure viewed from the front, which includes metal pads, through-silicon vias (first excitation through-silicon via 101, second excitation through-silicon via 102, multiple through-silicon vias in the through-silicon via cluster, and grounding through-silicon via 108). The dotted-line framed area B is a side cross-sectional diagram of the test structure, including the internally prepared metal extension electrode, the back test contact area, the front test contact area, the temporary bonding adhesive layer, etc. Figure 8 In the figure, the structures in the top view of area A and the side view of area B are also jointly labeled.

[0105] See Figure 8 As shown, in the test structure, an etching stop layer 109 for the grounded silicon via 108 is prepared on the back side of the test wafer substrate 104, and the material is selected from amorphous silicon or other metals; then an insulating layer 110 is deposited, and then a back test contact area 1032 is etched on the insulating layer 110, and then the bottom extension electrode of the excitation silicon via pair 105 and the extension electrode of the back test contact area 1032 are prepared.

[0106] The test wafer substrate 104 and the carrier wafer 106 are temporarily bonded together using a temporary bonding adhesive layer 107. Similarly, the intermediate temporary bonding adhesive layer 107 can be removed when necessary by irradiation with light, solvent dissolution, or the like, to unbundle or release the carrier wafer 106 at the bottom, thereby facilitating reliability and failure analysis of the bottom structure of the through-silicon via.

[0107] Specifically, the front side of the test wafer substrate 104 is thinned and polished to a thickness of 50-100 μm, and deep silicon etching is performed to prepare a through-silicon via (TSV). Then, an insulating layer 110 is deposited on the bottom, sidewalls and surface of the TSV 104. The insulating layer 110 at the bottom and sidewalls of the grounded TSV 108 is then removed by wet etching, and the insulating layer 110 at the bottom of other TSVs is removed by dry etching, while the sidewall insulating layer 110 is retained.

[0108] A front test contact area 1031 is etched around the perimeter of the stimulated through-silicon via (TSV), corresponding to the location of the back test contact area 1032. Finally, a metal layer is deposited within the TSV and on the surface of the test wafer substrate 104, and an extended electrode is fabricated and connected to the corresponding metal pad. In this embodiment, the extended electrode 211 of the front test contact area 1031 is connected to the back test contact area 1032, and both share a single metal pad, enabling simultaneous testing of the front test contact area 1031 and the back test contact area 1032.

[0109] The metal electrodes of the excitation TSV pair 105 are electrically connected through the RDL metal electrodes prepared under the insulating layer 110 . The sidewalls of the grounded TSV 108 contact the entire depth of the test wafer substrate 104 and penetrate the test wafer substrate 104 to be completely grounded.

[0110] The silicon via cluster 116 is composed of four silicon vias 1161 connected in parallel, the top of which is connected to the front test contact area 1031 through the RDL metal extension electrode 2, and the bottom is connected to the back test contact area 1032 adjacent to the excitation silicon via through the RDL metal extension electrode; the distance between the extension electrodes of the back test contact area 1032 and the front test contact area 1031 and the extension electrodes of the excitation silicon via pair 105 can be determined according to the chip active area layout design requirements, and the embodiments of the present application do not limit this.

[0111] When performing substrate noise testing, in this embodiment, the pulse voltage amplitude is 0.2-1.25V and the frequency is 1k-10kHz. For example, a square wave or pulse voltage (current) signal is applied to both ends of the excitation silicon vias 101 and 102 through the first metal pads 111 and 112, and is connected to a preamplifier (amplification factor 10) through the fourth metal pad 115 and the metal pad 113 of the ground silicon via 108. 4 -10 6 ), and then connected to the input end of the oscilloscope to measure the level disturbance signal of the back test contact area 1032 and the front test contact area 1031 to the ground.

[0112] The test structure of this embodiment includes both a back test contact area and a front test contact area. That is, in the test structure of this embodiment, after applying square wave signals to both ends of the first excitation silicon via 101 and the second excitation silicon via 102, the extended electrode 211 of the front test contact area 1031 is connected to the back test contact area 1032, and the two share the fourth metal pad 115. In this way, the common ground level disturbance signal of the front test contact area 1031 and the back test contact area 1032 is obtained by measuring the fourth metal pad 115 and the metal pad 113 of the ground silicon via 108, and the substrate noise is determined based on the common ground level disturbance signal of the two.

[0113] In addition, the present invention also provides a method for testing the noise of a through silicon via substrate. Figure 9 As shown, this embodiment includes:

[0114] S801, applying a pulse signal to a first excitation through silicon via and a second excitation through silicon via; wherein the first excitation through silicon via and the second excitation through silicon via are both embedded in the front surface of the test wafer substrate, and the first excitation through silicon via and the second excitation through silicon via are electrically connected to form an excitation through silicon via pair.

[0115] S802 , obtaining a ground response pulse signal of at least one group of test contact areas formed around an excitation through silicon via.

[0116] S803 , determining the through silicon via substrate noise according to the ground response signals of each test contact area.

[0117] Among them, a program instruction for indicating a test of through-silicon-via substrate noise can be pre-set. After the computer device receives a trigger of the program instruction, the corresponding operation is performed, that is, based on a test structure including a first excitation through-silicon-via and a second excitation through-silicon-via, both of which are embedded in the front surface of the test wafer substrate, and the first excitation through-silicon-via and the second excitation through-silicon-via are electrically connected to form an excitation through-silicon-via pair. According to the preset program instruction, a pulse signal is applied to the first excitation through-silicon-via and the second excitation through-silicon-via. Then, the computer device can continue to execute the preset program instruction to obtain a ground response pulse signal of at least one group of test contact areas prepared in a preset range area around the excitation through-silicon-via pair, and determine the through-silicon-via substrate noise according to the ground response signal of each test contact area.

[0118] It will be appreciated that the above process is implemented via computer program instructions, which are provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device, such that the instructions executed by the processor of the computer or other programmable data processing device implement the TSV substrate noise test in this embodiment. Of course, these computer program instructions may also be stored in a computer-readable memory that directs the computer or other programmable data processing device to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device. Alternatively, these computer program instructions may be loaded onto a computer or other programmable data processing device, causing the computer or other programmable device to execute a series of operational steps to produce a computer-implemented process, thereby executing the computer program instructions on the computer or other programmable device to implement the above-described functions.

[0119] The principles and logic for implementing each step according to program instructions in this embodiment are the same as those in the aforementioned test structure embodiments, and are not further described in this embodiment. Of course, when implementing TSV substrate noise testing in conjunction with program instructions, the implementation method can be adapted and handled accordingly, and this embodiment is not limited thereto.

[0120] In one embodiment, each group of test contact areas includes front-side test contact areas and / or back-side test contact areas. The process of determining the TSV substrate noise based on the ground response signals of each test contact area in step S803 includes determining the TSV substrate noise by measuring the ground response signals of the back-side test contact areas and / or the front-side test contact areas when the TSV pair is stimulated by a square wave pulse. This embodiment enables simultaneous monitoring of noise signals from the backside, frontside, or both sides of the wafer.

[0121] Based on the above-mentioned method for testing TSV substrate noise, an embodiment of the present application further provides a device for testing TSV substrate noise. The device comprises: a signal applying module, a signal acquiring module, and a noise determining module, wherein:

[0122] a signal applying module, configured to apply a pulse signal to a first excitation TSV and a second excitation TSV; wherein the first excitation TSV and the second excitation TSV are both embedded in the front surface of the test wafer substrate, and the first excitation TSV and the second excitation TSV are electrically connected to form an excitation TSV pair;

[0123] A signal acquisition module, configured to acquire a ground response pulse signal of at least one group of test contact areas formed around the excitation through silicon via;

[0124] The noise determination module is used to determine the through silicon via substrate noise according to the ground response signal of each test contact area.

[0125] The implementation principles of each step in the above-mentioned TSV substrate noise testing device are the same as the principles and logic of each embodiment of the TSV substrate noise testing method, and can be found in the above description, which will not be repeated here.

[0126] In addition, an embodiment of the present application further provides a computer device comprising a memory and a processor, wherein a computer program is stored in the memory. When the computer program is executed by the processor, the processor executes the steps of any of the through silicon via substrate noise testing methods provided in the above embodiments.

[0127] The processor can be regarded as a very large-scale integrated circuit, which includes an arithmetic unit, a controller, a register, a memory, and the like. The processor includes but is not limited to CPU, GPU, FPGA, DSP, and ASIC, etc., and this embodiment of the application does not limit this. Computer equipment refers to any terminal or electronic device that requires an external power supply or a built-in power supply, such as various personal computers, laptops, mobile phones (smart mobile terminals), tablet computers, and portable wearable devices, etc., and this embodiment does not limit this. If it is an external power supply, the power supply can be a power adapter, a mobile power supply (power bank, travel charger), etc., and this embodiment does not limit this.

[0128] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of testing the through-silicon-via substrate noise provided in any of the above embodiments are implemented.

[0129] In some embodiments, based on the above description, those skilled in the art may understand that the present application also provides an electronic device or apparatus, which may include one or more of the above-mentioned boards.

[0130] According to different application scenarios, the computer equipment of the present application may include a server, a cloud server, a server cluster, a data processing device, a robot, a computer, a tablet computer, an intelligent terminal, a PC device, an Internet of Things terminal, a mobile terminal, a mobile phone, a wearable device, a visual terminal, and / or a medical device. The medical device includes a nuclear magnetic resonance device, a B-ultrasound device and / or an electrocardiograph. In the present application, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same location or distributed across multiple network units. In addition, according to actual needs, some or all of the units may be selected to achieve the purpose of the scheme described in the embodiments of the present application. In addition, in some scenarios, multiple units in the embodiments of the present application may be integrated into one unit or each unit may exist physically separately.

[0131] In some implementation scenarios, the above-mentioned integrated unit can be implemented in the form of a software program module. If implemented in the form of a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable memory. Based on this, when the solution of the present application is embodied in the form of a software product (such as a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to enable a computer device (such as a personal computer, a server or a network device, etc.) to perform some or all of the steps of the method described in the embodiment of the present application. The aforementioned memory may include, but is not limited to, various media that can store program code, such as a USB flash drive, a flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0132] In some other implementation scenarios, the above-mentioned integrated unit can also be implemented in the form of hardware, that is, a specific hardware circuit, which may include digital circuits and / or analog circuits, etc. The physical implementation of the hardware structure of the circuit may include but is not limited to physical devices, and the physical devices may include but are not limited to devices such as transistors or memristors. In view of this, the various devices described herein (such as computing devices or other processing devices) can be implemented by appropriate hardware processors, such as CPUs, GPUs, FPGAs, DSPs, and ASICs. Furthermore, the aforementioned storage unit or storage device can be any appropriate storage medium (including magnetic storage media or magneto-optical storage media, etc.), which can be, for example, resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), ROM and RAM, etc.

[0133] Although multiple embodiments of the present application have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Those skilled in the art can conceive of many changes, modifications, and alternatives without departing from the thought and spirit of the present application. It should be understood that in the process of practicing the present application, various alternatives to the embodiments of the present application described herein can be adopted. The accompanying claims are intended to define the scope of protection of the present application and therefore cover equivalents or alternatives within the scope of these claims.

[0134] In the above embodiments, the description of each embodiment has its own emphasis. For parts not described in detail in a particular embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined in any way. To keep the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0135] The embodiments of the present application are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. At the same time, changes or modifications made by those skilled in the art based on the ideas of the present application, the specific implementation methods, and the scope of application of the present application, all fall within the scope of protection of the present application. In summary, the contents of this specification should not be construed as limiting the present application.

Claims

1. A test structure for through silicon via substrate noise, characterized in that: The test structure includes: a first excitation through silicon via, a second excitation through silicon via, at least one set of test contact areas, and at least one through silicon via cluster embedded in the front side of the test wafer substrate; The first excitation through silicon via and the second excitation through silicon via are both embedded in the front surface of the test wafer substrate, and the first excitation through silicon via and the second excitation through silicon via are electrically connected to form an excitation through silicon via pair; each of the test contact areas is around the excitation through silicon via; Each group of test contact areas includes: a front test contact area and / or a back test contact area; the front test contact area is prepared on the front side of the test wafer substrate; the back test contact area is prepared on the back side of the test wafer substrate at a position corresponding to the front test contact area; Any one of the at least one through silicon via cluster comprises at least two parallel through silicon vias; tops of the at least two parallel through silicon vias are connected via a metal extension electrode, and bottoms of the at least two parallel through silicon vias are connected to the backside test contact area via a metal extension electrode; A pulse signal is applied to the pair of stimulated through silicon vias, and a ground response signal of each of the test contact areas is measured to determine the through silicon via substrate noise.

2. The test structure according to claim 1, wherein: The pulse signal is a square wave pulse.

3. The test structure according to claim 1, wherein: The test structure further includes: a grounded through silicon via, wherein the grounded through silicon via is embedded in the front surface of the test wafer substrate and is grounded after penetrating the test wafer substrate.

4. The test structure according to claim 1, wherein: The bottom of the test wafer substrate comprises an insulating layer, and the insulating layer is used to electrically isolate the embedded excitation through silicon via pairs and each of the test contact areas from the test wafer substrate.

5. The test structure according to any one of claims 1 to 4, characterized in that: The tops of the at least two parallel through silicon vias are connected through a metal extension electrode and then connected to the front test contact area through the metal extension electrode.

6. The test structure according to any one of claims 1 to 4, characterized in that: Each of the TSV clusters is prepared at a different position on the front side of the test wafer substrate, and each of the TSV clusters has a different distance from the front side of the test wafer substrate to the excitation TSV pair.

7. The test structure according to claim 6, characterized in that The distances between the positions of the through silicon via clusters on the front side of the test wafer substrate and the exciting through silicon via pairs are gradually increased.

8. The test structure according to any one of claims 1 to 4, characterized in that: The test structure uses the test wafer substrate and the carrier wafer as a base, and the test wafer substrate and the carrier wafer are adhered to each other through a temporary binding adhesive layer.

9. A method for testing through silicon via substrate noise, characterized in that: The method is applied to the test structure according to any one of claims 1 to 8; the method comprises: Applying a pulse signal to a first excitation through-silicon via and a second excitation through-silicon via; wherein the first excitation through-silicon via and the second excitation through-silicon via are both embedded in the front surface of the test wafer substrate, and the first excitation through-silicon via and the second excitation through-silicon via are electrically connected to form an excitation through-silicon via pair; Acquiring a ground response pulse signal of at least one group of test contact areas formed around the excitation through silicon via; The through silicon via substrate noise is determined according to the ground response signal of each test contact area.

10. The testing method according to claim 9, characterized in that: Each set of test contact areas includes: a front test contact area and / or a back test contact area; Then, determining the through silicon via substrate noise according to the ground response signal of each test contact area includes: When the pair of stimulated TSVs passes a square wave pulse, the TSV substrate noise is determined by measuring a ground response signal of the backside test contact region and / or the frontside test contact region.

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