Semiconductor device and layout structure and manufacturing method thereof

Abstract

A semiconductor device and its layout structure and manufacturing method. The layout structure includes: a first transistor, a second transistor and a third transistor integrated on a gallium nitride substrate, and a startup resistor integrated in the gallium nitride substrate; the second transistor is turned on and off at the same time as the first transistor, and a sampling signal is output through the source end of the first transistor; the third transistor controls the on and off of the third transistor through the startup resistor during power-on; wherein the startup resistor is wound in a non-active area in the gallium nitride substrate. By adopting the above scheme, a semiconductor device with current sampling and startup functions can be integrated on a gallium nitride substrate, thereby improving the performance of the semiconductor device with current sampling and startup functions.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its layout structure and a manufacturing method. Background Art

[0002] A semiconductor device with current sampling and startup functions usually includes: a switching transistor, a sampling transistor, a startup transistor and a startup resistor. Among them, the AC voltage can be converted into a DC voltage by controlling the gate voltage of the switching transistor through a control circuit. The gate power supply of the sampling transistor can be controlled by a control circuit to sample the current of the sampling transistor, and then the gate voltage of the startup transistor can be controlled by a startup resistor according to the current sampling result, so as to realize functions such as charging the external capacitor.

[0003] Existing semiconductor devices with current sampling and startup functions are usually integrated on the same substrate. In this case, the startup resistor is wound on the voltage-resistant region of the transistor, and at the same time plays a role in optimizing the surface electric field of the voltage-resistant region.

[0004] However, the semiconductor device with current sampling and startup functions is difficult to integrate on a gallium nitride substrate due to the limitation of the startup resistor itself, and cannot utilize the low characteristic on-resistance and high operating frequency characteristics of gallium nitride itself to improve the performance of the semiconductor device. Summary of the invention

[0005] The problem to be solved by the present invention is: how to integrate a semiconductor device with current sampling and startup functions on a gallium nitride substrate to improve the performance of the semiconductor device with current sampling and startup functions.

[0006] To solve the above problems, an embodiment of the present invention provides a layout structure of a semiconductor device, comprising: a first transistor, a second transistor and a third transistor integrated on the gallium nitride substrate, and a startup resistor integrated in the gallium nitride substrate;

[0007] The drain terminal of the first transistor, the drain terminal of the second transistor and the drain terminal of the third transistor are connected, and the gate terminal of the first transistor and the gate terminal of the second transistor are connected; the second transistor and the first transistor are turned on and off at the same time, and a sampling signal is output through the source terminal of the second transistor;

[0008] One end of the startup resistor is connected to the drain end of the third transistor, and the other end is connected to the gate end of the third transistor; the third transistor is controlled to be turned on and off by the startup resistor during power-on;

[0009] Wherein, the starting resistor is wound in a non-active area within the gallium nitride substrate.

[0010] An embodiment of the present invention further provides a semiconductor device, comprising: a first transistor, a second transistor, a third transistor, a current sampling unit, a startup unit, and a startup resistor; the drain terminal of the first transistor, the drain terminal of the second transistor, and the drain terminal of the third transistor are connected, and the gate terminal of the first transistor and the gate terminal of the second transistor are connected;

[0011] One end of the starting resistor is connected to the drain end of the third transistor, and the other end is connected to the gate end of the third transistor;

[0012] The current sampling unit is connected to the first transistor and the second transistor, and is used to sample the source current of the second transistor and control the on and off of the first transistor according to the sampling result;

[0013] The startup unit is connected to the third transistor and is used to form a negative feedback loop with the startup resistor to control the on and off of the third transistor;

[0014] The semiconductor device includes at least one of the following: a first voltage clamping unit and a second voltage clamping unit: the first voltage clamping unit has one end connected to the drain end of the first transistor and the drain end of the second transistor, and the other end connected to the gate end of the first transistor and the gate end of the second transistor, and is used to clamp the gate terminal voltage of the first transistor and the gate terminal voltage of the second transistor; the second voltage clamping unit has one end connected to the source end of the third transistor, and the other end connected to the gate terminal of the third transistor, and is used to clamp the gate terminal voltage of the third transistor.

[0015] The embodiment of the present invention further provides a method for manufacturing a layout structure, which is used to manufacture the layout structure of the semiconductor device mentioned above, and is characterized in that the method for manufacturing the first layout structure includes:

[0016] Providing the gallium nitride substrate;

[0017] forming the startup resistor in a non-active area within the gallium nitride substrate;

[0018] The first transistor, the second transistor and the third transistor are formed on the gallium nitride substrate.

[0019] An embodiment of the present invention further provides a chip, wherein the chip includes the layout structure of the semiconductor device described above.

[0020] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0021] By applying the solution of the present invention, since the starting resistor is wound in the non-active area in the gallium nitride substrate, and the resistivity of the gallium nitride substrate is much higher than the resistivity of the metal layer on the surface of the gallium nitride substrate, a starting resistor with a high resistance value can be realized, and a semiconductor device with current sampling and starting functions can be integrated on the gallium nitride substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a partial circuit structure diagram of a switching power supply chip;

[0023] Figure 2 is a schematic diagram of a circuit structure of a semiconductor device according to an embodiment of the present invention;

[0024] Figure 3 is a schematic diagram of a first layout structure of a semiconductor device in an embodiment of the present invention;

[0025] Figure 4 is a schematic diagram of a first layout structure of another semiconductor device according to an embodiment of the present invention;

[0026] Figure 5 is a schematic diagram of a first layout structure of another semiconductor device in an embodiment of the present invention;

[0027] Figure 6 is a schematic diagram of a first layout structure of another semiconductor device in an embodiment of the present invention;

[0028] Figure 7 is a schematic diagram of a first layout structure of another semiconductor device in an embodiment of the present invention;

[0029] Figure 8 is a schematic diagram of a first layout structure of another semiconductor device according to an embodiment of the present invention;

[0030] Fig. 9 yes Figure 3 A magnified schematic diagram of the local structure of the middle W region;

[0031] Fig.10 yes Fig. 9 The schematic cross-sectional view along line BB';

[0032] Fig.11 yes Figure 3 Schematic diagram of the cross section along line AA'. DETAILED DESCRIPTION

[0033] Figure 1 It is a common semiconductor device with current sampling and starting functions.

[0034] Reference Figure 1A local circuit structure of a switching power supply chip includes: a switching transistor M1, a sampling transistor M2, a start transistor M3, a start resistor R1 and a sampling resistor R2. Among them, SW is a high voltage terminal. GATE is a drive signal output terminal. SOUCE is a source terminal of the first transistor M1. SENSE is a source terminal of the sampling transistor M2, connected to the sampling resistor R2 and then to the ground, and at the same time input to the control circuit 103 as a sampling signal. The control circuit 103 includes a start circuit 101 and a pulse width modulation circuit 102.

[0035] During the power-on process, the gate voltage of the start transistor M3 slowly increases. When the voltage difference between the gate voltage and the source voltage of the start transistor M3 is greater than its threshold voltage, the start transistor M3 is turned on and charges the external capacitor through the start circuit 101. At the same time, the components in the start circuit 101 and the start resistor R1 form a negative feedback loop to control the gate voltage of the drive transistor M3, thereby stabilizing the charging current of the start transistor M3 to the outside world and avoiding the influence of the change of the drain voltage due to the change of the voltage on the external capacitor. The pulse width modulation circuit 102 can receive the sampling signal and generate a corresponding drive signal based on the sampling signal to control the on and off of the switch transistor M1 and the sampling transistor M2.

[0036] Figure 1 In the conventional circuit structure shown, when making a layout, the transistor and the start-up resistor are usually integrated on the same substrate, and the control circuit 103 is integrated on another layout. The start-up resistor is wound above the voltage-resistant region of the transistor, and at the same time plays a role in optimizing the surface electric field of the voltage-resistant region.

[0037] Gallium nitride semiconductor devices are semiconductor devices implemented on gallium nitride substrates. Since gallium nitride materials themselves have the characteristics of low characteristic on-resistance and high operating frequency, semiconductor devices implemented on gallium nitride substrates can significantly improve power conversion efficiency compared to silicon-based semiconductor devices.

[0038] However, when the layout is made in the traditional way, it is difficult to form high resistance above the substrate and the voltage-resistant area because the existing gallium nitride process lacks high-resistance materials on the substrate surface that are compatible with the process. At the same time, the traditional transistor layout structure cannot be adapted to the gallium nitride substrate.

[0039] Therefore, how to provide a layout structure of a gallium nitride semiconductor device with current sampling and start-up functions has become an urgent problem to be solved.

[0040] To solve this problem, the present invention provides a layout structure of a semiconductor device, in which a startup resistor is wound in a non-active area within a gallium nitride substrate, rather than formed on the surface of the gallium nitride substrate. Since the resistivity of the gallium nitride substrate is much higher than the resistivity of the metal layer on the surface of the gallium nitride substrate, the resistivity requirement of the startup resistor can be met, thereby realizing a semiconductor device with current sampling and startup functions formed on the gallium nitride substrate.

[0041] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0042] Figure 2 A circuit diagram of a semiconductor device provided by an embodiment of the present invention. Figure 2 The device may include: a first transistor T1, a second transistor T2, a third transistor T3, a current sampling unit 21, a starting unit 22 and a starting resistor R1.

[0043] The drain terminal of the first transistor T1, the drain terminal of the second transistor T2 and the drain terminal of the third transistor T3 are connected, and the gate terminal of the first transistor T1 and the gate terminal of the second transistor T2 are connected;

[0044] One end of the starting resistor R1 is connected to the drain end of the third transistor T3, and the other end is connected to the gate end of the third transistor T3;

[0045] The current sampling unit 21 is connected to the first transistor T1 and the second transistor T2, and is used to sample the source current of the second transistor T2, and control the on and off of the first transistor T1 according to the sampling result;

[0046] The start-up unit 22 is connected to the third transistor T3 and is used to form a negative feedback loop with the start-up resistor R1 to control the on-off of the third transistor T3.

[0047] The high voltage terminal SW is connected to the drain terminals of the first transistor T1, the second transistor T2 and the third transistor T3. The source terminal of the first transistor T1 is grounded. The first transistor T1 and the second transistor T2 are turned on and off at the same time.

[0048] The current sampling unit 21 includes: a sampling resistor R2 and a sampling circuit 211. The source terminal of the second transistor T2 is grounded through the sampling resistor R2, and outputs a sampling signal to the sampling circuit 211. The semiconductor device may also include: a driving unit 23. The driving unit 23 is connected to the gate terminals of the first transistor T1 and the second transistor T2 to output a corresponding driving signal according to the sampling result.

[0049] The third transistor T3 is controlled to be turned on and off by the start-up resistor R1 during the power-on period. Specifically, during the power-on process of the high-voltage terminal SW, the gate voltage of the third transistor T3 slowly increases, and after the third transistor T3 is turned on, it charges the control circuit through the start-up unit 22. At the same time, the start-up unit 22 forms a negative feedback loop through the start-up resistor R1 to control the gate voltage of the third transistor T3 to stabilize the charging current. After the startup is completed, the start-up unit 22 will reduce the gate voltage of the third transistor T3, thereby turning off the transistor and reducing system power consumption.

[0050] In the semiconductor device, the gate terminals of the first transistor T1 and the second transistor T2 are connected, so they can be turned on or off at the same time, which is beneficial to improving the sampling accuracy. In addition, the circuit structure has a small area, which is beneficial to reducing the circuit cost and is widely used in switching power supplies. In addition, since the semiconductor device has both the current sampling unit 21 and the start-up unit 22, the current sampling and start-up functions can be realized at the same time.

[0051] In an embodiment of the present invention, the semiconductor device may further include at least one of the following: a first voltage clamping unit 24 and a second voltage clamping unit 25. Wherein:

[0052] The first voltage clamping unit 24 has one end connected to the drain of the first transistor T1 and the drain of the second transistor T2, and the other end connected to the gate of the first transistor T1 and the gate of the second transistor T2, and is used to clamp the gate voltage of the first transistor T1 and the gate voltage of the second transistor T2.

[0053] The second voltage clamping unit 25 has one end connected to the source end of the third transistor T3 and the other end connected to the gate end of the third transistor T3, and is used to clamp the gate end voltage of the third transistor T3.

[0054] By providing the first voltage clamping unit 24 and the second voltage clamping unit 25 , the gate terminal voltages of the first transistor T1 to the third transistor T3 can be clamped after reaching the driving voltage, thereby protecting the transistor gates from breakdown and improving the reliability of the semiconductor device.

[0055] It should be noted that the semiconductor device may be provided with only one voltage clamping unit 24, or only the second voltage clamping unit 25, or both the first voltage clamping unit 24 and the second voltage clamping unit 25. It is understandable that when only one voltage clamping unit is provided, the reliability of the semiconductor device can still be improved to a certain extent.

[0056] In a specific implementation, the transistor and the start-up resistor of the semiconductor device can be integrated on a transistor chip, and the control units of the semiconductor device can be integrated on a control chip. The transistor chip has a first layout structure, and the control signal has a second layout structure. Therefore, the layout structure of the semiconductor device provided in an embodiment of the present invention includes the first layout structure. In some embodiments, the layout structure of the semiconductor device may also include a second layout structure. The first layout structure is described in detail below:

[0057] In a specific implementation, the first layout structure includes: a first transistor, a second transistor, and a third transistor integrated on the gallium nitride substrate, and a startup resistor integrated in the gallium nitride substrate.

[0058] The drain terminal of the first transistor, the drain terminal of the second transistor and the drain terminal of the third transistor are connected, and the gate terminal of the first transistor and the gate terminal of the second transistor are connected; the second transistor and the first transistor are turned on and off at the same time, and a sampling signal is output through the source terminal of the first transistor;

[0059] One end of the startup resistor is connected to the drain end of the third transistor, and the other end is connected to the gate end of the third transistor; the third transistor is controlled to be turned on and off by the startup resistor during power-on;

[0060] Wherein, the starting resistor is wound in a non-active area within the gallium nitride substrate.

[0061] Since the resistivity of the gallium nitride substrate is much higher than the resistivity of the metal layer on the surface of the gallium nitride substrate, when the startup resistor is set in the gallium nitride substrate, the requirements for the resistivity of the startup resistor can be met, and a startup resistor with a high resistance value can be realized, thereby realizing the formation of a semiconductor device with current sampling and startup functions on the gallium nitride substrate.

[0062] In a specific implementation, the distribution of the first transistor, the second transistor, the third transistor and the start-up resistor on the first layout structure is not limited, as long as the three transistors maintain the above-mentioned electrical connection relationship.

[0063] In one embodiment, referring to Figure 3 , along the X direction, the first transistor to the third transistor can be arranged in sequence. It should be noted that Figure 3 , only the third transistor T3 and the source terminal 332 of the second transistor are identified. The second transistor shares a gate terminal and a drain terminal with the first transistor, so except for the third transistor T3, the drain terminal of the second transistor is the same as the drain terminal of the second transistor, and the gate terminal of the second transistor is the same as the gate terminal of the second transistor. Except for the source terminal of the third transistor T3 and the source terminal 332 of the second transistor, the remaining source terminals are all source terminals of the first transistor.

[0064] like Figure 3 As shown, the drain terminal of the first transistor, the drain terminal of the second transistor and the drain terminal of the third transistor T3 are all connected to the drain terminal welding area 31. The gate terminal of the first transistor and the gate terminal 322 of the second transistor are all connected to the first gate terminal welding area 32a. The gate terminal of the third transistor is connected to the second gate terminal welding area 32b. The source terminal of the first transistor is connected to the first source terminal welding area 33a, the source terminal 332 of the second transistor is connected to the second source terminal welding area 33b, and the source terminal of the third transistor T3 is connected to the third source terminal welding area 33c. A cut-off ring 34 is provided on the periphery of the first layout structure for grounding the corresponding port to prevent the accumulated charge from damaging the transistor in the cut-off ring 34 and to protect the transistor in the cut-off ring 34.

[0065] Among them, the drain terminal welding area, the gate terminal welding area and the source terminal welding area are called the metal welding area of ​​the layout structure, that is, pad, which is used to realize the external connection of the corresponding port. Specifically, the drain terminal welding area 31 is used to realize the external connection of the source terminal of the transistor. The first gate terminal welding area 32a and the second gate terminal welding area 32b are used to realize the external connection of the gate terminal of the transistor. The first source terminal welding area 33a, the second source terminal welding area 33b and the third source terminal welding area 33c are used to realize the external connection of the source terminal of the transistor.

[0066] In another embodiment of the present invention, referring to Figure 4 , along the X direction, the second transistor, the first transistor and the third transistor T3 are arranged in sequence. At this time, the second transistor and the third transistor T3 are distributed on the left and right sides of the first transistor, and accordingly, the first gate terminal welding area 32a and the second source terminal welding area 33b also change accordingly. The connection relationship between the second transistor, the first transistor and the third transistor T3 is as described above. Figure 3 The description is not repeated here.

[0067] In another embodiment of the present invention, referring to Figure 5 , the second transistor and the third transistor T3 can be distributed along the Y direction, that is, distributed up and down. The connection relationship between the second transistor, the first transistor and the third transistor T3 refers to the above Figure 3 The description is not repeated here.

[0068] In a specific implementation, the active region of the transistor includes the drain terminal and the source terminal of the transistor. The active region of the transistor is located on the substrate. The region between the transistors is the inactive region, and the inactive region between the transistors is located in the substrate.

[0069] The source terminals of the second transistor and the third transistor can be located at any position in the active area, and the positions of the corresponding source terminal welding areas will also change accordingly. Figure 3The second source terminal welding area 33b and the third source terminal welding area 33c are located on the same side of the first source terminal welding area 33a. Figure 4 The second source terminal welding area 33b and the third source terminal welding area 33c are located on both sides of the first source terminal welding area 33a.

[0070] In a specific implementation, the starting resistor is wound in the non-active area in the gallium nitride substrate. The position of the non-active area in the gallium nitride substrate is not limited, as long as it is wound in the non-active area in the gallium nitride substrate.

[0071] In one embodiment of the present invention, the non-active region in the gallium nitride substrate may include a non-active region near the transistor region in the gallium nitride substrate, that is, a non-active region in the gallium nitride substrate, in the region surrounded by the cutoff ring, excluding the non-active region below the metal welding region. The non-active region near the transistor region includes both the non-active region between transistors and the non-active region outside the transistor region and within the cutoff ring.

[0072] For example, refer to Figures 3 to 5 The start-up resistor 35 is completely wound in the non-active area near the transistor area. One end of the start-up resistor 35 is connected to the drain terminal 313 of the third transistor, and the other end is connected to the gate terminal 323 of the third transistor.

[0073] In another embodiment of the present invention, the non-active area in the gallium nitride substrate may include a non-active area below the metal welding area, wherein the metal welding area may be at least one of a drain terminal welding area, a gate terminal welding area, and a source terminal welding area, which is not limited here. Since the non-active area below the metal welding area in the substrate itself is part of the first layout structure and does not occupy additional area, when the start-up resistor is wound in the non-active area below the metal welding area, no additional area is required to form the start-up resistor, which effectively reduces the area of ​​the first layout structure and reduces the cost.

[0074] by Figure 4 For example, refer to the distribution of transistors in Figure 6 The startup resistor 35 can be completely wound in the non-active area below the first source terminal welding area 33a. At this time, the startup resistor 35 can be connected to the drain terminal of the first transistor, and the other end is connected to the third source terminal welding area 33c, and then connected to the source terminal of the third transistor.

[0075] In another embodiment of the present invention, the non-active area in the gallium nitride substrate may include both the non-active area near the transistor area and the non-active area below the metal welding area. Since a portion of the start-up resistor is wound in the non-active area below the metal welding area, compared with winding the start-up resistor entirely in the non-active area near the transistor area, the area of ​​the first layout structure is reduced to a certain extent, thereby reducing the cost.

[0076] by Figure 3 For example, refer to the distribution of transistors in Figure 7 The start-up resistor 35 can be partially wound in the non-active area below the drain terminal welding area 31, and the other part can be wound below the first gate terminal welding area 32a and the second gate terminal welding area 32b, the first source terminal welding area 33a, the second source terminal welding area 33b and the third source terminal welding area 33c. The two parts are connected through the non-active area near the transistor area.

[0077] by Figure 4 For example, refer to the distribution of transistors in Figure 8 The start-up resistor 35 can be wound in the non-active area near the transistor area and the non-active area below the metal welding area.

[0078] In a specific implementation, since there is a metal layer on the surface of the gallium nitride substrate, when a transistor active region is formed on the gallium nitride substrate, a non-rectifying contact, ie, an ohmic contact, is formed when the semiconductor material forming the active region contacts the surface metal layer.

[0079] In one embodiment of the present invention, the ohmic contact of the drain terminal of the third transistor is disconnected from the ohmic contact of the drain terminal of the first transistor to form an ohmic contact disconnection area; the drain terminal of the third transistor is connected to the drain terminal of the first transistor through surface metal; the gate terminal of the first transistor is connected to the gate terminal of the second transistor through the ohmic contact disconnection area.

[0080] by Figure 3 Taking the distribution of transistors in as an example, Fig. 9 for Figure 3 A partial enlarged view of the middle W area. Fig. 9 The ohmic contact 313a of the drain terminal of the third transistor is disconnected from the ohmic contact 311a of the drain terminal of the first transistor to form an ohmic contact disconnection region. The drain terminal 313 of the third transistor is connected to the drain terminal 311 of the first transistor through the surface metal layer s1; the gate terminal 321 of the first transistor is connected to the gate terminal 322 of the second transistor through the ohmic contact disconnection region.

[0081] Since the gate terminal 321 of the first transistor is connected to the gate terminal 322 of the second transistor, the first transistor and the second transistor can be turned on or off at the same time, thereby improving the sampling accuracy.

[0082] Fig.10 for Fig. 9 Schematic diagram of the cross section along line BB'. Fig.10The gallium nitride substrate may include: a second substrate layer 110, a second substrate layer 120 and a third substrate layer 130. The second substrate layer 120 is located above the second substrate layer 110, the third substrate layer 130 is located above the second substrate layer 120, and the third substrate layer 130 is provided with first to third transistors.

[0083] In a specific implementation, the material of the first substrate layer can be silicon, sapphire or silicon carbide, etc., or can be gallium nitride (GaN). The material of the second substrate layer 120 can be gallium nitride, and the material of the third substrate layer 130 can be aluminum gallium nitride (AlGaN).

[0084] The second substrate layer 120 is a high resistance layer of the gallium nitride substrate. The interface between the second substrate layer 120 and the third substrate layer 130 is called a two-dimensional electron gas layer. The two-dimensional electron gas layer is not only conductive, but also close to the high resistance layer of the gallium nitride substrate, which can meet the resistivity requirements of the start-up resistor. Therefore, the start-up resistor is usually set at the interface between the second substrate layer 120 and the third substrate layer 130 (such as Fig.11 As shown in FIG. 1 , the starting resistor is used to meet the use requirements of the starting resistor. The starting resistor, also called the two-dimensional electron gas resistor or the epitaxial resistor, can not only drive the gate terminal of the third transistor, but also the resistivity can basically meet the requirements.

[0085] The use of an epitaxial resistor as a startup resistor can be realized without an additional process flow, thereby effectively simplifying the process. Of course, in other embodiments, the startup resistor may also be other resistors, which are not limited here.

[0086] In the specific implementation, refer to Fig. 9 and Fig.10 The non-active region 140 between the transistors can be used as an isolation structure between the transistors to prevent the potential and current from interfering with each other, so as to electrically isolate the transistors and the transistors from the start-up resistor. The non-active region can be formed between the transistors by ion implantation into the gallium nitride substrate. The injected ions are not limited as long as they can play an isolation role, such as fluorine ions. The depth of the isolation structure can be set according to actual needs. For example, the depth of the isolation structure can be greater than the thickness of the third substrate layer, but less than the sum of the thickness of the second substrate layer and the third substrate layer.

[0087] In a specific implementation, the starting resistor may be spiral-shaped and distributed in the same plane, such as Figure 8 Of course, it can also be in other shapes, which are not limited here.

[0088] In a specific implementation, the resistivity of the start-up resistor is related to the winding width and the composition of the metal aluminum in the gallium nitride substrate. The composition of the metal aluminum in the gallium nitride substrate is the composition of the metal aluminum in the third substrate layer. At the same time, the substrate aluminum composition and the winding width can be changed to meet different requirements of the start-up resistor and transistor characteristics. Taking the spiral distribution of the resistor as an example, the winding width of the resistor can be proportional to the number of turns.

[0089] In one embodiment of the present invention, in a specific implementation, the size of the second transistor can be set to be smaller than the size of the first transistor, so that when sampling the second transistor, the sampling current value is smaller, but a larger driving current can be output to the first transistor through the current sampling unit, and sampling a smaller current can reduce system losses.

[0090] In a specific implementation, the size of the third transistor can be set to be smaller than the size of the first transistor. As a startup transistor, the third transistor only needs a current capacity sufficient to start the control chip in a short time, and does not need a large-size transistor.

[0091] In a specific implementation, at least one of the first transistor, the second transistor, and the third transistor may be an enhanced lateral high-voltage transistor. Preferably, the first transistor, the second transistor, and the third transistor are all enhanced lateral high-voltage transistors. Since the enhanced lateral high-voltage transistor has the characteristic of gate positive voltage drive, the first transistor, the second transistor, and the third transistor are set as enhanced lateral high-voltage transistors, which can simplify the first layout structure without the need for an additional common source and common gate (cascode) structure.

[0092] In a specific implementation, the current sampling unit and the startup unit can be integrated on a control chip, and the chip has a second layout structure. In the second layout structure, the specific layout structure of the current sampling unit and the startup unit is not limited, and those skilled in the art can set it according to actual conditions.

[0093] In an embodiment of the present invention, the transistor chip may further include at least one of the following: a first voltage clamping unit and a second voltage clamping unit.

[0094] The first voltage clamping unit has one end connected to the drain end of the first transistor and the drain end of the second transistor, and the other end connected to the gate end of the first transistor and the gate end of the second transistor, and is used to clamp the gate end voltage of the first transistor and the gate end voltage of the second transistor;

[0095] The second voltage clamping unit has one end connected to the source end of the third transistor and the other end connected to the gate end of the third transistor, and is used to clamp the gate end voltage of the third transistor.

[0096] In a specific implementation, the first voltage clamping unit and the second voltage clamping unit may both belong to the first layout structure, that is, integrated on a gallium nitride substrate. Integration on a gallium nitride substrate can reduce the complexity of the control circuit and improve the clamping effect.

[0097] In other embodiments, the first voltage clamping unit and the second voltage clamping unit may also be located on the control chip, that is, integrated on a substrate corresponding to the control chip, which is not limited here.

[0098] As can be seen from the above content, the layout structure in the embodiment of the present invention has both current sampling and startup functions and is easy to implement. Compared with silicon-based semiconductor devices, semiconductor devices implemented on gallium nitride substrates can effectively improve power conversion efficiency. In addition, when the startup resistor is partially or completely set in the non-active area below the welding area, the cost can be effectively reduced.

[0099] In order to enable those skilled in the art to better understand and implement the present invention, the manufacturing method and chip corresponding to the above layout are described in detail below.

[0100] An embodiment of the present invention provides a method for manufacturing a layout structure, and the method can be used to manufacture any of the above-mentioned layout structures of semiconductor devices. Specifically, the method for manufacturing the first layout structure includes:

[0101] Step A1, providing the gallium nitride substrate.

[0102] In the specific implementation, refer to Fig.10 , the gallium nitride substrate may include: a first substrate layer 110, a second substrate layer 120 and a third substrate layer 130. The material of the first substrate layer 110 may be silicon, sapphire or silicon carbide, etc., or may be gallium nitride (GaN). The material of the second substrate layer 120 may be gallium nitride, and the material of the third substrate layer 130 may be aluminum gallium nitride (AlGaN).

[0103] The interface between the second substrate layer 120 and the third substrate layer 130 is called a two-dimensional electron gas layer, which is not only conductive but also has a high resistivity, and can basically meet the resistivity requirement of the starting resistor.

[0104] In other embodiments, the gallium nitride substrate may also have other structures as long as it contains gallium nitride.

[0105] Step A2: forming the startup resistor in the inactive area of ​​the gallium nitride substrate.

[0106] In a specific implementation, a startup resistor can be formed while forming an inactive region in the gallium nitride substrate. After the startup resistor is formed, the inactive region between the transistors is used as an isolation structure between the transistors. Under the isolation effect of the isolation structure, the startup resistor is wound to form multiple turns, and the isolation structure fills the gaps between adjacent turns.

[0107] by Figure 3 For example, take the position of the starting resistor along Figure 3 The cross-sectional diagram of the AA' line is shown in Fig.11 See Fig.11 , the AA' line sequentially passes through the drain terminal 311 of the first transistor and the gate terminal 321 of the first transistor, and extends to the startup resistor 35. The startup resistor 35 is completely wound in the non-active area near the transistor area. After the startup resistor and the non-active area are formed at the same time, except for the non-active area occupied by the startup resistor, the non-active area between the remaining transistors serves as an isolation structure 140 between the transistors. The isolation structure 140 fills the gaps between adjacent turns of the startup resistor 35, and the gaps between the startup resistor 35 and the transistor.

[0108] Step A3: forming the first transistor, the second transistor and the third transistor on the gallium nitride substrate.

[0109] After forming the inactive region and the start-up resistor in the gallium nitride substrate, the first transistor, the second transistor and the third transistor are formed on the gallium nitride substrate. Fig.11 , a drain terminal 311 and a gate terminal 321 of the first transistor are formed on the gallium nitride substrate.

[0110] By adopting the solution of the present invention, the starting resistor is formed by winding in the non-active area of ​​the gallium nitride substrate, so that the first layout structure can be integrated on the gallium nitride substrate, thereby utilizing the characteristics of gallium nitride itself to improve the power conversion efficiency of the semiconductor device and improve the performance of the semiconductor device.

[0111] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A layout structure of a semiconductor device, characterized in that include: A first transistor, a second transistor and a third transistor integrated on a gallium nitride substrate, and a startup resistor integrated in the gallium nitride substrate; The startup resistor is used to control the gate voltage of the third transistor when the power-on device is powered on; The drain terminal of the first transistor, the drain terminal of the second transistor and the drain terminal of the third transistor are connected, and the gate terminal of the first transistor and the gate terminal of the second transistor are connected; the second transistor and the first transistor are turned on and off at the same time, and a sampling signal is output through the source terminal of the second transistor; One end of the startup resistor is connected to the drain end of the third transistor, and the other end is connected to the gate end of the third transistor; the third transistor is controlled to be turned on and off by the startup resistor during power-on; The starting resistor is wound in a non-active area in the gallium nitride substrate; the non-active area in the gallium nitride substrate includes at least one of the following: a non-active area in the gallium nitride substrate near a transistor area; a non-active area in the gallium nitride substrate below a metal welding area.

2. The layout structure according to claim 1, characterized in that: The gallium nitride substrate includes: a first substrate layer, a second substrate layer located above the first substrate layer, and a third substrate layer located above the second substrate layer, wherein the first transistor, the second transistor and the third transistor are arranged above the third substrate layer; and the start-up resistor is located at an interface between the second substrate layer and the third substrate layer.

3. The layout structure according to claim 1, characterized in that: The resistivity of the starting resistor is related to the winding width and the composition of the metal aluminum in the gallium nitride substrate.

4. The layout structure according to claim 1, characterized in that: An isolation structure is provided between the first transistor, the second transistor, the third transistor and the start-up resistor.

5. The layout structure according to claim 1, characterized in that: The ohmic contact at the drain terminal of the third transistor is disconnected from the ohmic contact at the drain terminal of the first transistor to form an ohmic contact disconnection region; The drain terminal of the third transistor is connected to the drain terminal of the first transistor through surface metal; the gate terminal of the first transistor is connected to the gate terminal of the second transistor through the ohmic contact disconnection area.

6. The layout structure according to claim 1, characterized in that: The starting resistors are distributed in a spiral shape.

7. The layout structure according to any one of claims 1 to 6, characterized in that: The layout structure further includes at least one of the following: a first voltage clamping unit and a second voltage clamping unit; The first voltage clamping unit has one end connected to the drain end of the first transistor and the drain end of the second transistor, and the other end connected to the gate end of the first transistor and the gate end of the second transistor, and is used to clamp the gate end voltage of the first transistor and the gate end voltage of the second transistor; The second voltage clamping unit has one end connected to the source end of the third transistor and the other end connected to the gate end of the third transistor, and is used to clamp the gate end voltage of the third transistor.

8. The layout structure according to any one of claims 1 to 6, characterized in that: The first transistor, the second transistor and the third transistor are enhancement type lateral high voltage transistors.

9. The layout structure according to any one of claims 1 to 6, characterized in that: The sizes of the second transistor and the third transistor are smaller than the size of the first transistor.

10. A semiconductor device, characterized in that: include: A first transistor, a second transistor, a third transistor, a current sampling unit, a startup unit and a startup resistor; the drain end of the first transistor, the drain end of the second transistor and the drain end of the third transistor are connected, and the gate end of the first transistor and the gate end of the second transistor are connected; One end of the starting resistor is connected to the drain end of the third transistor, and the other end is connected to the gate end of the third transistor; The current sampling unit is connected to the first transistor and the second transistor, and is used to sample the source current of the second transistor and control the on and off of the first transistor according to the sampling result; The startup unit is connected to the third transistor and is used to form a negative feedback loop with the startup resistor to control the on and off of the third transistor; The semiconductor device includes at least one of the following: a first voltage clamping unit and a second voltage clamping unit: the first voltage clamping unit has one end connected to the drain end of the first transistor and the drain end of the second transistor, and the other end connected to the gate end of the first transistor and the gate end of the second transistor, and is used to clamp the gate end voltage of the first transistor and the gate end voltage of the second transistor; The second voltage clamping unit has one end connected to the source end of the third transistor and the other end connected to the gate end of the third transistor, and is used to clamp the gate end voltage of the third transistor.

11. A method for manufacturing a layout structure, used for manufacturing a layout structure of a semiconductor device according to any one of claims 1 to 9, characterized in that: The method for making the layout structure comprises: Providing the gallium nitride substrate; forming the startup resistor in a non-active area within the gallium nitride substrate; The first transistor, the second transistor and the third transistor are formed on the gallium nitride substrate.

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