Array substrate, display panel and display device

Abstract

The present application relates to an array substrate, a display panel and a display device, wherein the array substrate comprises a first functional layer, a second functional layer and an insulating layer insulated between the first functional layer and the second functional layer, the array substrate has a plurality of transistors and a plurality of capacitors, each capacitor is electrically connected to at least one transistor, and the capacitor comprises a first electrode plate and a second electrode plate, the first electrode plate is formed on the first functional layer and is arranged in the same layer as at least part of the transistor, and the second electrode plate is formed on the second functional layer and is arranged in the same layer as at least part of the transistor; wherein the thickness of the insulating layer in the region between the first electrode plate and the second electrode plate is less than the thickness of the insulating layer in the region of the transistor. The array substrate provided in the embodiment of the present application has a capacitor that can meet the capacitance requirements of the capacitor, and the manufacturing process is simple and the cost is low.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] In the prior art, an array substrate usually includes a plurality of transistors and capacitors. Generally, for MicroLED, its light-emitting elements are controlled by transistors and capacitors. The pixel circuit for driving the light-emitting elements usually includes a switching transistor, a driving transistor and a capacitor. When the array substrate is working, the capacitor is mainly used for energy storage. When the switching transistor is selected by the scan signal line (Scan line) signal, the data voltage on the data signal line (Data line) is transmitted to the gate of the driving transistor, and the capacitor is charged at the same time. When the scan signal does not select the switching transistor, the switching transistor is cut off, and the voltage stored in the capacitor will be used to drive the transistor to ensure the brightness of the light-emitting element.

[0003] In order to ensure the capacitance requirements of the capacitor, existing array substrates usually add a metal layer for forming the capacitor plates between the layer structures of the formed transistors. Although this setting method can meet the capacitance requirements of the capacitor, the addition of the metal layer for forming the capacitor plates increases the production process of the array substrate, thereby increasing the cost of the array substrate.

[0004] Therefore, a new array substrate, display panel and display device are urgently needed. Summary of the invention

[0005] The embodiments of the present application provide an array substrate, a display panel, and a display device. The capacitors of the array substrate can meet the capacitance requirements of the capacitors, and the manufacturing process is simple and the cost is low.

[0006] On the one hand, according to an embodiment of the present application, an array substrate is proposed, including a first functional layer, a second functional layer, and an insulating layer insulated between the first functional layer and the second functional layer, the array substrate has multiple transistors and multiple capacitors, each capacitor is electrically connected to at least one transistor, the capacitor includes a first electrode plate and a second electrode plate, the first electrode plate is formed on the first functional layer and is arranged in the same layer as at least part of the transistor, the second electrode plate is formed on the second functional layer and is arranged in the same layer as at least part of the transistor; wherein the thickness of the insulating layer in the area between the first electrode plate and the second electrode plate is less than the thickness of the insulating layer in the transistor area.

[0007] On the other hand, according to an embodiment of the present application, a display panel is provided, comprising: the above-mentioned array substrate; a light-emitting layer stacked on the array substrate, the light-emitting layer comprising a plurality of light-emitting elements, each light-emitting element being electrically connected to at least one transistor.

[0008] In yet another aspect, a display device is provided according to an embodiment of the present application, comprising the above-mentioned display panel.

[0009] The array substrate, display panel and display device provided by the embodiments of the present application, the array substrate includes a first functional layer, a second functional layer and an insulating layer insulated between the first functional layer and the second functional layer, the array substrate has a plurality of transistors and a plurality of capacitors, each capacitor is electrically connected to at least one transistor, the capacitor includes a first electrode plate and a second electrode plate, since the first electrode plate is formed in the first functional layer and is arranged in the same layer as at least part of the transistor, the second electrode plate is formed in the second functional layer and is arranged in the same layer as at least part of the transistor. In other words, the first electrode plate and the second electrode plate of the capacitor are both arranged in the same layer as the corresponding layer structure of the transistor, and there is no need to add an additional metal layer to form the electrode plate of the capacitor separately, so that the overall manufacturing process of the array substrate is simple and the cost is low.

[0010] Furthermore, by making the thickness of the insulating layer in the area between the first electrode plate and the second electrode plate smaller than the thickness of the insulating layer in the transistor area, the distance between the first electrode plate and the second electrode plate is reduced to increase the capacitance between the first electrode plate and the second electrode plate. At the same time, the thickness of the insulating layer in the transistor area is increased, which can not only simplify the process but also avoid mutual influence between different layer structures of the transistor, thereby ensuring the performance of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The features, advantages and technical effects of exemplary embodiments of the present application will be described below with reference to the accompanying drawings.

[0012] Figure 1 is a schematic diagram of a pixel circuit in the prior art;

[0013] Figure 2 is a cross-sectional view of an array substrate according to an embodiment of the present application;

[0014] Figure 3 is a schematic diagram of a pixel circuit of an embodiment of the present application;

[0015] Figure 4 is a cross-sectional view of an array substrate according to another embodiment of the present application;

[0016] Figure 5 is a cross-sectional view of an array substrate according to yet another embodiment of the present application;

[0017] Figure 6 is a cross-sectional view of an array substrate according to yet another embodiment of the present application;

[0018] Figure 7 is a cross-sectional view of an array substrate according to yet another embodiment of the present application;

[0019] Figure 8 is a cross-sectional view of an array substrate according to yet another embodiment of the present application;

[0020] Fig. 9 is a top view of a display panel according to an embodiment of the present application;

[0021] Fig.10 yes Fig. 9 The cross-sectional view along the AA direction;

[0022] Fig.11 FIG. 4 is a partial cross-sectional view of a display panel according to another embodiment of the present application.

[0023] in:

[0024] 100-array substrate;

[0025] 10-first functional layer; 20-second functional layer; 30-insulating layer; 31-groove; 40-inorganic film layer; 50-third functional layer; 60-planarization layer;

[0026] 110 - transistor; 111 - active region; 112 - gate; 113 - source; 114 - drain;

[0027] 120 - capacitor; 121 - first electrode plate; 122 - second electrode plate;

[0028] 200 - light-emitting layer; 210 - light-emitting element; X - thickness direction.

[0029] In the drawings, the same reference numerals are used for the same components. The drawings are not drawn to scale. DETAILED DESCRIPTION

[0030] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0031] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0032] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0033] In the related art, the array substrate of the display panel usually includes a plurality of pixel circuits, each of which is used to drive at least one light-emitting element to ensure the light-emitting requirements. In the prior art, the array substrate usually includes a plurality of transistors and capacitors. Generally, for Micro LED, its light-emitting elements are controlled by transistors and capacitors.

[0034] like Figure 1 As shown, Figure 1 is a schematic diagram of a pixel circuit in the prior art.

[0035] Figure 1 It is a relatively simple pixel circuit. The array substrate includes multiple driving circuits. Each pixel driver is used to drive a light-emitting element. The pixel circuit includes at least two transistors, a switching transistor T2, a driving transistor T1 and a capacitor Cst. When the array substrate 100 is working, the capacitor Cst is mainly used for energy storage. When the switching transistor T2 is selected by the scan signal line (Scan line) signal, the data voltage Vdata on the data signal line (Data line) is transmitted to the gate of the driving transistor Data, and the capacitor Cst is charged at the same time. When the scan signal does not select the switching transistor T2, the switching transistor T2 is turned off, and the voltage stored in the capacitor T2 will be used to drive the transistor T1 to ensure the brightness of the light-emitting element 210.

[0036] A transistor usually includes an active region, a gate, a source electrode, and a drain electrode. The source electrode and the drain electrode are arranged in the same layer, and the active region, the gate electrode, and the source electrode are arranged in layers. In order to meet the capacitance requirements of the capacitor, the existing array substrate usually adds a metal layer for forming the electrode plate of the capacitor between the layer structures of the formed transistor. For example, a metal layer is formed between the layer structures for forming the gate electrode and the layer structures for forming the source electrode and the drain electrode to form one of the electrode plates of the capacitor. Although this arrangement can meet the capacitance requirements of the capacitor, the addition of a metal layer for forming the capacitor electrode plate increases the production process of the array substrate, thereby increasing the cost of the array substrate.

[0037] In order to solve the above technical problems, the embodiment of the present application provides a new array substrate, the capacitors of the array substrate can meet the capacitance requirements of the capacitors, and the manufacturing process is simple and the cost is low.

[0038] like Figure 2 As shown, Figure 2 : is a cross-sectional view of an array substrate of an embodiment of the present application. The array substrate 100 provided in the embodiment of the present application includes a first functional layer 10, a second functional layer 20, and an insulating layer 30 insulated between the first functional layer 10 and the second functional layer 20. The array substrate 100 has a plurality of transistors 110 and a plurality of capacitors 120, each capacitor 120 is electrically connected to at least one transistor 110, and the capacitor 120 includes a first electrode plate 121 and a second electrode plate 122. The first electrode plate 121 is formed on the first functional layer 10 and is disposed in the same layer as at least part of the transistor 110, and the second electrode plate 122 is formed on the second functional layer 20 and is disposed in the same layer as at least part of the transistor 110. The thickness of the insulating layer 30 located between the first electrode plate 121 and the second electrode plate 122 is less than the thickness of the insulating layer 30 located in the transistor 110 region.

[0039] Optionally, the first functional layer 10 may be an active layer, and the second functional layer 20 may be a metal layer. Of course, in some embodiments, both the first functional layer 10 and the second functional layer 20 may be metal layers.

[0040] Optionally, the number of transistors 110 included on the array substrate 100 is not specifically limited. Optionally, the number of transistors 110 may be greater than the number of capacitors 120, which may be specifically set according to the pixel circuit formed on the array substrate 100. For example, when the pixel circuit formed on the array substrate 100 is a 2T1C circuit, the "2T1C circuit" refers to a pixel circuit including two transistors 110 (T) and one capacitor 120 (C) in the pixel circuit, that is, Figure 1 In the structural form shown, the number of transistors 110 included in the array substrate 100 may be twice the number of capacitors 120 .

[0041] like Figure 3 As shown, when the pixel circuit formed on the array substrate 100 is a 7T1C circuit, the "7T1C circuit" refers to a pixel circuit including 7 transistors 110 (T1-T7) and 1 capacitor 120 (C) in the pixel circuit. Then the number of transistors 110 included in the array substrate 100 pixel can be 7 times the number of capacitors 120, and when T3 and T4 are double transistors 110, the number of transistors 110 included in the array substrate 100 pixel can be 9 times the number of capacitors 120. Specifically, it can be driven according to the form of the pixel circuit, as long as it can meet the driving requirements of the light-emitting element.

[0042] Optionally, when the pixel circuit formed on the array substrate 100 can also be any one of a 7T2C circuit or a 9T1C circuit, accordingly, the number of transistors 110 and the number of capacitors 120 can be set and arranged according to the form of the pixel circuit formed, so that when the array substrate 100 is used for a display panel, it can meet the driving requirements of its light-emitting element 210.

[0043] Optionally, the number of the insulating layer 30 included between the first functional layer 10 and the second functional layer 20 may be one layer, or two layers or more than two layers, as long as the functional requirements of the capacitor 120 and the transistor 110 are met.

[0044] Optionally, the transistor 110 may include an active area 111, a gate 112, a source 113 and a drain 114. The active area 111 may be formed in the first functional layer 10, and the gate 112 may be formed in the second functional layer 20. Accordingly, the first electrode plate 121 may be arranged on the same layer as the active area 111, and the second electrode plate 122 may be arranged on the same layer as the gate 112.

[0045] Optionally, in some embodiments, the gate 112 can be formed in the first functional layer 10, and the source 113 and the drain 114 can be formed in the second functional layer 20. Accordingly, the first electrode plate 121 can be arranged on the same layer as the gate 112, and the second electrode plate 122 can be arranged on the same layer as the source 113 and the drain 114.

[0046] Optionally, the insulating layer 30 may be formed such that the thickness of the region between the first electrode plate 121 and the second electrode plate 122 of the capacitor 120 is less than the thickness of the region of the transistor 110 in the thickness direction X of the array substrate by removing part of the material in the region corresponding to the two first electrode plates 121 and the second electrode plate 122. Of course, in some embodiments, the insulating layer 30 may be formed such that the thickness of the region between the first electrode plate 121 and the second electrode plate 122 is less than the thickness of the region of the transistor 110, which can meet the capacitance requirements between the first electrode plate 121 and the second electrode plate 122 and the performance requirements of the transistor 110.

[0047] The array substrate 100 provided in the embodiment of the present application includes a first functional layer 10, a second functional layer 20, and an insulating layer 30 insulated between the first functional layer 10 and the second functional layer 20. The array substrate 100 has a plurality of transistors 110 and a plurality of capacitors 120. Each capacitor 120 is electrically connected to at least one transistor 110. The capacitor 120 includes a first electrode plate 121 and a second electrode plate 122. Since the first electrode plate 121 is formed on the first functional layer 10 and is disposed in the same layer as at least part of the transistor 110, the second electrode plate 122 is formed on the second functional layer 20 and is disposed in the same layer as at least part of the transistor 110. In other words, the first electrode plate 121 and the second electrode plate 122 of the capacitor 120 are both disposed in the same layer as the corresponding layer structure of the transistor 110, and there is no need to add an additional metal layer to form the electrode plate of the capacitor 120 separately, so that the overall manufacturing process of the array substrate 100 is simple and the cost is low.

[0048] Moreover, in the thickness direction X of the array substrate 100, by making the thickness of the insulating layer 30 in the area between the first electrode plate 121 and the second electrode plate 122 smaller than the thickness of the insulating layer 30 in the area of ​​the transistor 110, the distance between the first electrode plate 121 and the second electrode plate 122 is reduced to increase the capacitance between the first electrode plate 121 and the second electrode plate 122. At the same time, the thickness of the insulating layer 30 in the area of ​​the transistor 110 is larger, which can not only simplify the process, but also avoid mutual influence between different layer structures of the transistor 110, thereby ensuring the performance of the transistor 110.

[0049] As an optional implementation, in the array substrate 100 provided in the embodiment of the present application, the polarity of the charge on the first electrode plate 121 is opposite to the polarity of the charge on the second electrode plate 122 .

[0050] That is to say, the first electrode plate 121 and the second electrode plate 122 are only provided with the insulating layer 30, and no other metal layer is provided. One of the first electrode plate 121 and the second electrode plate 122 carries a positive charge, and the other carries a negative charge. The first electrode plate 121 and the second electrode plate 122 carry equal amounts of opposite charges. After charging, an electric field is generated between the first electrode plate 121 and the second electrode plate 122. The electric energy obtained during the charging process is stored in the capacitor 120. During the discharging process, the charged capacitor 120 loses its charge, releasing the charge and electric energy.

[0051] The array substrate 100 provided in the embodiment of the present application makes the charge polarity on the first electrode plate 121 opposite to the charge polarity on the second electrode plate 122, so that no other electrode plates are arranged between the first electrode plate 121 and the second electrode plate 122, thereby improving the stability of the capacitance of the first electrode plate 121 and the second electrode plate 122.

[0052] See also Figure 4 , Figure 4 1 is a cross-sectional view of an array substrate of another embodiment of the present application. In an optional implementation, the array substrate 100 provided in the embodiment of the present application has a groove 31 on the insulating layer 30 that matches the shape of the second electrode plate 122 , and the second electrode plate 122 is at least partially located in the groove 31 .

[0053] Optionally, the groove 31 on the insulating layer 30 may be manufactured by a halftone photo mask process, which can meet the molding process of the groove 31 and has a simple manufacturing process, thereby reducing the cost of the array substrate 100 .

[0054] Optionally, the second electrode plate 122 may be partially or entirely located in the second groove 31 .

[0055] Optionally, the shape of the groove 31 may be circular, elliptical or polygonal. When it is a polygon, it may be a rectangular structure, etc., which may be specifically set according to the shape requirements of the second electrode plate 122 .

[0056] The array substrate 100 provided in the embodiment of the present application is provided with a groove 31 matching the shape of the second electrode plate 122 on the insulating layer 30, so that the second electrode plate 122 can at least partially sink into the groove 31, and the thickness of the remaining portion of the insulating layer 30 between the first electrode plate 121 and the second electrode plate 122 will be less than the thickness of the insulating layer 30 in the region where the transistor 110 is located. In the thickness direction X of the array substrate 100, the distance between the surface of the second electrode plate 122 facing the first electrode plate 121 and the first electrode plate 121 is closer, so as to effectively increase the capacitance between the two.

[0057] like Figure 5as well as Figure 6 As shown, Figure 5 is a cross-sectional view of an array substrate according to another embodiment of the present application. Figure 6 is a cross-sectional view of an array substrate according to yet another embodiment of the present application.

[0058] like Figure 5 As shown, as an optional implementation, in the array substrate 100 provided in the embodiment of the present application, the number of the insulating layers 30 is more than two and they are stacked.

[0059] like Figure 6 As shown, optionally, when a groove 31 is included, the groove 31 can be arranged in at least one insulating layer 30, and the depth of the groove 31 can be less than the thickness of one insulating layer 30. Of course, in some embodiments, the groove 31 can be arranged through one insulating layer 30. In some other examples, the groove 31 can also be arranged through at least one insulating layer 30 and extend to other insulating layers 30.

[0060] Optionally, the number of the insulating layers 30 disposed between the first functional layer 10 and the second functional layer 20 may be two or more layers. Two or more insulating layers 30 are stacked on each other.

[0061] Optionally, the groove 31 may penetrate one of the metal layers. Of course, this is an optional embodiment. In some examples, the groove 31 may penetrate one metal layer and extend to the next metal layer by a predetermined length.

[0062] The array substrate 100 provided in the embodiment of the present application can better meet the performance requirements of the transistor 110 by making the number of insulating layers 30 more than two, and the correspondingly arranged grooves 31 can be arranged in at least one layer of the insulating layer 30, so that the thickness of the remaining insulating layer 30 between the first electrode plate 121 and the second electrode plate 122 can be thinner, thereby meeting the capacitance requirements therebetween.

[0063] As an optional implementation, in the array substrate 100 provided in the embodiment of the present application, the thickness of the insulating layer 30 located between the first electrode plate 121 and the second electrode plate 122 is less than or equal to 2000 angstroms.

[0064] Optionally, in the thickness direction X of the array substrate 100, the total thickness of the insulating layer 30 in the region between the first electrode plate 121 and the second electrode plate 122 is less than or equal to 2000 angstroms. For example, when the number of layers of the insulating layer 30 is one, the thickness of one insulating layer 30 in the region between the first electrode plate 121 and the second electrode plate 122 is less than or equal to 2000 angstroms, and when the number of layers of the insulating layer 30 between the first electrode plate 121 and the second electrode plate 122 is two or more, the sum of the thicknesses of the insulating layers 30 between the first electrode plate 121 and the second electrode plate 122 is less than or equal to 2000 angstroms.

[0065] Optionally, the thickness of the insulating layer 30 in the area between the first electrode plate 121 and the second electrode plate 122 is less than or equal to 2000 angstroms, and can further be less than or equal to 1500 angstroms. In some optional embodiments, the thickness of the insulating layer 30 in the area between the first electrode plate 121 and the second electrode plate 122 can be less than or equal to 800 angstroms. In some embodiments, the thickness of the insulating layer 30 in the area between the first electrode plate 121 and the second electrode plate 122 can be less than or equal to 400 angstroms. While meeting the conditions of the manufacturing process and preventing the first electrode plate 121 and the second electrode plate 122 from short-circuiting due to the breakage of the insulating layer 30, the thickness of the insulating layer 30 between the first electrode plate 121 and the second electrode plate 122 can be minimized to maximize the capacitance between the first electrode plate 121 and the second electrode plate 122.

[0066] As an optional implementation, in the array substrate 100 provided in the embodiment of the present application, the insulating layer 30 includes at least one of a silicon oxide layer and a silicon nitride layer.

[0067] Optionally, the insulating layer 30 may include only a silicon oxide layer. Of course, the insulating layer 30 may also include only a silicon nitride layer. In some examples, the insulating layer 30 may also include a stacked silicon oxide layer and a silicon nitride layer.

[0068] like Figures 2 to 7 As shown, in some optional embodiments, the array substrate 100 provided by the above embodiments of the present application, its transistor 110 includes an active area 111, a gate 112, a source 113 and a drain 114, the active area 111 and the gate 112 are insulated by at least one insulating layer 30, and the source 113 and the drain 114 are insulated from the gate 112 by at least another insulating layer 30. The gate 112 is formed in one of the first functional layer 10 and the second functional layer 20.

[0069] That is to say, the gate 112 may be formed in the first functional layer 10 or in the second functional layer 20 .

[0070] When the gate 112 is formed in the second functional layer 20, the second electrode plate 122 can be disposed in the same layer as the gate 112, and the first electrode plate 121 can be disposed in the same layer as the active region 111. When the gate 112 is formed in the first functional layer 10, the first electrode plate 121 can be disposed in the same layer as the gate 112, and the second electrode plate 122 can be disposed in the same layer as the source 113 and the drain 114.

[0071] The array substrate 100 provided in the embodiment of the present application enables the gate 112 to be formed in one of the first functional layer 10 and the second functional layer 20, so that the first electrode plate 121 and the second electrode plate 122 of the capacitor 120 can be arranged in the same layer as the active area 111 and the gate 112, or the first electrode plate 121 and the second electrode plate 122 of the capacitor 120 can be arranged in the same layer as the gate 112, the source 113 and the drain 114. On the basis of reducing the manufacturing process of the array substrate 100, multiple options can be provided for the forming of the capacitor 120, and the first electrode plate 121 and the second electrode plate 122 can be arranged adjacent to each other to minimize the distance between the two, thereby increasing the capacitance of the capacitor 120 to meet the functional requirements of the array substrate 100.

[0072] Continue reading Figures 2 to 6 As shown, as an optional implementation, the array substrate 100 provided in the embodiment of the present application has a first functional layer 10 as an active layer, a second functional layer 20 as a metal layer, an active area 111 formed in the first functional layer 10 , and a gate 112 formed in the second functional layer 20 .

[0073] That is, the first electrode plate 121 is disposed at the same layer as the active region 111 of the transistor 110 , and the second electrode plate 122 is disposed at the same layer as the gate 112 of the transistor 110 .

[0074] Optionally, the insulating layer 30 between the active layer and the metal layer forming the gate 112 is used to separate the active region 111 from the gate 112 , and the insulating layer 30 may be made of silicon oxide or silicon nitride.

[0075] like Figure 2 As shown, exemplarily, when the first electrode plate 121 is disposed on the same layer as the active area 111 of the transistor 110 and the second electrode plate 122 is disposed on the same layer as the gate 112 of the transistor 110, the number of insulating layers 30 between the first functional layer 10 and the second functional layer 20 can be one layer.

[0076] When the insulating layer 30 is a single layer, the thickness of the insulating layer 30 between the first electrode plate 121 and the second electrode plate 122 can be smaller than the thickness of the insulating layer 30 between the active region 111 and the gate 112. Of course, this is an optional method.

[0077] like Figure 4 As shown, in some embodiments, a groove 31 may be provided on the insulating layer 30 so that the second electrode plate 122 is at least partially located in the groove 31.

[0078] It can be understood that when the first electrode plate 121 is arranged on the same layer as the active area 111 of the transistor 110, and the second electrode plate 122 is arranged on the same layer as the gate 112 of the transistor 110, the number of insulating layers 30 between the first functional layer 10 and the second functional layer 20 can also be two layers. Among the two insulating layers 30, the insulating layer 30 close to the first functional layer 10 can be a silicon oxide layer, and the insulating layer 30 close to the second functional layer 20 can be a silicon nitride layer.

[0079] like Figure 5 As shown, when the insulating layer 30 is two layers, one of the insulating layers 30 can be manufactured so that the thickness between the first electrode plate 121 and the second electrode plate 122 is smaller than the thickness between the active region 111 and the gate 112. Of course, the two insulating layers 30 can also be manufactured so that the thickness between the first electrode plate 121 and the second electrode plate 122 is smaller than the thickness between the active region 111 and the gate 112.

[0080] like Figure 6 As shown, of course, when the insulating layer 30 is two layers, a groove 31 can also be set on the insulating layer 30 set away from the first functional layer 10. The groove 31 can penetrate the thickness of the insulating layer 30 in depth. Of course, it can also be less than the thickness of the insulating layer 30. It can also extend to a predetermined thickness to the insulating layer 30 close to the active area 111 on the basis of penetrating the insulating layer 30.

[0081] Optionally, when the first electrode plate 121 is disposed at the same layer as the active region 111 of the transistor 110 and the second electrode plate 122 is disposed at the same layer as the gate 112 of the transistor 110 , the thickness of the insulating layer 30 between the first electrode plate 121 and the second electrode plate 122 may be less than or equal to 800 angstroms.

[0082] It can be understood that the above embodiments limit the first electrode plate 121 and the active area 111 of the transistor 110 to be disposed at the same layer, and the second electrode plate 122 and the gate 112 of the transistor 110 to be disposed at the same layer is only an optional example.

[0083] like Figure 7 , Figure 8 FIG. 2 is a cross-sectional view of an array substrate according to another embodiment of the present application. Figure 8In some embodiments, the first functional layer 10 and the second functional layer 20 may be metal layers, the gate 112 may be formed on the first functional layer 10 , and the source 113 and the drain 114 may be formed on the second functional layer 20 .

[0084] That is to say, the first electrode plate 121 and the gate electrode 112 of the transistor 110 may be disposed on the same layer, and the second electrode plate 122 and the source electrode 113 and the drain electrode 114 of the transistor 110 may be disposed on the same layer.

[0085] Optionally, an insulating layer 30 between the metal layer forming the gate 112 and the metal layer forming the source 113 and the drain 114 is used to separate the two metal layers. The insulating layer 30 can be made of silicon nitride material. Of course, in some embodiments, the insulating layer 30 can also be made of silicon oxide and silicon nitride stacked materials, as long as the capacitance requirements of the capacitor 120 can be guaranteed.

[0086] Exemplarily, when the first electrode plate 121 is disposed on the same layer as the gate 112 of the transistor 110 and the second electrode plate 122 is disposed on the same layer as the source 113 and the drain 114 of the transistor 110 , the number of insulating layers 30 between the first functional layer 10 and the second functional layer 20 can be one layer.

[0087] like Figure 7 As shown, when the insulating layer 30 is a single layer, the thickness of the insulating layer 30 between the first electrode plate 121 and the second electrode plate 122 can be smaller than the thickness of the insulating layer 30 between the source electrode 113, the drain electrode 114 and the gate electrode 112. Of course, this is an optional method.

[0088] like Figure 8 As shown, in some embodiments, a groove 31 may also be provided on the insulating layer 30 , so that the second electrode plate 122 is at least partially located in the groove 31 .

[0089] The groove 31 can be manufactured by using a halftone photo mask process.

[0090] It can be understood that when the first electrode plate 121 is arranged on the same layer as the gate 112 of the transistor 110, and the second electrode plate 122 is arranged on the same layer as the source 113 and the drain 114 of the transistor 110, the number of insulating layers 30 between the first functional layer 10 and the second functional layer 20 can also be two layers, and of the two insulating layers 30, one can be a silicon nitride layer and the other can be a silicon oxide layer.

[0091] When the insulating layer 30 has two layers, one of the insulating layers 30 can be manufactured so that the thickness between the first electrode plate 121 and the second electrode plate 122 is smaller than the thickness between the gate 112 and the source 113 and the drain 114. Of course, the two insulating layers 30 can also be manufactured so that the thickness between the first electrode plate 121 and the second electrode plate 122 is smaller than the thickness between the gate 112 and the source 113 and the drain 114.

[0092] Of course, when the insulating layer 30 consists of two layers, a groove 31 can be set on the insulating layer 30 that is set away from the first functional layer 10. The groove 31 can penetrate the thickness of the insulating layer 30 to a depth. Of course, it can also be less than the thickness of the insulating layer 30. It can also extend to a predetermined thickness toward the insulating layer 30 close to the active area 111 on the basis of penetrating the insulating layer 30.

[0093] Optionally, when the first electrode plate 121 is disposed on the same layer as the gate 112 of the transistor 110, and the second electrode plate 122 is disposed on the same layer as the source 113 and the drain 114 of the transistor 110, the thickness of the insulating layer 30 between the first electrode plate 121 and the second electrode plate 122 may be less than or equal to 400 angstroms.

[0094] Please continue reading Figure 2 , Figures 4 to 8 As shown, as an optional implementation, the array substrate 100 provided in the above embodiments of the present application further includes an inorganic film layer 40, a third functional layer 50 and a planarization layer 60, the third functional layer 50 is a metal layer, the inorganic film layer 40 is insulated and arranged between the second functional layer 20 and the third functional layer 50, and the planarization layer 60 is arranged on the side of the third functional layer 50 away from the second functional layer 20.

[0095] Optionally, the planarization layer 60 may be an organic film layer.

[0096] Optionally, the third functional layer 50 can be used to form power lines. At the same time, part of the third functional layer 50 can be patterned according to the source 113 and the drain 114 to form a metal block to which the source 113 and the drain 114 are connected through vias. This can reduce the depth of the via when the source 113 or the drain 114 is electrically connected to the light-emitting element 210 when the array substrate 100 is used for a display panel, thereby ensuring the reliability of the connection.

[0097] In the array substrate 100 in the prior art, the planarization layer 60 is usually located between the second functional layer 20 and the third functional layer 50. At the same time, the inorganic film layer 40 is located on the side of the third functional layer 50 away from the second functional layer 20. Since the planarization layer 60 is an organic film layer, its thickness is relatively thick, while the inorganic film layer 40 is relatively thin. Therefore, the inorganic film layer 40 of the array substrate 100 in the prior art cannot completely cover the third functional layer 50, resulting in the problem of low reliability of the array substrate 100.

[0098] In the array substrate 100 provided in the embodiment of the present application, the inorganic film layer 40 is insulated and disposed between the second functional layer 20 and the third functional layer 50, and the planarization layer 60 is disposed on the side of the third functional layer 50 away from the second functional layer 20. The original process route of the array substrate 100 is changed, and the planarization layer 60 with good fluidity and thick film layer is disposed on the side of the third functional layer 50 away from the second functional layer 20, which can ensure the coverage of the third functional layer 50 and improve the reliability of the array substrate 100.

[0099] It can be understood that the array substrate 100 provided in the embodiment of the present application can be provided with a third functional layer 50 to facilitate the formation of power lines, etc. Of course, in some embodiments, the power lines, etc. can also be provided on the second functional layer, etc., as long as the performance requirements of the array substrate 100 can be guaranteed.

[0100] like Figures 9 to 11 As shown, on the other hand, an embodiment of the present application also includes a display panel, including the above-mentioned array substrate 100 and a light-emitting layer 200, the light-emitting layer 200 is stacked on the array substrate 100, and the light-emitting layer 200 includes a plurality of light-emitting elements 210, and each light-emitting element 210 is electrically connected to at least one transistor 110.

[0101] The display panel provided in the embodiment of the present application includes the array substrate 100 provided in the above embodiments, so that the first electrode plate 121 and the second electrode plate 122 of the capacitor 120 are both arranged in the same layer structure as the corresponding layer structure of the transistor 110, and no additional metal layer is needed to form the electrode plate of the capacitor 120 separately, so that the overall manufacturing process of the array substrate 100 is simple and the cost is low. In addition, by making the thickness of the insulating layer 30 located between the first electrode plate 121 and the second electrode plate 122 smaller than the thickness of the insulating layer 30 located in the transistor 110 region, the distance between the first electrode plate 121 and the second electrode plate 122 is reduced, so as to increase the capacitance between the first electrode plate 121 and the second electrode plate 122, and at the same time, making the thickness of the insulating layer 30 located in the transistor 110 region larger, which can not only simplify the process, but also avoid the mutual influence between the different layer structures of the transistor 110, thereby ensuring the performance of the transistor 110 and the uniformity of the display panel during display.

[0102] On the other hand, an embodiment of the present application also includes a display device, including the display panel provided by the above embodiments, which has good display uniformity.

[0103] Although the present application has been described with reference to preferred embodiments, various modifications may be made thereto and parts thereof may be replaced with equivalents without departing from the scope of the present application. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there are no structural conflicts. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. An array substrate, comprising a first functional layer, a second functional layer, and an insulating layer insulated between the first functional layer and the second functional layer, characterized in that: The array substrate has a plurality of transistors and a plurality of capacitors, each of the capacitors is electrically connected to at least one of the transistors, and the capacitors include a first electrode plate and a second electrode plate, the first electrode plate is formed on the first functional layer and is disposed in the same layer as at least part of the transistors, and the second electrode plate is formed on the second functional layer and is disposed in the same layer as at least part of the transistors; The thickness of the insulating layer in the area between the first electrode plate and the second electrode plate is less than the thickness of the insulating layer in the transistor area, and a groove matching the shape of the second electrode plate is provided on the insulating layer, and the groove is circular, elliptical or polygonal, and the second electrode plate is at least partially located in the groove.

2. The array substrate according to claim 1, characterized in that: The polarity of the charge on the first electrode plate is opposite to the polarity of the charge on the second electrode plate.

3. The array substrate according to claim 1, characterized in that: The thickness of the second electrode plate is greater than or equal to the depth of the groove.

4. The array substrate according to claim 2, characterized in that: The number of the insulating layers is more than two and they are stacked, and the groove is arranged in at least one of the insulating layers.

5. The array substrate according to claim 1, characterized in that: The thickness of the insulating layer in the region between the first electrode plate and the second electrode plate is less than or equal to 2000 angstroms.

6. The array substrate according to claim 1, characterized in that: The insulating layer includes at least one of a silicon oxide layer and a silicon nitride layer.

7. The array substrate according to any one of claims 1 to 6, characterized in that: The transistor includes an active region, a gate, a source, and a drain. The gate is formed in one of the first functional layer and the second functional layer.

8. The array substrate according to claim 7, characterized in that: The first functional layer is an active layer, the second functional layer is a metal layer, the active region is formed in the first functional layer, and the gate is formed in the second functional layer.

9. The array substrate according to claim 7, characterized in that: The first functional layer and the second functional layer are metal layers respectively. The gate is formed on the first functional layer, and the source and the drain are both formed on the second functional layer.

10. The array substrate according to claim 9, characterized in that: The array substrate also includes an inorganic film layer, a third functional layer and a planarization layer, the third functional layer is a metal layer, the inorganic film layer is insulated and arranged between the second functional layer and the third functional layer, and the planarization layer is arranged on a side of the third functional layer away from the second functional layer.

11. A display panel, characterized in that: include: The array substrate according to any one of claims 1 to 10; The light-emitting layer is stacked on the array substrate, and the light-emitting layer includes a plurality of light-emitting elements, each of which is electrically connected to at least one of the transistors.

12. A display device, characterized in that: Comprising the display panel as claimed in claim 11.

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