Packaging structure and manufacturing method thereof

Abstract

The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes a reconfiguration circuit layer, a chip component, a plurality of solder balls and a packaging colloid. The reconfiguration circuit layer includes a plurality of reconfiguration circuits, a plurality of photosensitive dielectric layers, a plurality of conductive vias and a plurality of chip pads. The two outermost photosensitive dielectric layers respectively have an upper surface and a plurality of openings. The chip pad is located on the upper surface and is electrically connected to the reconfiguration circuit through the conductive vias. The opening exposes part of the reconfiguration circuit to define a plurality of solder ball pads. The line width and line spacing of the reconfiguration circuit decrease from the solder ball pad to the chip pad. The chip component is arranged on the chip pad and includes at least two chips of different sizes. The solder balls are respectively arranged on the solder ball pads, and the packaging colloid at least covers the chip component. Since the present invention does not require a transfer board, the packaging structure can have better structural reliability.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a manufacturing method thereof, and in particular to a packaging structure and a manufacturing method thereof. Background Art

[0002] In the prior art, when making a fan-out panel level package (FOPLP) of chip-last (or RDL first), the fine circuits of the reconfiguration circuit substrate are first made on a temporary substrate. Then, after the general circuits of the reconfiguration circuit substrate are made, the reconfiguration circuit substrate needs to be transferred from the original temporary substrate to another temporary substrate, and before the chip and the reconfiguration circuit substrate are bonded, the original temporary substrate is debonded to expose the chip pads for electrical connection with the chip. However, during the transfer process, the reconfiguration circuit substrate is prone to uneven expansion and contraction, which in turn affects the structural reliability of subsequent products. Summary of the invention

[0003] The present invention is directed to a packaging structure which can have better structural reliability.

[0004] The present invention also provides a method for manufacturing a packaging structure, which is used to manufacture the above packaging structure.

[0005] According to an embodiment of the present invention, a packaging structure includes a reconfiguration circuit layer, a chip component, a plurality of solder balls, and a packaging colloid. The reconfiguration circuit layer includes a plurality of reconfiguration circuits, a plurality of photosensitive dielectric layers, a plurality of conductive vias, and a plurality of chip pads. The reconfiguration circuits and the photosensitive dielectric layers are alternately arranged, and the conductive vias penetrate the photosensitive dielectric layers and are electrically connected to the reconfiguration circuits. One of the two outermost photosensitive dielectric layers has an upper surface, and the chip pads are located on the upper surface and are electrically connected to the reconfiguration circuits through the conductive vias. The other of the two outermost photosensitive dielectric layers has a plurality of openings, and the openings expose a portion of the reconfiguration circuits to define a plurality of solder ball pads. The line width and line spacing of the reconfiguration circuits decrease from the solder ball pads to the chip pads. The chip component is arranged on the chip pads and is electrically connected to the chip pads, wherein the chip component includes at least two chips of different sizes. The solder balls are respectively arranged on the solder ball pads and are electrically connected to the solder ball pads. The packaging colloid at least covers the chip component.

[0006] In the packaging structure according to an embodiment of the present invention, the above-mentioned reconfiguration circuit layer includes a first reconfiguration circuit layer, a second reconfiguration circuit layer and a third reconfiguration circuit layer. The reconfiguration circuit includes a first reconfiguration circuit, a second reconfiguration circuit and a third reconfiguration circuit. The photosensitive dielectric layer includes a first photosensitive dielectric layer, a second photosensitive dielectric layer, a third photosensitive dielectric layer and a fourth photosensitive dielectric layer. The conductive via includes a plurality of first conductive vias, a plurality of second conductive vias and a plurality of third conductive vias. The first reconfiguration circuit layer includes a chip pad, a first reconfiguration circuit, a first photosensitive dielectric layer and a first conductive via penetrating the first photosensitive dielectric layer. The first photosensitive dielectric layer has an upper surface, and the chip pad is electrically connected to the first reconfiguration circuit through the first conductive via. The second reconfiguration circuit layer includes a second reconfiguration circuit, a second photosensitive dielectric layer and a second conductive via penetrating the second photosensitive dielectric layer. The second conductive via electrically connects the first reconfiguration circuit with the second reconfiguration circuit. The third reconfiguration circuit layer includes a third reconfiguration circuit, a third photosensitive dielectric layer, a fourth photosensitive dielectric layer, and a third conductive via penetrating the third photosensitive dielectric layer. The third conductive via electrically connects the second reconfiguration circuit and the third reconfiguration circuit. The fourth photosensitive dielectric layer covers the third photosensitive dielectric layer and the third reconfiguration circuit and has an opening. The opening exposes a portion of the third reconfiguration circuit to define a solder ball pad. The line width and line spacing of the third reconfiguration circuit are greater than the line width and line spacing of the second reconfiguration circuit. The line width and line spacing of the second reconfiguration circuit are greater than the line width and line spacing of the first reconfiguration circuit.

[0007] In the packaging structure according to the embodiment of the present invention, the line width and line spacing of the first reconfiguration circuit are 2 microns, the line width and line spacing of the second reconfiguration circuit are 5 microns, and the line width and line spacing of the third reconfiguration circuit are 10 microns.

[0008] In the package structure according to the embodiment of the present invention, the thickness of the first reconfiguration circuit is equal to the thickness of the second reconfiguration circuit, and the thickness of the second reconfiguration circuit is less than the thickness of the third reconfiguration circuit.

[0009] In the packaging structure according to the embodiment of the present invention, the depth of the second conductive via is equal to the depth of the third conductive via, and the depth of the first conductive via is less than the depth of the second conductive via.

[0010] In the packaging structure according to the embodiment of the present invention, the periphery of the packaging colloid is aligned with the periphery of the first reconfiguration circuit layer, the periphery of the second reconfiguration circuit layer, and the periphery of the third reconfiguration circuit layer.

[0011] In the packaging structure according to the embodiment of the present invention, the packaging structure further comprises a plurality of copper pillars and a plurality of solders. The copper pillars are arranged on the chip assembly and between the chip assembly and the chip pads. The solders are arranged on the copper pillars and between the copper pillars and the chip pads.

[0012] In the packaging structure according to the embodiment of the present invention, the packaging structure further comprises a primer disposed between the packaging colloid and the reconfiguration circuit layer. The primer covers the copper pillars, solder and chip pads, and the periphery of the primer is aligned with the periphery of the packaging colloid.

[0013] In the packaging structure according to the embodiment of the present invention, the chip assembly includes a processor and two memories, and the size of the processor is larger than the size of each memory.

[0014] In the packaging structure according to the embodiment of the present invention, the packaging structure further includes a circuit board, which is arranged below the reconfiguration circuit layer, and the chip assembly is electrically connected to the circuit board through solder balls.

[0015] According to an embodiment of the present invention, a method for manufacturing a packaging structure includes the following steps. A reconfiguration circuit layer is formed on a temporary carrier. The reconfiguration circuit layer includes a plurality of reconfiguration circuits, a plurality of photosensitive dielectric layers, a plurality of conductive vias, and a plurality of chip pads. The reconfiguration circuits and the photosensitive dielectric layers are alternately configured. The conductive vias penetrate the photosensitive dielectric layers and are electrically connected to the reconfiguration circuits. One of the two outermost photosensitive dielectric layers has an upper surface, and the chip pad is located on the upper surface and is electrically connected to the reconfiguration circuits through the conductive vias. The other of the two outermost photosensitive dielectric layers is directly attached to the temporary carrier. A chip assembly is configured on the chip pad and electrically connected to the chip pad, wherein the chip assembly includes at least two chips of different sizes. A packaging colloid is formed to at least cover the chip assembly. After the chip assembly is configured on the chip pad, the temporary carrier is removed to expose the other of the two outermost photosensitive dielectric layers. A plurality of openings are formed in the other of the two outermost photosensitive dielectric layers to expose a portion of the reconfiguration circuits and define a plurality of solder ball pads. The line width and line spacing of the reconfiguration circuits decrease from the solder ball pads to the chip pads. A plurality of solder balls are formed on the solder ball pads to electrically connect the solder ball pads.

[0016] In the manufacturing method of the packaging structure according to an embodiment of the present invention, the above-mentioned reconfiguration circuit layer includes a first reconfiguration circuit layer, a second reconfiguration circuit layer and a third reconfiguration circuit layer. The reconfiguration circuit includes a first reconfiguration circuit, a second reconfiguration circuit and a third reconfiguration circuit. The photosensitive dielectric layer includes a first photosensitive dielectric layer, a second photosensitive dielectric layer, a third photosensitive dielectric layer and a fourth photosensitive dielectric layer. The conductive via includes a plurality of first conductive vias, a plurality of second conductive vias and a plurality of third conductive vias. The step of forming a reconfiguration circuit layer on a temporary carrier includes providing a temporary carrier, the temporary carrier includes a substrate and a release film located on the substrate. A third reconfiguration circuit layer is formed on the temporary carrier, the third reconfiguration circuit layer includes a third reconfiguration circuit, a third photosensitive dielectric layer, a fourth photosensitive dielectric layer and a third conductive via penetrating the third photosensitive dielectric layer. The fourth photosensitive dielectric layer covers the third photosensitive dielectric layer and the third reconfiguration circuit. A second reconfiguration circuit layer is formed on the third reconfiguration circuit layer. The second reconfiguration circuit layer includes a second reconfiguration circuit, a second photosensitive dielectric layer, and a second conductive via penetrating the second photosensitive dielectric layer. The second reconfiguration circuit and the third conductive via are formed simultaneously. The third conductive via electrically connects the second reconfiguration circuit and the third reconfiguration circuit. A first reconfiguration circuit layer is formed on the second reconfiguration circuit layer. The first reconfiguration circuit layer includes a chip pad, a first reconfiguration circuit, a first photosensitive dielectric layer, and a first conductive via penetrating the first photosensitive dielectric layer. The first photosensitive dielectric layer has an upper surface, and the chip pad is electrically connected to the first reconfiguration circuit through the first conductive via. The first reconfiguration circuit and the second conductive via are formed simultaneously. The second conductive via electrically connects the first reconfiguration circuit and the second reconfiguration circuit. The chip pad and the first conductive via are formed simultaneously. The line width and line spacing of the third reconfiguration circuit are greater than the line width and line spacing of the second reconfiguration circuit. The line width and line spacing of the second reconfiguration circuit are greater than the line width and line spacing of the first reconfiguration circuit.

[0017] In the method for manufacturing a package structure according to an embodiment of the present invention, the line width and line spacing of the first reconfiguration circuit are 2 microns, the line width and line spacing of the second reconfiguration circuit are 5 microns, and the line width and line spacing of the third reconfiguration circuit are 10 microns.

[0018] In the method for manufacturing a package structure according to an embodiment of the present invention, the thickness of the first reconfiguration circuit is equal to the thickness of the second reconfiguration circuit, and the thickness of the second reconfiguration circuit is less than the thickness of the third reconfiguration circuit.

[0019] In the method for manufacturing a package structure according to an embodiment of the present invention, the depth of the second conductive via is equal to the depth of the third conductive via, and the depth of the first conductive via is less than the depth of the second conductive via.

[0020] In the method for manufacturing a package structure according to an embodiment of the present invention, the step of forming an opening includes: performing a drilling process on the fourth photosensitive dielectric layer to form an opening that exposes a portion of the third reconfiguration circuit.

[0021] In the method for manufacturing the package structure according to the embodiment of the present invention, before configuring the chip assembly on the chip pad, it also includes forming a plurality of copper pillars on at least two chips of the wafer and forming a plurality of solders on the copper pillars. The copper pillars are located between the at least two chips and the solders.

[0022] In the method for manufacturing the packaging structure according to the embodiment of the present invention, before forming the packaging glue to at least cover the chip component, it also includes forming a primer on the reconfiguration circuit layer to cover the copper pillars, solder and chip pads.

[0023] In the method for manufacturing a package structure according to an embodiment of the present invention, the chip assembly includes a processor and two memories, and the size of the processor is larger than the size of each memory.

[0024] In the method for manufacturing a package structure according to an embodiment of the present invention, the method for manufacturing a package structure further comprises providing a circuit board below the reconfiguration circuit layer, wherein the chip component is electrically connected to the circuit board via solder balls.

[0025] Based on the above, in the packaging structure and manufacturing method of the present invention, the reconfiguration circuit layer is formed on a temporary carrier, and the temporary carrier is removed after the chip component is configured on the chip pad. In other words, the present invention first manufactures the reconfiguration circuit for forming the solder ball pad, and then manufactures the reconfiguration circuit for forming the chip pad. Therefore, the present invention does not need to transfer the board, and can make the packaging structure have better structural reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic top view of a packaging structure according to an embodiment of the present invention;

[0027] Figures 2A to 2Z is a cross-sectional schematic diagram of a method for manufacturing a packaging structure according to an embodiment of the present invention;

[0028] Figure 3 is a cross-sectional schematic diagram of a packaging structure according to another embodiment of the present invention.

[0029] Description of Reference Numerals

[0030] 10: Temporary bearing member;

[0031] 12: substrate;

[0032] 14: release film;

[0033] 20: Temporary bearing member;

[0034] 22: substrate;

[0035] 24: release film;

[0036] 100a, 100b: packaging structure;

[0037] 110: first reconfiguration circuit layer;

[0038] 112: first reconfiguration circuit;

[0039] 114: a first photosensitive dielectric layer;

[0040] 115: Open your mouth;

[0041] 116: first conductive via;

[0042] 117: upper surface;

[0043] 118: chip pad;

[0044] 120: second reconfiguration circuit layer;

[0045] 122: second reconfiguration circuit;

[0046] 124: a second photosensitive dielectric layer;

[0047] 125: Open your mouth;

[0048] 126: second conductive via;

[0049] 130: third reconfiguration circuit layer;

[0050] 132: third reconfiguration line;

[0051] 134: a third photosensitive dielectric layer;

[0052] 135: Open your mouth;

[0053] 136: a third conductive via;

[0054] 138: fourth photosensitive dielectric layer;

[0055] 139: Open your mouth;

[0056] 140: processor;

[0057] 150: memory;

[0058] 160: base glue;

[0059] 170: encapsulation colloid;

[0060] 180: solder ball;

[0061] 190: circuit board;

[0062] C: copper column;

[0063] D1, D2, D3: depth;

[0064] E1, E2: surface treatment layer;

[0065] M1: first metal layer;

[0066] M2: second metal layer;

[0067] M3: the third metal layer;

[0068] M4: fourth metal layer;

[0069] P1: first patterned photoresist layer;

[0070] P2: second patterned photoresist layer;

[0071] P3: third patterned photoresist layer;

[0072] P4: fourth patterned photoresist layer;

[0073] S: solder;

[0074] S1: first seed layer;

[0075] S2: second seed layer;

[0076] S3: third seed layer;

[0077] S4: fourth seed layer;

[0078] SP: Solder ball pad;

[0079] T1, T2, T3, T4, T5: thickness;

[0080] RDL: Reconfiguration Line Layer. DETAILED DESCRIPTION

[0081] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0082] Figure 1 is a top view schematically showing a packaging structure according to an embodiment of the present invention. Figures 2A to 2Z is a cross-sectional schematic diagram of a method for manufacturing a packaging structure according to an embodiment of the present invention. It should be noted that: Figures 2A to 2Z is along Figure 1Regarding the method for making the packaging structure of this embodiment, first, please refer to Figure 2S , a reconfiguration wiring layer RDL is formed on the temporary carrier 10 , wherein the reconfiguration wiring layer RDL includes a first reconfiguration wiring layer 110 , a second reconfiguration wiring layer 120 and a third reconfiguration wiring layer 130 .

[0083] For details, please refer to Figure 2A A temporary carrier 10 is provided, wherein the temporary carrier 10 includes a substrate 12 and a release film 14 located on the substrate 12. The substrate 12 is, for example, a glass substrate, but is not limited thereto. Next, a fourth photosensitive dielectric layer 138 and a first seed layer S1 thereon are formed on the release film 14 of the temporary carrier 10.

[0084] Next, please refer to Figure 2B , forming a first patterned photoresist layer P1 on the first seed layer S1 , wherein the first patterned photoresist layer P1 exposes a portion of the first seed layer S1 .

[0085] Next, please refer to Figure 2C , using the first patterned photoresist layer P1 as a plating mask, the first metal layer M1 is electroplated on the first seed layer S1 where the first patterned photoresist layer P1 is not disposed.

[0086] Next, please also refer to Figure 2C and Figure 2D , the first patterned photoresist layer P1 and the first seed layer S1 thereunder are removed to expose a portion of the fourth photosensitive dielectric layer 138 , and to form a third reconfiguration circuit 132 .

[0087] Next, please refer to Figure 2E , a third photosensitive dielectric layer 134 is formed on the third reconfiguration circuit 132 and the exposed fourth photosensitive dielectric layer 138 . Here, the third photosensitive dielectric layer 134 has a plurality of openings 135 , wherein the openings 135 expose a portion of the third reconfiguration circuit 132 .

[0088] Next, please refer to Figure 2F , a second seed layer S2 is formed on the third photosensitive dielectric layer 134 , wherein the second seed layer S2 covers the third photosensitive dielectric layer 134 and the inner wall of the opening 135 .

[0089] Next, please refer to Figure 2G , forming a second patterned photoresist layer P2 on the second seed layer S2, wherein the second patterned photoresist layer P2 exposes a portion of the second seed layer S2.

[0090] Next, please refer to Figure 2H, using the second patterned photoresist layer P2 as a plating mask, the second metal layer M2 is electroplated on the second seed layer S2 where the second patterned photoresist layer P2 is not disposed.

[0091] Next, please also refer to Figure 2H as well as Fig.2I , remove the second patterned photoresist layer P2 and the second seed layer S2 thereunder, thereby exposing a portion of the third photosensitive dielectric layer 134, and forming a plurality of third conductive vias 136 in the opening 135 and a second reconfiguration circuit 122 on the third photosensitive dielectric layer 134. Here, the third conductive vias 136 are formed simultaneously with the second reconfiguration circuit 122, and the third conductive vias 136 electrically connect the third reconfiguration circuit 132 and the second reconfiguration circuit 122. At this point, a third reconfiguration circuit layer 130 has been formed on the temporary carrier 10, wherein the third reconfiguration circuit layer 130 includes a third reconfiguration circuit 132, a third photosensitive dielectric layer 134, a third conductive via 136 penetrating the third photosensitive dielectric layer 134, and a fourth photosensitive dielectric layer 138 covering the third photosensitive dielectric layer 134 and the third reconfiguration circuit 132.

[0092] In particular, in the present embodiment, the line width and line spacing of the third reconfiguration circuit 132 are greater than the line width and line spacing of the second reconfiguration circuit 122. Preferably, the line width and line spacing of the second reconfiguration circuit 122 are, for example, 5 microns, respectively, and the line width and line spacing of the third reconfiguration circuit 132 are, for example, 10 microns, respectively. Furthermore, the thickness T2 of the second reconfiguration circuit 122 is less than the thickness T3 of the third reconfiguration circuit 132, wherein the thickness T2 of the second reconfiguration circuit 122 is, for example, 2.5 microns, and the thickness T3 of the third reconfiguration circuit 132 is, for example, 8 microns. In addition, the depth D3 of the third conductive via 136 is, for example, 6.5 microns.

[0093] Next, please refer to Figure 2J , a second photosensitive dielectric layer 124 is formed on the second reconfiguration circuit 122 and the exposed third photosensitive dielectric layer 134 . Here, the second photosensitive dielectric layer 124 has a plurality of openings 125 , wherein the openings 125 expose a portion of the second reconfiguration circuit 122 .

[0094] Next, please refer to Figure 2K , a third seed layer S3 is formed on the second photosensitive dielectric layer 124 , wherein the third seed layer S3 covers the second photosensitive dielectric layer 124 and the inner wall of the opening 125 .

[0095] Next, please refer to Figure 2L , forming a third patterned photoresist layer P3 on the third seed layer S3, wherein the third patterned photoresist layer P3 exposes a portion of the third seed layer S3.

[0096] Next, please refer to Figure 2M , using the third patterned photoresist layer P3 as a plating mask, the third metal layer M3 is electroplated on the third seed layer S3 where the third patterned photoresist layer P3 is not disposed.

[0097] Next, please also refer to Figure 2M as well as Figure 2N , the third patterned photoresist layer P3 and the third seed layer S3 thereunder are removed to expose a portion of the second photosensitive dielectric layer 124, and to form a plurality of second conductive vias 126 in the opening 125 and a first reconfiguration circuit 112 on the second photosensitive dielectric layer 124. Here, the second conductive vias 126 are formed simultaneously with the first reconfiguration circuit 112, and the second conductive vias 126 electrically connect the second reconfiguration circuit 122 and the first reconfiguration circuit 112. Thus, a second reconfiguration circuit layer 120 has been formed on the third reconfiguration circuit layer 130, wherein the second reconfiguration circuit layer 120 includes the second reconfiguration circuit 122, the second photosensitive dielectric layer 124, and the second conductive vias 126 penetrating the second photosensitive dielectric layer 124.

[0098] In particular, the line width and line spacing of the second reconfiguration circuit 122 are greater than the line width and line spacing of the first reconfiguration circuit 112. Preferably, the line width and line spacing of the first reconfiguration circuit 112 are, for example, 2 microns respectively. Furthermore, the thickness T1 of the first reconfiguration circuit 112 is equal to the thickness T2 of the second reconfiguration circuit 122, which means that the thickness T2 of the first reconfiguration circuit 112 is 2.5 microns. In addition, the depth D2 of the second conductive via 126 is equal to the depth D3 of the third conductive via 136, which means that the depth D2 of the second conductive via 126 is, for example, 6.5 microns.

[0099] Next, please refer to Fig.2O , a first photosensitive dielectric layer 114 is formed on the first reconfiguration circuit 112 and the exposed second photosensitive dielectric layer 124 . Here, the first photosensitive dielectric layer 114 has a plurality of openings 115 , wherein the openings 115 expose a portion of the first reconfiguration circuit 112 .

[0100] Next, please refer to Figure 2P , a fourth seed layer S4 is formed on the first photosensitive dielectric layer 114 , wherein the fourth seed layer S4 covers the first photosensitive dielectric layer 114 and the inner wall of the opening 115 .

[0101] Next, please refer to Figure 2Q , forming a fourth patterned photoresist layer P4 on the fourth seed layer S4 , wherein the fourth patterned photoresist layer P4 exposes a portion of the fourth seed layer S4 .

[0102] Next, please refer to Figure 2R, using the fourth patterned photoresist layer P4 as a plating mask, a fourth metal layer M4 is electroplated on the fourth seed layer S4 where the fourth patterned photoresist layer P4 is not disposed.

[0103] Next, please also refer to Figure 2R as well as Figure 2S , the fourth patterned photoresist layer P4 and the fourth seed layer S4 thereunder are removed to expose a portion of the first photosensitive dielectric layer 114, and to form a plurality of first conductive vias 116 in the opening 115 and a plurality of chip pads 118 on the first photosensitive dielectric layer 114. Here, the first conductive vias 116 and the chip pads 118 are formed simultaneously, and the first conductive vias 116 are electrically connected to the first reconfiguration circuit 112 and the chip pads 118. In particular, the depth D1 of the first conductive via 116 is less than the depth D2 of the second conductive via 126, wherein the depth D1 of the first conductive via 116 is, for example, 5 microns. The size of the chip pad 118 is, for example, 35 microns, and the thickness T4 of the chip pad 118 is, for example, 8 microns. At this point, the first reconfiguration circuit layer 110 has been formed on the second reconfiguration circuit layer 120 , wherein the first reconfiguration circuit layer 110 includes a first reconfiguration circuit 112 , a first photosensitive dielectric layer 114 , a first conductive via 116 penetrating the first photosensitive dielectric layer 114 , and a chip pad 118 .

[0104] Next, please refer to Figure 2T , forming a surface treatment layer E1 on the chip pad 118 to protect the chip pad 118 from oxidation. Here, the material of the surface treatment layer E1 is, for example, nickel-palladium immersion gold (ENEPIG), organic solderability preservatives (OSP) or electroless nickel immersion gold (ENIG), but is not limited thereto.

[0105] Next, please also refer to Figure 1 and Figure 2U, a chip component is configured on the chip pad 118, wherein the chip component includes a processor 140 and two memories 150, and the size of the processor 140 is larger than the size of the memory 150. Here, the size of the processor 140 is, for example, 10 mm x 10 mm, and the size of the memory 150 is, for example, 5 mm x 7 mm, and the processor 140 and the memory 150 are application chipsets for mobile applications. Further, before configuring the chip component on the chip pad 118, a plurality of copper pillars C are first formed on the processor 140 and the memory 150 of the wafer. Next, a plurality of solders S are formed on the copper pillars C, wherein the copper pillars C are located between the solders S and the processor 140 and the memory 150. Afterwards, the processor 140 and the memory 150 are bonded to the surface treatment layer E1 located on the chip pad 118 through the solders S on the copper pillars C, so that the processor 140 and the memory 150 are electrically connected to the chip pad 118.

[0106] It should be noted that, in one embodiment, the wafer is cut into chips after the copper pillars C and the solder S are formed, so the copper pillars C and the solder S formed on the wafer before singulation can be called wafer bumping. When the wafer is singulated to form independent chips (such as the processor 140 and the memory 150), they can be directly assembled on the chip pads 118 through the solder S. In another embodiment, the wafer can also be cut into chips before the copper pillars C and the solder S are formed, which still falls within the scope of the present invention.

[0107] Next, please refer to Figure 2V , forming an underfill 160 on the reconfiguration line layer RDL to cover the copper pillars C, the solder S, the surface treatment layer E1 and the chip pads 118. Next, forming a packaging glue 170 to at least cover the processor 140 and the memory 150, wherein the packaging glue 170 covers the processor 140, the memory 150 and the underfill 160.

[0108] Next, please also refer to Figure 2V as well as Figure 2W , the temporary carrier 10 is removed to expose the fourth photosensitive dielectric layer 138, wherein the temporary carrier 10 is removed by, for example, laser debonding to expose the fourth photosensitive dielectric layer 138. Here, before removing the temporary carrier 10, a temporary carrier 20 may be selectively disposed on the encapsulation colloid 170 to increase the overall structural strength, wherein the temporary carrier 20 includes a substrate 22 and a release film 24 located on the substrate 22.

[0109] Next, please refer to Figure 2X, the fourth photosensitive dielectric layer 138 is drilled to form an opening 139 exposing a portion of the third reconfiguration circuit 132. Then, the first seed layer S1 in the third reconfiguration circuit layer 132 exposed by the opening 139 is removed by etching (see Figure 2A ), and expose a portion of the first metal layer M1 (please refer to Figure 2C ) to define a plurality of solder ball pads SP. Here, the fourth photosensitive dielectric layer 138 can be regarded as a solder mask, and the drilling process is, for example, carbon dioxide laser drilling, but is not limited thereto. Preferably, the thickness T5 of the fourth photosensitive dielectric layer 138 is, for example, 5 microns, and the aperture of the opening 139 is, for example, 245 microns to 250 microns.

[0110] Next, please refer to Figure 2Y , forming a surface treatment layer E2 on the solder ball pad SP to protect the solder ball pad SP from oxidation. Here, the material of the surface treatment layer E2 is, for example, nickel-palladium immersion gold (ENEPIG), organic solder paste (OSP) or electroless nickel immersion gold (ENIG), but is not limited thereto.

[0111] Afterwards, please also refer to Figure 2Y as well as Figure 2Z , a plurality of solder balls 180 are formed on the surface treatment layer E2 of the solder ball pads SP to electrically connect the solder ball pads SP. Finally, if a temporary carrier 20 is provided, the temporary carrier 20 can be removed to expose the encapsulation colloid 170, wherein the method of removing the temporary carrier 20 is, for example, peeling off the release film 24 to expose the encapsulation colloid 170. At this point, the production of the package structure 100a has been completed.

[0112] In terms of structure, please refer to Figure 2Z, the packaging structure 100a of this embodiment includes a reconfiguration circuit layer RDL, a chip component, a solder ball 180 and a packaging colloid 170. The reconfiguration circuit layer RDL includes a plurality of reconfiguration circuits, a plurality of photosensitive dielectric layers, a plurality of conductive vias and a plurality of chip pads 118, wherein the reconfiguration circuits and the photosensitive dielectric layers are alternately arranged, and the conductive vias penetrate the photosensitive dielectric layers and are electrically connected to the reconfiguration circuits. Further, the reconfiguration circuit layer RDL includes a first reconfiguration circuit layer 110, a second reconfiguration circuit layer 120 and a third reconfiguration circuit layer 130. The reconfiguration circuit includes a first reconfiguration circuit 112, a second reconfiguration circuit 122 and a third reconfiguration circuit 132. The photosensitive dielectric layer includes a first photosensitive dielectric layer 114, a second photosensitive dielectric layer 124, a third photosensitive dielectric layer 134 and a fourth photosensitive dielectric layer 138. The conductive vias include a first conductive via 116, a second conductive via 126 and a third conductive via 136. The first reconfiguration circuit layer 110 includes a chip pad 118, a first reconfiguration circuit 112, a first photosensitive dielectric layer 114, and a first conductive via 116 penetrating the first photosensitive dielectric layer 114. The first photosensitive dielectric layer 114 has an upper surface 117, and the chip pad 118 is electrically connected to the first reconfiguration circuit 112 through the first conductive via 116. The second reconfiguration circuit layer 120 includes a second reconfiguration circuit 122, a second photosensitive dielectric layer 124, and a second conductive via 126 penetrating the second photosensitive dielectric layer 124. The second conductive via 126 electrically connects the first reconfiguration circuit 112 and the second reconfiguration circuit 122. The third reconfiguration circuit layer 130 includes a third reconfiguration circuit 132, a third photosensitive dielectric layer 134, a fourth photosensitive dielectric layer 138, and a third conductive via 136 penetrating the third photosensitive dielectric layer 134. The third conductive via 136 electrically connects the second reconfiguration circuit 122 and the third reconfiguration circuit 132. The fourth photosensitive dielectric layer 138 covers the third photosensitive dielectric layer 134 and the third reconfiguration circuit 132 and has an opening 139. The opening 139 exposes a portion of the third reconfiguration circuit 132 to define a solder ball pad SP. Here, the reconfiguration circuit layer RDL is located at the two outermost photosensitive dielectric layers, which are the first photosensitive dielectric layer 114 and the fourth photosensitive dielectric layer 138, respectively, wherein the first photosensitive dielectric layer 114 has an upper surface 117, and the fourth photosensitive dielectric layer 138 has an opening 139.

[0113] In particular, in the present embodiment, the line width and line spacing of the reconfiguration circuit decrease from the solder ball pad SP to the chip pad 118. That is, the line width and line spacing of the third reconfiguration circuit 132 are greater than the line width and line spacing of the second reconfiguration circuit 122, and the line width and line spacing of the second reconfiguration circuit 122 are greater than the line width and line spacing of the first reconfiguration circuit 112. Preferably, the line width and line spacing of the first reconfiguration circuit 112 are, for example, 2 microns, respectively, while the line width and line spacing of the second reconfiguration circuit 122 are, for example, 5 microns, respectively, and the line width and line spacing of the third reconfiguration circuit are, for example, 10 microns, respectively. Furthermore, the thickness T1 of the first reconfiguration circuit 112 is equal to the thickness T2 of the second reconfiguration circuit 122, and the thickness T2 of the second reconfiguration circuit 122 is less than the thickness T3 of the third reconfiguration circuit 132. In addition, the depth D2 of the second conductive via 126 is equal to the depth D3 of the third conductive via 136 , and the depth D1 of the first conductive via 116 is less than the depth D2 of the second conductive via 126 .

[0114] Please refer to Figure 2Z , the chip component is disposed on the chip pad 118 and electrically connected to the chip pad 118, wherein the chip component includes a processor 140 and a memory 150, and the size of the processor 140 is larger than the size of each memory 150. In order to prevent oxidation of the chip pad 118, the package structure 100a of the present embodiment further includes a surface treatment layer E1, which is disposed on the chip pad 118. Furthermore, the package structure 100a of the present embodiment further includes a copper pillar C and a solder S, wherein the copper pillar C is disposed on the chip component and is located between the chip component and the chip pad 118, and the solder S is disposed on the copper pillar C and is located between the copper pillar C and the chip pad 118. The processor 140 and the memory 150 are electrically connected to the chip pad 118 through the copper pillar C, the solder S and the surface treatment layer E1. In order to protect the copper pillars C, the solder S, the surface treatment layer E1 and the chip pads 118, the package structure 100a of the present embodiment may further include an underfill 160 to cover the copper pillars C, the solder S, the surface treatment layer E1 and the chip pads 118. The packaging colloid 170 covers the processor 140, the memory 150 and the underfill 160, wherein the underfill 160 is arranged between the packaging colloid 170 and the reconfiguration circuit layer RDL, and the periphery of the underfill 160 is aligned with the periphery of the packaging colloid 170. Here, the periphery of the packaging colloid 170 is aligned with the periphery of the first reconfiguration circuit layer 110, the periphery of the second reconfiguration circuit layer 120 and the periphery of the third reconfiguration circuit layer 130. In addition, the solder balls 180 are respectively arranged on the solder ball pads SP and electrically connected to the solder ball pads SP.

[0115] In short, in this embodiment, the reconfiguration circuit layer RDL is first formed on the temporary carrier 10, and this temporary carrier 10 is removed after the chip component is configured on the chip pad 118. In other words, the third reconfiguration circuit 132 for subsequently forming the solder ball pad SP is first made, and then the chip pad 118 is formed. Therefore, this embodiment does not require board transfer, and the packaging structure 100a can have better structural reliability. Furthermore, because the reconfiguration circuit layer RDL is formed on the temporary carrier 10, the reconfiguration circuit layer RDL can be very hard and flat, so that the solder S between the chip component and the reconfiguration circuit layer RDL can be reflowed, which can have a higher throughput. In addition, compared to the existing package-on-package (POP), the package structure 100a formed by the chip components and the reconfiguration circuit layer RDL of this embodiment does not require stacking (that is, the processor 140 and the memory 150 can be placed on the same substrate), so it can have a lower production cost, a small package size, and the overall signal transmission path is shortened, resulting in better performance.

[0116] It must be noted that the following embodiments use the same component numbers and some contents of the previous embodiments, wherein the same number is used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the previous embodiments, and the following embodiments will not be repeated.

[0117] Figure 3 is a cross-sectional schematic diagram of a packaging structure according to another embodiment of the present invention. Figure 2Z and Figure 3 The packaging structure 100a of this embodiment is similar to the above-mentioned packaging structure 100b, and the difference between the two is that: in this embodiment, a circuit board 190 is also provided below the reconfiguration line layer RDL, wherein the processor 140 and the memory 150 can be electrically connected to the circuit board 190 through the solder balls 180.

[0118] In summary, the present invention first forms the reconfiguration circuit layer on a temporary carrier, and the temporary carrier is removed after the chip component is configured on the chip pad. In other words, the third reconfiguration circuit for subsequently forming the solder ball pad is first made, and then the chip pad is made. Therefore, the present invention does not require a transfer board, and the packaging structure can have better structural reliability. In addition, because the reconfiguration circuit layer is formed on a temporary carrier, the reconfiguration circuit layer can be very hard and flat, so that the solder between the chip component and the reconfiguration circuit layer can be reflowed, which can have a higher throughput.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A packaging structure, characterized in that: include: A reconfiguration circuit layer, comprising a plurality of reconfiguration circuits, a plurality of photosensitive dielectric layers, a plurality of conductive through holes and a plurality of chip pads, wherein the plurality of reconfiguration circuits and the plurality of photosensitive dielectric layers are alternately arranged, the plurality of conductive through holes penetrate the plurality of photosensitive dielectric layers and electrically connect the plurality of reconfiguration circuits, wherein one of the plurality of photosensitive dielectric layers located at two relatively outermost sides has an upper surface, the plurality of chip pads are located at the upper surface and electrically connected to the plurality of reconfiguration circuits through the plurality of conductive through holes, and the other of the plurality of photosensitive dielectric layers located at two relatively outermost sides has a plurality of openings, the plurality of openings expose part of the plurality of reconfiguration circuits to define a plurality of solder ball pads, and the line width and line spacing of the plurality of reconfiguration circuits decrease from the plurality of solder ball pads toward the plurality of chip pads; a chip assembly, disposed on the plurality of chip pads and electrically connected to the plurality of chip pads, wherein the chip assembly includes at least two chips with different sizes; A plurality of solder balls are respectively disposed on the plurality of solder ball pads and electrically connected to the plurality of solder ball pads; A packaging colloid, at least covering the chip component; as well as The bottom glue is arranged between the packaging glue and the reconfiguration circuit layer, wherein the periphery of the bottom glue is aligned with the periphery of the packaging glue.

2. The packaging structure according to claim 1, characterized in that: The reconfiguration circuit layer includes a first reconfiguration circuit layer, a second reconfiguration circuit layer and a third reconfiguration circuit layer, the plurality of reconfiguration circuits include a first reconfiguration circuit, a second reconfiguration circuit and a third reconfiguration circuit, the plurality of photosensitive dielectric layers include a first photosensitive dielectric layer, a second photosensitive dielectric layer, a third photosensitive dielectric layer and a fourth photosensitive dielectric layer, and the plurality of conductive vias include a plurality of first conductive vias, a plurality of second conductive vias and a plurality of third conductive vias; The first reconfiguration circuit layer includes the plurality of chip pads, the first reconfiguration circuit, the first photosensitive dielectric layer, and the plurality of first conductive vias penetrating the first photosensitive dielectric layer, the first photosensitive dielectric layer having the upper surface, and the plurality of chip pads being electrically connected to the first reconfiguration circuit through the plurality of first conductive vias; The second reconfiguration circuit layer includes the second reconfiguration circuit, the second photosensitive dielectric layer, and the plurality of second conductive vias penetrating the second photosensitive dielectric layer, wherein the plurality of second conductive vias electrically connect the first reconfiguration circuit and the second reconfiguration circuit; The third reconfiguration circuit layer includes the third reconfiguration circuit, the third photosensitive dielectric layer, the fourth photosensitive dielectric layer, and the plurality of third conductive vias penetrating the third photosensitive dielectric layer, the plurality of third conductive vias electrically connecting the second reconfiguration circuit and the third reconfiguration circuit, the fourth photosensitive dielectric layer covers the third photosensitive dielectric layer and the third reconfiguration circuit and has the plurality of openings, the plurality of openings expose a portion of the third reconfiguration circuit to define the plurality of solder ball pads, The line width and line spacing of the third reconfiguration circuit are greater than the line width and line spacing of the second reconfiguration circuit, and the line width and line spacing of the second reconfiguration circuit are greater than the line width and line spacing of the first reconfiguration circuit.

3. The packaging structure according to claim 2, characterized in that: The line width and line spacing of the first reconfiguration circuit are 2 micrometers respectively, the line width and line spacing of the second reconfiguration circuit are 5 micrometers respectively, and the line width and line spacing of the third reconfiguration circuit are 10 micrometers respectively.

4. The packaging structure according to claim 2, characterized in that: The thickness of the first reconfiguration circuit is equal to the thickness of the second reconfiguration circuit, and the thickness of the second reconfiguration circuit is less than the thickness of the third reconfiguration circuit.

5. The packaging structure according to claim 2, characterized in that: A depth of each of the plurality of second conductive vias is equal to a depth of the third conductive via, and a depth of the first conductive via is less than a depth of the second conductive via.

6. The packaging structure according to claim 2, characterized in that: The periphery of the encapsulant is aligned with the periphery of the first reconfiguration circuit layer, the periphery of the second reconfiguration circuit layer, and the periphery of the third reconfiguration circuit layer.

7. The packaging structure according to claim 1, characterized in that: Also includes: A plurality of copper pillars are disposed on the chip component and located between the chip component and the plurality of chip pads; as well as A plurality of solders are disposed on the plurality of copper pillars and located between the plurality of copper pillars and the plurality of chip pads.

8. The packaging structure according to claim 7, characterized in that: The base glue covers the copper pillars, the solders and the chip pads.

9. The packaging structure according to claim 1, characterized in that: The chip assembly includes a processor and two memories, and the size of the processor is larger than the size of each of the two memories.

10. The packaging structure according to claim 1, characterized in that: Also includes: The circuit board is arranged below the reconfiguration circuit layer, and the chip component is electrically connected to the circuit board through the plurality of solder balls.

11. A method for manufacturing a packaging structure, characterized in that: include: Forming a reconfiguration circuit layer on a temporary carrier, the reconfiguration circuit layer comprising a plurality of reconfiguration circuits, a plurality of photosensitive dielectric layers, a plurality of conductive through holes and a plurality of chip pads, the plurality of reconfiguration circuits and the plurality of photosensitive dielectric layers being alternately arranged, the plurality of conductive through holes penetrating the plurality of photosensitive dielectric layers and electrically connecting the plurality of reconfiguration circuits, wherein one of the plurality of photosensitive dielectric layers located at two relatively outermost sides has an upper surface, and the plurality of chip pads are located on the upper surface and electrically connected to the plurality of reconfiguration circuits through the plurality of conductive through holes, and the other one of the plurality of photosensitive dielectric layers located at two relatively outermost sides is directly attached to the temporary carrier; Disposing a chip assembly on the plurality of chip pads and electrically connecting the plurality of chip pads, wherein the chip assembly includes at least two chips with different sizes; forming an encapsulation colloid to at least cover the chip assembly; removing the temporary carrier after disposing the chip component on the plurality of chip pads to expose the other one of the plurality of photosensitive dielectric layers located at two opposite outermost sides; forming a plurality of openings in the other of the plurality of photosensitive dielectric layers located at two opposite outermost sides to expose a portion of the plurality of reconfiguration circuits to define a plurality of solder ball pads, wherein the line width and line spacing of the plurality of reconfiguration circuits decrease from the plurality of solder ball pads toward the plurality of chip pads; as well as A plurality of solder balls are respectively formed on the plurality of solder ball pads to electrically connect the plurality of solder ball pads.

12. The method for manufacturing a packaging structure according to claim 11, characterized in that: The reconfiguration circuit layer includes a first reconfiguration circuit layer, a second reconfiguration circuit layer, and a third reconfiguration circuit layer; the plurality of reconfiguration circuits include a first reconfiguration circuit, a second reconfiguration circuit, and a third reconfiguration circuit; the plurality of photosensitive dielectric layers include a first photosensitive dielectric layer, a second photosensitive dielectric layer, a third photosensitive dielectric layer, and a fourth photosensitive dielectric layer; the plurality of conductive vias include a plurality of first conductive vias, a plurality of second conductive vias, and a plurality of third conductive vias; and the step of forming the reconfiguration circuit layer on the temporary carrier includes: Providing the temporary carrier, wherein the temporary carrier comprises a substrate and a release film located on the substrate; forming the third reconfiguration circuit layer on the temporary carrier, wherein the third reconfiguration circuit layer includes the third reconfiguration circuit, the third photosensitive dielectric layer, the fourth photosensitive dielectric layer, and the plurality of third conductive vias penetrating the third photosensitive dielectric layer, and the fourth photosensitive dielectric layer covers the third photosensitive dielectric layer and the third reconfiguration circuit; forming the second reconfiguration circuit layer on the third reconfiguration circuit layer, the second reconfiguration circuit layer comprising the second reconfiguration circuit, the second photosensitive dielectric layer, and the plurality of second conductive vias penetrating the second photosensitive dielectric layer, the second reconfiguration circuit and the plurality of third conductive vias being formed simultaneously, and the plurality of third conductive vias electrically connecting the second reconfiguration circuit and the third reconfiguration circuit; and forming the first reconfiguration circuit layer on the second reconfiguration circuit layer, the first reconfiguration circuit layer comprising the plurality of chip pads, the first reconfiguration circuit, the first photosensitive dielectric layer, and the plurality of first conductive vias penetrating the first photosensitive dielectric layer, the first photosensitive dielectric layer having the upper surface, the plurality of chip pads being electrically connected to the first reconfiguration circuit through the plurality of first conductive vias, the first reconfiguration circuit and the plurality of second conductive vias being formed simultaneously, and the plurality of second conductive vias being electrically connected to the first reconfiguration circuit and the second reconfiguration circuit, and the plurality of chip pads and the plurality of first conductive vias being formed simultaneously; The line width and line spacing of the third reconfiguration circuit are greater than the line width and line spacing of the second reconfiguration circuit, and the line width and line spacing of the second reconfiguration circuit are greater than the line width and line spacing of the first reconfiguration circuit.

13. The method for manufacturing a packaging structure according to claim 12, characterized in that: The line width and line spacing of the first reconfiguration circuit are 2 micrometers respectively, the line width and line spacing of the second reconfiguration circuit are 5 micrometers respectively, and the line width and line spacing of the third reconfiguration circuit are 10 micrometers respectively.

14. The method for manufacturing a packaging structure according to claim 12, characterized in that: The thickness of the first reconfiguration circuit is equal to the thickness of the second reconfiguration circuit, and the thickness of the second reconfiguration circuit is less than the thickness of the third reconfiguration circuit.

15. The method for manufacturing a packaging structure according to claim 12, characterized in that: The depth of the second conductive via is equal to the depth of the third conductive via, and the depth of the first conductive via is less than the depth of the second conductive via.

16. The method for manufacturing a packaging structure according to claim 12, characterized in that: The step of forming the plurality of openings comprises: The fourth photosensitive dielectric layer is subjected to a drilling process to form the plurality of openings exposing a portion of the third reconfiguration circuit.

17. The method for manufacturing a packaging structure according to claim 11, characterized in that: Before configuring the chip assembly on the plurality of chip pads, the method further includes: forming a plurality of copper pillars on the at least two chips of the wafer; and A plurality of solders are on the plurality of copper pillars, wherein the plurality of copper pillars are located between the at least two chips and the plurality of solders.

18. The method for manufacturing a packaging structure according to claim 17, characterized in that: Before forming the encapsulation colloid to at least cover the chip assembly, the method further comprises: A primer is formed on the reconfiguration circuit layer to cover the copper pillars, the solders and the chip pads.

19. The method for manufacturing a packaging structure according to claim 11, characterized in that: The chip assembly includes a processor and two memories, and the size of the processor is larger than the size of each of the two memories.

20. The method for manufacturing a packaging structure according to claim 11, characterized in that: Also includes: A circuit board is provided below the reconfiguration circuit layer, wherein the chip component is electrically connected to the circuit board through the plurality of solder balls.

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