Silicon photomultiplier tube and preparation method thereof

Abstract

The present disclosure discloses a silicon photomultiplier tube and a preparation method thereof, which relates to the technical field of photoelectric sensors, and in particular to the technical field of single-photon detectors. The silicon photomultiplier tube comprises: a back electrode, a first-type epitaxial silicon substrate, an anti-reflection layer and an electrode, wherein the first-type epitaxial silicon substrate comprises a first-type silicon substrate layer, a first-type epitaxial layer and at least one second-type heavily doped region, wherein the first-type epitaxial layer and the at least one second-type heavily doped region form at least one three-dimensional PN junction; an inverted pyramid structure is arranged on the upper surface of the second-type heavily doped region; the anti-reflection layer is arranged on the upper surface of the first-type epitaxial silicon substrate; the electrode is arranged in the area where the anti-reflection layer does not cover the upper surface of the first-type epitaxial silicon substrate; wherein the first type and the second type are respectively one of an electron type and a hole type. The present disclosure can improve the photon detection efficiency of the silicon photomultiplier tube while reducing the operating voltage of the silicon photomultiplier tube.

Description

Technical Field

[0001] The present disclosure relates to the technical field of photoelectric sensors, and in particular to a silicon photomultiplier tube and a preparation method thereof. Background Art

[0002] Silicon photomultiplier tube (SiPM) is a single-photon detector with photon number resolution capability. Compared with traditional photomultiplier tube (PMT), SiPM works in a non-vacuum environment and is therefore not easily damaged. SiPM is small in size, unaffected by magnetic fields, has low power consumption, and has strong single-photon resolution capability. These advantages have made SiPM gradually replace PMT and become a single-photon detector with broad development prospects. It has been widely used in astrophysics, high-energy physics, lidar, nuclear medicine imaging, and other fields.

[0003] However, since silicon is an indirect bandgap material, it has a weak absorption of light, especially in the near-infrared band. To improve the photon detection efficiency of SiPM, a thicker absorption layer is required, which inevitably increases the operating voltage and cost. Therefore, how to improve the photon detection efficiency of silicon photomultiplier tubes while reducing their operating voltage has become a focus of attention. Summary of the invention

[0004] The present disclosure aims to solve one of the technical problems in the related art at least to some extent.

[0005] To this end, the first objective of the present disclosure is to provide a silicon photomultiplier tube that can improve the photon detection efficiency of the silicon photomultiplier tube while reducing the operating voltage of the silicon photomultiplier tube.

[0006] The second objective of the present disclosure is to provide a method for preparing a silicon photomultiplier tube.

[0007] To achieve the above-mentioned object, a silicon photomultiplier tube proposed in an embodiment of the first aspect of the present disclosure includes: a back electrode, a first-type epitaxial silicon substrate, an anti-reflection layer and an electrode, wherein the first-type epitaxial silicon substrate includes a first-type silicon substrate layer, a first-type epitaxial layer and at least one second-type heavily doped region, wherein:

[0008] The first type silicon substrate layer is disposed on the upper surface of the back electrode, the first type epitaxial layer is disposed on the upper surface of the first type silicon substrate layer, the at least one second type heavily doped region is disposed on the upper surface of the first type epitaxial layer, and the first type epitaxial layer and the at least one second type heavily doped region form at least one three-dimensional PN junction;

[0009] An inverted pyramid structure is provided on the upper surface of the second type heavily doped region, and the upper surface of the first type epitaxial silicon substrate includes the upper surface of the inverted pyramid structure;

[0010] The anti-reflection layer is disposed on the upper surface of the first type epitaxial silicon substrate and does not completely cover the upper surface of the first type epitaxial silicon substrate;

[0011] The electrode is disposed in a region of the upper surface of the first type epitaxial silicon substrate not covered by the anti-reflection layer, and the electrode is connected to the second type heavily doped region;

[0012] The first type and the second type are respectively one of an electron type and a hole type.

[0013] Optionally, in one embodiment of the present disclosure, the upper surface of the second type heavily doped region and the upper surface of the first type epitaxial layer constitute the upper surface of the first type epitaxial silicon substrate, the anti-reflection layer does not completely cover the upper surface of the second type heavily doped region, and the silicon photomultiplier tube further includes: a bias electrode and a quenching electrode; wherein,

[0014] The quenching electrode is arranged on the upper surface of the anti-reflection layer;

[0015] The bias electrode is disposed on the upper surface of the quenching electrode, and the bias electrode is connected to the electrode through the quenching electrode.

[0016] Optionally, in one embodiment of the present disclosure, the opening shape of the inverted pyramid structure is a square;

[0017] The anti-reflection layer is provided with an opening at the bottom position of the inverted pyramid structure, and the size of the opening is smaller than the size of the square and not larger than the area size of the second type heavily doped region.

[0018] Optionally, in one embodiment of the present disclosure, the silicon photomultiplier tube further includes: a second type heavily doped layer; wherein,

[0019] The second type heavily doped layer includes the at least one second type heavily doped region, the first type epitaxial layer includes at least one first type heavily doped region, the first type heavily doped region is arranged on the lower surface of the second type heavily doped region, and the at least one first type heavily doped region and the at least one second type heavily doped region form the at least one three-dimensional PN junction;

[0020] The upper surface of the second type heavily doped layer is the upper surface of the first type epitaxial silicon substrate, the electrode is arranged on the upper surface of the second type heavily doped layer except the first type heavily doped region, and the electrode is connected to the second type heavily doped region through the second type heavily doped layer.

[0021] Optionally, in one embodiment of the present disclosure, the back electrode includes a first metal layer and at least one second metal layer; wherein,

[0022] The first metal layer is located on the upper surface of the at least one second metal layer and is in contact with the first type silicon substrate layer;

[0023] The material of the first metal layer is different from that of the second metal layer.

[0024] Optionally, in one embodiment of the present disclosure, the electrode includes a third metal layer and a fourth metal layer; wherein,

[0025] The third metal layer is connected to the second type heavily doped region, and the fourth metal layer is connected to the second type heavily doped region through the third metal layer;

[0026] The material of the third metal layer is different from that of the fourth metal layer.

[0027] In summary, the silicon photomultiplier tube proposed in the embodiment of the first aspect of the present disclosure includes: a back electrode, a first type epitaxial silicon substrate, an anti-reflection layer and an electrode, wherein the first type epitaxial silicon substrate includes a first type silicon substrate layer, a first type epitaxial layer and at least one second type heavily doped region, wherein the first type silicon substrate layer is arranged on the upper surface of the back electrode, the first type epitaxial layer is arranged on the upper surface of the first type silicon substrate layer, the at least one second type heavily doped region is arranged on the upper surface of the first type epitaxial layer, and the first type epitaxial layer and the at least one second type heavily doped region form at least one three-dimensional PN junction; an inverted pyramid structure is arranged on the upper surface of the second type heavily doped region, and the upper surface of the first type epitaxial silicon substrate includes the upper surface of the inverted pyramid structure; the anti-reflection layer is arranged on the upper surface of the first type epitaxial silicon substrate, and does not completely cover the upper surface of the first type epitaxial silicon substrate; the electrode is arranged in the area where the anti-reflection layer does not cover the upper surface of the first type epitaxial silicon substrate, and the electrode is connected to the second type heavily doped region; wherein the first type and the second type are respectively one of an electron type and a hole type. The present invention introduces an inverted pyramid structure and realizes a three-dimensional second type heavily doped region, which can improve the absorption rate of incident light and the performance of a silicon photomultiplier tube, thereby improving the photoelectric conversion efficiency of the silicon photomultiplier tube, and further can improve the photon detection efficiency of the silicon photomultiplier tube while reducing the operating voltage of the silicon photomultiplier tube.

[0028] To achieve the above-mentioned purpose, a method for preparing a silicon photomultiplier tube is provided in a second aspect of the present disclosure, comprising:

[0029] Selecting a first type epitaxial silicon substrate, and preparing an inverted pyramid structure on the upper surface of the first type epitaxial silicon substrate;

[0030] Performing ion implantation on the upper surface of the first type epitaxial silicon substrate to form a second type heavily doped region;

[0031] preparing an anti-reflection layer on the upper surface of the first type epitaxial silicon substrate;

[0032] Corrosion-removing the anti-reflection layer in a preset area;

[0033] preparing an electrode in a region formed after the anti-reflection layer is removed by etching;

[0034] A back electrode is prepared on the lower surface of the first type epitaxial silicon substrate.

[0035] Optionally, in one embodiment of the present disclosure, preparing the inverted pyramid structure on the upper surface of the first type epitaxial silicon substrate includes:

[0036] preparing a silicon dioxide layer on the upper surface of the first type epitaxial silicon substrate;

[0037] making periodic square openings in the silicon dioxide layer;

[0038] Spin-coating photoresist on the lower surface of the first type epitaxial silicon substrate and placing it in a silicon etching solution;

[0039] The photoresist on the lower surface and the silicon oxide on the upper surface of the first type epitaxial silicon substrate are removed.

[0040] Optionally, in one embodiment of the present disclosure, ion implantation is performed on the upper surface of the first type epitaxial silicon substrate to form a second type heavily doped region, including:

[0041] Performing ion implantation at the bottom of the inverted pyramid structure to form a second type heavily doped region;

[0042] The method of removing the anti-reflection layer in a preset area by etching and removing the anti-reflection layer; and preparing an electrode in the area formed after the anti-reflection layer is removed by etching and removing the anti-reflection layer comprises:

[0043] preparing a quenching resistor at a preset position on the upper surface of the first type epitaxial silicon substrate;

[0044] Corrosion-removing the anti-reflection layer at the bottom of the inverted pyramid structure;

[0045] An electrode connecting the quenching resistor and the second type heavily doped region is prepared in the area formed after the anti-reflection layer is removed by etching, and a bias electrode is prepared on the upper surface of the quenching resistor.

[0046] Optionally, in an embodiment of the present disclosure, performing ion implantation on the upper surface of the first type epitaxial silicon substrate to form a second type heavily doped region includes:

[0047] Performing deep ion implantation below the inverted pyramid structure to form a first type heavily doped region;

[0048] Shallow ion implantation is performed on the upper surface of the first type epitaxial silicon substrate to form a second type heavily doped layer.

[0049] In summary, the method for preparing a silicon photomultiplier tube proposed in the second embodiment of the present disclosure is to select a first type epitaxial silicon substrate, and prepare an inverted pyramid structure on the upper surface of the first type epitaxial silicon substrate; perform ion implantation on the upper surface of the first type epitaxial silicon substrate to form a second type heavily doped region; prepare an anti-reflection layer on the upper surface of the first type epitaxial silicon substrate; perform etching and removal of the anti-reflection layer in a preset area; prepare an electrode in the area formed after the anti-reflection layer is corroded and removed; and prepare a back electrode on the lower surface of the first type epitaxial silicon substrate. The present disclosure can improve the absorption rate of incident light and the performance of the silicon photomultiplier tube by introducing an inverted pyramid structure and realizing a three-dimensional second type heavily doped region, thereby improving the photoelectric conversion efficiency of the silicon photomultiplier tube, and further improving the photon detection efficiency of the silicon photomultiplier tube while reducing the operating voltage of the silicon photomultiplier tube.

[0050] Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description or learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The above and / or additional aspects and advantages of the present disclosure will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0052] Figure 1 A cross-sectional schematic diagram of a first silicon photomultiplier tube provided in an embodiment of the present disclosure;

[0053] Figure 2 A working principle diagram of the first silicon photomultiplier tube provided in the embodiment of the present disclosure;

[0054] Figure 3 A cross-sectional schematic diagram of a three-dimensional PN junction provided by an embodiment of the present disclosure;

[0055] Figure 4 A top view of a first silicon photomultiplier tube provided by an embodiment of the present disclosure;

[0056] Figure 5 A cross-sectional schematic diagram of a second silicon photomultiplier tube provided in an embodiment of the present disclosure;

[0057] Figure 6 A top view of a second silicon photomultiplier tube provided by an embodiment of the present disclosure;

[0058] Figure 7 A schematic diagram of the process flow of the first silicon photomultiplier tube provided in the embodiment of the present disclosure;

[0059] Figure 8 A schematic diagram of the process flow of the second silicon photomultiplier tube provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0060] Embodiments of the present disclosure are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present disclosure, and are not to be construed as limitations of the present disclosure. On the contrary, the embodiments of the present disclosure include all changes, modifications, and equivalents that fall within the spirit and connotation of the appended claims.

[0061] The present disclosure is described in detail below with reference to specific embodiments.

[0062] A silicon photomultiplier tube provided by an embodiment of the present disclosure includes: a back electrode, a first-type epitaxial silicon substrate, an anti-reflection layer and an electrode, wherein the first-type epitaxial silicon substrate includes a first-type silicon substrate layer, a first-type epitaxial layer and at least one second-type heavily doped region, wherein:

[0063] A first type silicon substrate layer is disposed on the upper surface of the back electrode, a first type epitaxial layer is disposed on the upper surface of the first type silicon substrate layer, at least one second type heavily doped region is disposed on the upper surface of the first type epitaxial layer, and the first type epitaxial layer and the at least one second type heavily doped region form at least one three-dimensional PN junction;

[0064] An inverted pyramid structure is provided on the upper surface of the second type heavily doped region, and the upper surface of the first type epitaxial silicon substrate includes the upper surface of the inverted pyramid structure;

[0065] The anti-reflection layer is disposed on the upper surface of the first type epitaxial silicon substrate and does not completely cover the upper surface of the first type epitaxial silicon substrate;

[0066] The electrode is disposed in a region of the upper surface of the first type epitaxial silicon substrate not covered by the anti-reflection layer, and the electrode is connected to the second type heavily doped region;

[0067] The first type and the second type are respectively one of an electron type and a hole type.

[0068] According to some embodiments, when the first type and the second type are respectively one of the electron type and the hole type, the first type and the second type may not be the same type, that is, when the first type is the electron type, the second type is the hole type; when the first type is the hole type, the second type is the electron type.

[0069] According to some embodiments, the first type silicon substrate does not specifically refer to a fixed substrate. For example, the first type silicon substrate may be a P-type heavily doped P substrate with a (100) crystal plane. ++ The first type silicon substrate may also be a silicon substrate with a roughness of less than 1 nm.

[0070] In some embodiments, the first type epitaxial layer does not specifically refer to a fixed epitaxial layer. For example, the first type epitaxial layer can be a P-type lightly doped P - Epitaxial silicon. The thickness of the first type epitaxial layer may be 10-50 microns. The resistivity of the first type epitaxial layer may be 10-1000 Ω.cm.

[0071] In some embodiments, the second type heavily doped region does not specifically refer to a fixed doping region. For example, the second type heavily doped region may be an N-type heavily doped N ++ The doping concentration of the second type heavily doped region may be 10 16 -10 20 cm -3 .

[0072] In some embodiments, the anti-reflection layer does not specifically refer to a fixed anti-reflection layer. For example, the anti-reflection layer can be a silicon oxide anti-reflection layer. The thickness of the anti-reflection layer can be 10-500 nm.

[0073] It is easy to understand that the silicon photomultiplier tube provided by the present invention can improve the photoelectric conversion efficiency and the photon detection efficiency of the silicon photomultiplier tube by introducing an inverted pyramid structure and realizing a three-dimensional second type heavily doped region, and can reduce the operating voltage of the silicon photomultiplier tube. It can be used to detect single-photon level weak light signals and has the potential to become an essential optical sensor in applications that require weak light detection, such as lidar systems and near-infrared brain function imaging systems. It can be widely used in fields that require extremely weak light detection, such as lidar and near-infrared brain function imaging.

[0074] In the embodiment of the present disclosure, the upper surface of the second type heavily doped region and the upper surface of the first type epitaxial layer constitute the upper surface of the first type epitaxial silicon substrate, the anti-reflection layer does not completely cover the upper surface of the second type heavily doped region, and the silicon photomultiplier tube further includes: a bias electrode and a quenching electrode; wherein,

[0075] The quenching electrode is arranged on the upper surface of the anti-reflection layer;

[0076] The bias electrode is arranged on the upper surface of the quenching electrode, and the bias electrode is connected to the electrode through the quenching electrode.

[0077] According to some embodiments, Figure 1 Schematic diagram of the cross section of the first silicon photomultiplier tube provided by the embodiment of the present disclosure. Figure 1 As shown, the first type is hole type, the second type is electron type, and the first type silicon substrate layer is P ++ Silicon, the first type epitaxial layer is P - Epitaxial silicon, second type heavily doped region is N ++ region, and the back electrode is grounded.

[0078] In some embodiments, the structure and materials of the electrode and the bias electrode are the same. When the bias electrode is connected to the electrode through the quenching electrode, such as Figure 1 As shown, part of the electrode is in contact with silicon, and part of the electrode is not in contact with silicon. The size of the part of the electrode in contact with silicon can be 1-5 microns, and the width of the part of the electrode not in contact with silicon can be 1-3 microns.

[0079] In some embodiments, the material of the quenching resistor includes but is not limited to polysilicon, titanium dioxide, etc. The thickness of the quenching resistor may be 10-100 nm. The width of the quenching resistor may be 1-3 microns. The resistance of the quenching resistor may be 50-500 kΩ.

[0080] In some embodiments, Figure 2 This is a working principle diagram of the first silicon photomultiplier tube provided in the embodiment of the present disclosure. Figure 2 As shown in the figure, the silicon photomultiplier (SiPM) is composed of a series of avalanche photodiode (APD) micro-units working in Geiger mode in parallel. The micro-units are independent of each other. Each micro-unit includes a three-dimensional PN junction and a quenching resistor. All micro-units output signals through a common anode and a common cathode. The signal size is proportional to the number of micro-units in the excited state, that is, proportional to the number of detected photons.

[0081] In some embodiments, Figure 3 Schematic diagram of the cross section of the three-dimensional PN junction provided by the embodiment of the present disclosure. Figure 3 As shown, under the action of reverse bias, P - Epitaxial silicon P - Interface and N ++ N ++ A three-dimensional depletion region is formed between the interfaces. Compared with the traditional planar PN junction structure, the volume of the depletion region is increased, thereby improving the detection efficiency of photons without increasing the operating voltage. ++The inverted pyramid structure on the upper surface of the region can also reduce the reflection of incident light, thereby further improving the light absorption efficiency. Compared with the planar PN junction structure, this three-dimensional PN junction structure can increase the photon detection efficiency by more than 2 times.

[0082] In the embodiments of the present disclosure, according to some embodiments, Figure 4 This is a top view of the first silicon photomultiplier tube provided by the embodiment of the present disclosure. Figure 4 As shown, the opening shape of the inverted pyramid structure can be a square;

[0083] The anti-reflection layer is provided with an opening at the bottom of the inverted pyramid structure, and the size of the opening is smaller than the size of the square and not larger than the area size of the second type heavily doped region.

[0084] According to some embodiments, the side length of the square of the opening of the inverted pyramid structure may be 1-8 micrometers. The size of the opening of the anti-reflection layer at the bottom of the inverted pyramid structure may be 0.5-5 micrometers. The area size of the second type heavily doped region may be 1-8 micrometers.

[0085] In some embodiments, Figure 4 As shown, an inverted pyramid structure corresponds to a three-dimensional PN junction, and the electrodes arranged on each three-dimensional PN junction can be connected to the same bias electrode through its corresponding quenching resistor.

[0086] In the embodiment of the present disclosure, the silicon photomultiplier tube further includes: a second type heavily doped layer; wherein,

[0087] The second type heavily doped layer includes at least one second type heavily doped region, the first type epitaxial layer includes at least one first type heavily doped region, the first type heavily doped region is arranged on the lower surface of the second type heavily doped region, and the at least one first type heavily doped region and the at least one second type heavily doped region form at least one three-dimensional PN junction;

[0088] The upper surface of the second type heavily doped layer is the upper surface of the first type epitaxial silicon substrate, the electrode is arranged on the upper surface of the second type heavily doped layer except the first type heavily doped region, and the electrode is connected to the second type heavily doped region through the second type heavily doped layer.

[0089] According to some embodiments, Figure 5 Schematic diagram of a cross section of a second silicon photomultiplier tube provided by an embodiment of the present disclosure. Figure 5 As shown, the first type is hole type, the second type is electron type, and the first type silicon substrate layer is P ++ Silicon, the first type epitaxial layer is P - Epitaxial silicon, the second type heavily doped layer is N ++ Layer, N ++ The layer includes at least one N++ The second type heavily doped region is P + Area, where P + N on the upper surface of the region ++ Layer is N ++ Area. + P + Interface and N ++ N ++ A three-dimensional PN junction is formed between the interfaces. The back electrode is grounded.

[0090] In some embodiments, P ++ The doping concentration of silicon is higher than that of P + The doping concentration of the region.

[0091] In some embodiments, Figure 6 FIG. 1 is a top view of a second silicon photomultiplier tube provided in an embodiment of the present disclosure. Figure 6 As shown, the opening shape of the inverted pyramid structure can be circular. The electrode can be arranged around N ++ Around the upper surface of the layer.

[0092] In the embodiment of the present disclosure, the back electrode includes a first metal layer and at least one second metal layer; wherein,

[0093] The first metal layer is located on the upper surface of at least one second metal layer and is in contact with the first type silicon substrate layer;

[0094] The material of the first metal layer is different from the material of the second metal layer.

[0095] According to some embodiments, the material of the first metal layer includes but is not limited to metals such as titanium and chromium. The thickness of the first metal layer may be 1-10 nm.

[0096] According to some embodiments, the material of the second metal layer includes but is not limited to gold, aluminum, copper and other metals. The thickness of the second metal layer may be 100nm-2000nm. The thickness of the second metal layer may also be 50-200nm.

[0097] For example, the back electrode includes a first metal layer and two second metal layers. The first second metal layer is located on the upper surface of the second second metal layer. The material of the first second metal layer includes but is not limited to metals such as titanium and chromium, and the thickness of the first second metal layer is 100nm-2000nm. The material of the second second metal layer is gold, and the thickness of the second second metal layer is 50-200nm.

[0098] In the embodiment of the present disclosure, the electrode includes a third metal layer and a fourth metal layer; wherein,

[0099] The third metal layer is connected to the second type heavily doped region, and the fourth metal layer is connected to the second type heavily doped region through the third metal layer;

[0100] The material of the third metal layer is different from the material of the fourth metal layer.

[0101] According to some embodiments, the material of the third metal layer includes but is not limited to metals such as titanium and chromium. The thickness of the third metal layer may be 1-10 nm. The third metal layer may be directly connected to the second type heavily doped region, such as Figure 1 The third metal layer can also be connected to the second type heavily doped region through the second type heavily doped layer, as shown in FIG. Figure 5 shown.

[0102] In some embodiments, the material of the fourth metal layer includes but is not limited to metals such as gold. The thickness of the fourth metal layer may be 50 nm-300 nm.

[0103] In summary, the silicon photomultiplier tube proposed in the embodiment of the present disclosure includes: a back electrode, a first type epitaxial silicon substrate, an anti-reflection layer and an electrode, the first type epitaxial silicon substrate includes a first type silicon substrate layer, a first type epitaxial layer and at least one second type heavily doped region, wherein the first type silicon substrate layer is arranged on the upper surface of the back electrode, the first type epitaxial layer is arranged on the upper surface of the first type silicon substrate layer, at least one second type heavily doped region is arranged on the upper surface of the first type epitaxial layer, and the first type epitaxial layer and the at least one second type heavily doped region form at least one three-dimensional PN junction; an inverted pyramid structure is arranged on the upper surface of the second type heavily doped region, and the upper surface of the first type epitaxial silicon substrate includes the upper surface of the inverted pyramid structure; the anti-reflection layer is arranged on the upper surface of the first type epitaxial silicon substrate, and does not completely cover the upper surface of the first type epitaxial silicon substrate; the electrode is arranged in the area where the anti-reflection layer does not cover the upper surface of the first type epitaxial silicon substrate, and the electrode is connected to the second type heavily doped region; wherein the first type and the second type are respectively one of an electron type and a hole type. The present invention introduces an inverted pyramid structure and realizes a three-dimensional second type heavily doped region, which can improve the absorption rate of incident light and the performance of a silicon photomultiplier tube, thereby improving the photoelectric conversion efficiency of the silicon photomultiplier tube, and further can improve the photon detection efficiency of the silicon photomultiplier tube while reducing the operating voltage of the silicon photomultiplier tube.

[0104] In order to implement the above embodiment, the present disclosure also proposes a method for preparing a silicon photomultiplier tube, comprising:

[0105] S101, selecting a first type epitaxial silicon substrate, and preparing an inverted pyramid structure on the upper surface of the first type epitaxial silicon substrate;

[0106] S102, performing ion implantation on the upper surface of the first type epitaxial silicon substrate to form a second type heavily doped region;

[0107] S103, preparing an anti-reflection layer on the upper surface of the first type epitaxial silicon substrate;

[0108] S104, removing the anti-reflection layer in the preset area by etching;

[0109] S105, preparing an electrode in the area formed after the anti-reflection layer is corroded and removed;

[0110] S106, preparing a back electrode on the lower surface of the first type epitaxial silicon substrate.

[0111] According to some embodiments, before forming the inverted pyramid structure on the upper surface of the first type epitaxial silicon substrate, the first type epitaxial silicon substrate needs to be cleaned.

[0112] In an embodiment of the present disclosure, an inverted pyramid structure is prepared on the upper surface of a first type epitaxial silicon substrate, including:

[0113] Preparing a silicon dioxide layer on the upper surface of the first type epitaxial silicon substrate;

[0114] making periodic square openings in a silicon dioxide layer;

[0115] Spin-coating photoresist on the lower surface of the first type epitaxial silicon substrate and placing it in a silicon etching solution;

[0116] The photoresist on the lower surface and the silicon oxide on the upper surface of the first type epitaxial silicon substrate are removed.

[0117] In the embodiment of the present disclosure, ion implantation is performed on the upper surface of the first type epitaxial silicon substrate to form a second type heavily doped region, including:

[0118] Ion implantation is performed at the bottom of the inverted pyramid structure to form a second type heavily doped region;

[0119] The anti-reflection layer in a preset area is removed by etching; and an electrode is prepared in the area formed after the anti-reflection layer is removed by etching, including:

[0120] Preparing a quenching resistor at a preset position on the upper surface of the first type epitaxial silicon substrate;

[0121] The anti-reflection layer at the bottom of the inverted pyramid structure is removed by etching;

[0122] An electrode connecting the quenching resistor and the second type heavily doped region is prepared in the region formed after the anti-reflection layer is removed by etching, and a bias electrode is prepared on the upper surface of the quenching resistor.

[0123] Take a scenario as an example. Figure 7 The process flow diagram of the first silicon photomultiplier tube provided in the embodiment of the present disclosure is shown in FIG. Figure 7 As shown, the process includes the following steps:

[0124] S201, selecting a first type epitaxial silicon substrate whose crystal surface is a (100) crystal plane, and cleaning the substrate;

[0125] Among them, in the first type epitaxial silicon substrate, the first type silicon substrate layer is P ++ Silicon, the P ++ The resistivity of silicon is 0.001Ω.cm; in the first type epitaxial silicon substrate, the first type epitaxial layer is P - doped silicon, the P - The thickness of doped silicon is 30 microns. - The resistivity of doped silicon is 100 Ω.cm.

[0126] S202, preparing a silicon dioxide layer on the upper surface of the first type epitaxial silicon substrate by plasma enhanced chemical vapor deposition, wherein the thickness of the silicon dioxide layer is 300 nm;

[0127] According to some embodiments, plasma enhanced chemical vapor deposition (PECVD) refers to a method of depositing a desired film on a substrate by ionizing a gas containing atoms of film components with the aid of microwaves or radio frequencies, forming a plasma locally, and the plasma has strong chemical activity and is easy to react. In order to allow the chemical reaction to proceed at a lower temperature, PECVD utilizes the activity of plasma to promote the reaction, and thus this vapor deposition method is called plasma enhanced chemical vapor deposition.

[0128] S203, making periodic square openings in the silicon dioxide layer, wherein the side length of the square openings is 4 microns;

[0129] S204, spin-coating a photoresist on the back side of the first type epitaxial silicon substrate, placing the silicon wafer (the first type epitaxial silicon substrate after the photoresist is spin-coated) into a silicon etching solution, and the silicon at the exposed silicon position on the surface of the first type epitaxial silicon substrate can form an inverted pyramid structure due to anisotropic corrosion;

[0130] S205, removing the photoresist on the back side and the silicon dioxide on the front side of the first type epitaxial silicon substrate;

[0131] S206, ion implantation is performed at the bottom of the inverted pyramid structure to form N ++ Doping area, N ++ The doping concentration of the doped region is 10 19 cm -3 ,N ++ The area size of the doped region is 3 microns, followed by rapid annealing to activate the doped ions;

[0132] S207, preparing a silicon oxide anti-reflection layer on the surface of the first type epitaxial silicon substrate by PECVD, wherein the thickness of the silicon oxide anti-reflection layer is 150 nm;

[0133] S208, preparing a polysilicon quenching resistor at a specific position on the upper surface of the silicon oxide anti-reflection layer, with a thickness of 20 nm, a width of 3 microns, and a resistance of 200 kΩ.

[0134] According to some embodiments, when a polysilicon quenching resistor is prepared at a specific position on the upper surface of the silicon oxide anti-reflection layer, the specific position is a side where an electrode corresponding to a three-dimensional PN junction is connected to a bias electrode.

[0135] S209, etching and removing the silicon oxide anti-reflection layer at the bottom of the inverted pyramid structure, wherein the size of the opening formed after the etching and removal is 2 micrometers;

[0136] S210, make bias electrode and N ++ The silicon contact electrodes are connected to the two ends of the quenching resistor respectively;

[0137] According to some embodiments, the bias electrode and the electrode are both two-layer metal structures. ++ The metal in contact with silicon in the region is titanium with a thickness of 2nm; ++ The metal of the silicon contact area is gold, with a thickness of 100nm and a size of 2 microns.

[0138] S211, forming a back electrode on the back side of the first type epitaxial silicon substrate.

[0139] According to some embodiments, the back electrode is a three-layer metal structure, the metal in contact with silicon is titanium and chromium with a thickness of 10nm; the second metal layer is aluminum with a thickness of 1000nm; the third metal layer is gold with a thickness of 100nm.

[0140] In the embodiment of the present disclosure, ion implantation is performed on the upper surface of the first type epitaxial silicon substrate to form a second type heavily doped region, including:

[0141] Performing deep ion implantation below the inverted pyramid structure to form a first type heavily doped region;

[0142] Shallow ion implantation is performed on the upper surface of the first type epitaxial silicon substrate to form a second type heavily doped layer.

[0143] Take a scenario as an example. Figure 8 The process flow diagram of the second silicon photomultiplier tube provided in the embodiment of the present disclosure is shown in FIG. Figure 8 As shown, the process includes the following steps:

[0144] S301, selecting a first type epitaxial silicon substrate and performing a cleaning process on it;

[0145] Among them, in the first type epitaxial silicon substrate, the first type silicon substrate layer is P ++ Silicon, the first type epitaxial layer is P - Doped silicon.

[0146] S302, preparing a silicon dioxide layer (dielectric film) on the upper surface of the first type epitaxial silicon substrate;

[0147] S303, making periodic circular openings in the silicon dioxide layer;

[0148] S304, spin-coating photoresist on the bottom surface of the first type epitaxial silicon substrate, placing the silicon wafer in a silicon etching solution, and forming an inverted pyramid structure on the silicon exposed position of the surface of the first type epitaxial silicon substrate due to anisotropic etching;

[0149] S305, P at the bottom of the inverted pyramid structure + Ion deep implantation to form P + layer;

[0150] S306, etching the silicon dioxide layer (dielectric film) and removing the photoresist spin-coated on the bottom surface of the back electrode;

[0151] S307, performing N ++ Ion shallow implantation to form N ++ layer;

[0152] S308, in N ++ A silicon oxide anti-reflection layer is prepared on the upper surface of the layer;

[0153] S309, performing etching to open windows in the silicon oxide anti-reflection layer;

[0154] S310, preparing an electrode in a region formed by etching and opening a window in the silicon oxide anti-reflection layer;

[0155] S311, forming a back electrode on the back side of the first type epitaxial silicon substrate.

[0156] In summary, the method for preparing a silicon photomultiplier tube proposed in an embodiment of the present disclosure selects a first type epitaxial silicon substrate, and prepares an inverted pyramid structure on the upper surface of the first type epitaxial silicon substrate; performs ion implantation on the upper surface of the first type epitaxial silicon substrate to form a second type heavily doped region; prepares an anti-reflection layer on the upper surface of the first type epitaxial silicon substrate; performs etching and removal of the anti-reflection layer in a preset area; prepares an electrode in the area formed after the anti-reflection layer is removed by etching; and prepares a back electrode on the lower surface of the first type epitaxial silicon substrate. The present disclosure can improve the absorption rate of incident light and the performance of the silicon photomultiplier tube by introducing an inverted pyramid structure and realizing a three-dimensional second type heavily doped region, thereby improving the photoelectric conversion efficiency of the silicon photomultiplier tube, and further improving the photon detection efficiency of the silicon photomultiplier tube while reducing the operating voltage of the silicon photomultiplier tube.

[0157] It should be noted that, in the description of the present disclosure, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present disclosure, unless otherwise specified, the meaning of "plurality" is two or more.

[0158] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present disclosure includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present disclosure belong.

[0159] It should be understood that the various parts of the present disclosure can be implemented in hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0160] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0161] In addition, each functional unit in each embodiment of the present disclosure may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0162] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0163] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0164] Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present disclosure. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present disclosure.

Claims

1. A silicon photomultiplier tube, characterized in that: include: A back electrode, a first type epitaxial silicon substrate, an anti-reflection layer and an electrode, wherein the first type epitaxial silicon substrate comprises a first type silicon substrate layer, a first type epitaxial layer and at least one second type heavily doped region, wherein: The first type silicon substrate layer is disposed on the upper surface of the back electrode, the first type epitaxial layer is disposed on the upper surface of the first type silicon substrate layer, the at least one second type heavily doped region is disposed on the upper surface of the first type epitaxial layer, and the first type epitaxial layer and the at least one second type heavily doped region form at least one three-dimensional PN junction; An inverted pyramid structure is provided on the upper surface of the second type heavily doped region, and the upper surface of the first type epitaxial silicon substrate includes the upper surface of the inverted pyramid structure; The anti-reflection layer is disposed on the upper surface of the first type epitaxial silicon substrate and does not completely cover the upper surface of the first type epitaxial silicon substrate; The electrode is disposed in a region of the upper surface of the first type epitaxial silicon substrate not covered by the anti-reflection layer, and the electrode is connected to the second type heavily doped region; The first type and the second type are respectively one of an electron type and a hole type; Wherein, the silicon photomultiplier tube further includes: a second type heavily doped layer; the second type heavily doped layer includes the at least one second type heavily doped region, the first type epitaxial layer includes at least one first type heavily doped region, the first type heavily doped region is arranged on the lower surface of the second type heavily doped region, and the at least one first type heavily doped region and the at least one second type heavily doped region form the at least one three-dimensional PN junction; The upper surface of the second type heavily doped layer is the upper surface of the first type epitaxial silicon substrate, the electrode is arranged on the upper surface of the second type heavily doped layer except the first type heavily doped region, and the electrode is connected to the second type heavily doped region through the second type heavily doped layer.

2. The silicon photomultiplier tube according to claim 1, characterized in that: The upper surface of the second type heavily doped region and the upper surface of the first type epitaxial layer constitute the upper surface of the first type epitaxial silicon substrate, the anti-reflection layer does not completely cover the upper surface of the second type heavily doped region, and the silicon photomultiplier tube further includes: a bias electrode and a quenching electrode; wherein, The quenching electrode is arranged on the upper surface of the anti-reflection layer; The bias electrode is disposed on the upper surface of the quenching electrode, and the bias electrode is connected to the electrode through the quenching electrode.

3. The silicon photomultiplier tube according to claim 2, characterized in that: The opening shape of the inverted pyramid structure is a square; The anti-reflection layer is provided with an opening at the bottom position of the inverted pyramid structure, and the size of the opening is smaller than the size of the square and not larger than the area size of the second type heavily doped region.

4. The silicon photomultiplier tube according to claim 1, characterized in that: The back electrode comprises a first metal layer and at least one second metal layer; wherein, The first metal layer is located on the upper surface of the at least one second metal layer and is in contact with the first type silicon substrate layer; The material of the first metal layer is different from that of the second metal layer.

5. The silicon photomultiplier tube according to claim 1, characterized in that: The electrode comprises a third metal layer and a fourth metal layer; wherein, The third metal layer is connected to the second type heavily doped region, and the fourth metal layer is connected to the second type heavily doped region through the third metal layer; The material of the third metal layer is different from that of the fourth metal layer.

6. A method for preparing a silicon photomultiplier tube, characterized in that: include: Selecting a first type epitaxial silicon substrate, and preparing an inverted pyramid structure on the upper surface of the first type epitaxial silicon substrate; Performing ion implantation on the upper surface of the first type epitaxial silicon substrate to form a second type heavily doped region, wherein deep ion implantation is performed below the inverted pyramid structure to form a first type heavily doped region, and shallow ion implantation is performed on the upper surface of the first type epitaxial silicon substrate to form a second type heavily doped layer; preparing an anti-reflection layer on the upper surface of the first type epitaxial silicon substrate; Corrosion-removing the anti-reflection layer in a preset area; preparing an electrode in a region formed after the anti-reflection layer is removed by etching; A back electrode is prepared on the lower surface of the first type epitaxial silicon substrate.

7. The method according to claim 6, characterized in that The step of preparing an inverted pyramid structure on the upper surface of the first type epitaxial silicon substrate comprises: preparing a silicon dioxide layer on the upper surface of the first type epitaxial silicon substrate; making periodic square openings in the silicon dioxide layer; Spin-coating photoresist on the lower surface of the first type epitaxial silicon substrate and placing it in a silicon etching solution; The photoresist on the lower surface and the silicon oxide on the upper surface of the first type epitaxial silicon substrate are removed.

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