Method for preparing semiconductor device

Abstract

The present application discloses a method for preparing a semiconductor device, which can reduce the probability of electrical damage to the semiconductor device after heat treatment. The present application provides a method for preparing a semiconductor device, comprising the following steps: providing a substrate, the substrate comprising an active area, an insulating area, and a buried gate structure formed in the active area and the insulating area; forming a first stacking structure on the upper surface of the substrate and the buried gate structure; forming a first trench in the first stacking structure, the first trench exposing the active area and the buried gate structure in the substrate; filling the first trench with a first amorphous material filling layer, the first amorphous material filling layer being doped with at least a first doping ion, the first doping ion including at least carbon ions.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices, and in particular to a method for preparing semiconductor devices. Background Art

[0002] Semiconductor devices have been widely used in the electronics industry due to their small size, multi-functions and / or low manufacturing cost. Semiconductor devices can be divided into semiconductor memory devices that store logic data, semiconductor logic devices that process operations on logic data, and hybrid devices that have the functions of both memory devices and logic devices.

[0003] In the production process of semiconductor devices, the process flow of heat treatment of semiconductor devices is often involved. After the heat treatment process, the electrical properties of the semiconductor devices often change, resulting in some leakage currents that need to be isolated not being isolated, causing electrical damage to the semiconductor devices. Therefore, how to solve or optimize the above problems is a topic of great concern in this field. Summary of the invention

[0004] In view of this, the present application provides a method for preparing a semiconductor device, which can reduce the probability of electrical damage to the semiconductor device after heat treatment.

[0005] The present application provides a method for preparing a semiconductor device, comprising the following steps: providing a substrate, the substrate comprising an active area, an insulating area, and a buried gate structure formed in the active area and the insulating area; forming a first stacking structure on the upper surface of the substrate and the buried gate structure; forming a first trench in the first stacking structure, the first trench exposing the active area and the buried gate structure in the substrate; filling the first trench with a first amorphous material filling layer, the first amorphous material filling layer being doped with at least first doping ions, the first doping ions including at least carbon ions.

[0006] Optionally, when filling the first amorphous material filling layer in the first trench, the following steps are included: filling the first trench with the first material layer; and performing first doping ion implantation on the first material layer filled in the first trench, thereby forming the first amorphous material filling layer.

[0007] Optionally, the first doping ions further include phosphorus ions, which are provided by phosphine, and the carbon ions in the first doping ions are provided by at least one of ethylene or methane.

[0008] Optionally, doping of phosphorus ions and carbon ions is achieved by introducing phosphine and methane, and the flow rate range of phosphine is 50 sccm to 500 sccm, and the flow rate range of methane is 20 sccm to 200 sccm; and / or: the carbon ions are provided by introducing a mixed gas of ethylene and methane, and the ratio of ethylene to methane is 5:1 to 1:20.

[0009] Optionally, a first stacking structure is formed on the upper surface of the substrate and the buried gate structure based on the following steps; a first isolation layer, a second isolation layer and a third isolation layer are stacked in sequence on the upper surface of the substrate and the buried gate structure, and the material of the second isolation layer is the same as the material of the first amorphous material filling layer.

[0010] Optionally, a plurality of active regions and insulating regions are formed inside the substrate, and each of the active regions is separated by the insulating regions, and the first trench exposes the active regions and partially exposes the inside of the insulating regions.

[0011] Optionally, the material of the first amorphous material filling layer includes at least one of amorphous silicon or polycrystalline silicon.

[0012] Optionally, after filling the first amorphous material filling layer in the first groove, the following steps are also included: heat treating the first amorphous material filling layer, the heat treatment temperature is greater than or equal to 100°C, the heat treatment time is greater than or equal to 1h, and the grain size range formed after the heat treatment is 1-5nm.

[0013] Optionally, after filling the first amorphous material filling layer in the first groove, the following steps are also included: forming a second stacking structure on the surface of the first amorphous material filling layer, the second stacking structure including at least a metal material layer; forming a second groove in the first stacking structure and the second stacking structure, the projection of the second groove on the upper surface of the substrate at least partially overlaps with the projection of the first groove on the upper surface of the substrate.

[0014] Optionally, before filling the first amorphous material filling layer in the first trench, the following steps are also included: forming a second filling layer in the first trench, the concentration of the first doping ions in the second filling layer is 0, the second filling layer includes a polysilicon layer, and the upper top surface of the second filling layer is lower than the upper surface of the substrate.

[0015] In this embodiment, since the first doping ions include at least carbon ions, the presence of carbon atoms can reduce the probability of crystallization of the first amorphous material filling layer after heat treatment, thereby avoiding the probability of electrical loss of the semiconductor device after crystallization. In addition, the size of the grains can be reduced to prevent the gap problem caused by larger grains when filling the grooves, so that a groove structure with a larger aspect ratio can be formed later. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 1 is a schematic flow chart of the steps of a method for preparing a semiconductor device according to an embodiment.

[0018] Figure 2 Schematic diagram of the structure of the substrate of the semiconductor device in one embodiment.

[0019] Figure 3 FIG. 1 is a schematic diagram of a structure after a first stacking structure is formed on the upper surface of the substrate and the buried gate structure in one embodiment.

[0020] Figure 4 FIG. 4 is a schematic structural diagram of forming a first groove in the first stacking structure in an embodiment.

[0021] Figure 5 A schematic structural diagram of forming a first material layer in the first trench in one embodiment.

[0022] Figure 6 It is a schematic structural diagram of forming a first amorphous material filling layer based on the first material layer in one embodiment.

[0023] Figure 7 It is a structural schematic diagram of forming a second stacking structure based on the first stacking structure in one embodiment. DETAILED DESCRIPTION

[0024] Research has found that an important reason why semiconductor devices are prone to electrical damage after heat treatment is that the heat treatment process will cause changes in the crystal structure of some material layers in the semiconductor device, causing these material layers to reduce or eliminate the barrier to leakage current, thereby causing electrical damage to the semiconductor device. For example, after heat treatment, amorphous silicon, polycrystalline silicon, etc. are converted into single crystal silicon, which may cause the amorphous silicon, polycrystalline silicon material layer to reduce or eliminate the barrier to leakage current.

[0025] In order to solve the above problems, a method for preparing a semiconductor device is provided below to solve or optimize the above problems.

[0026] The method for preparing the semiconductor device is further described below in conjunction with the accompanying drawings and embodiments.

[0027] See also Figure 1 , is a schematic flow chart of the steps of a method for preparing a semiconductor device described in an embodiment.

[0028] In this embodiment, the method for preparing the semiconductor device includes the following steps: Step S1: providing a substrate 101, wherein the substrate 101 includes an active area 1021, an insulating area, and a buried gate structure 102 formed in the active area 1021 and the insulating area 103; Step S2: forming a first stacking structure 107 on the upper surface of the substrate 101 and the buried gate structure 102; Step S3: forming a first trench 200 in the first stacking structure 107, wherein the first trench 200 exposes the active area 1021 and the buried gate structure 102 in the substrate 101; Step S4: filling the first trench 200 with a first amorphous material filling layer 301, wherein the first amorphous material filling layer 301 is doped with at least first doping ions, wherein the first doping ions include at least carbon ions.

[0029] In this embodiment, since the first doping ions include at least carbon ions, the presence of carbon atoms can reduce the probability of crystallization of the first amorphous material filling layer 301 after heat treatment, thereby avoiding the probability of electrical loss of the semiconductor device after crystallization.

[0030] Furthermore, the size of the crystal grains can be reduced, thereby preventing the gap problem caused by larger crystal grains when filling the grooves, so that a groove structure with a larger aspect ratio can be formed subsequently.

[0031] See also Figure 2 , is a schematic structural diagram of the substrate 101 described in one embodiment.

[0032] In this embodiment, the substrate 101 includes silicon (Si), such as at least one of crystalline Si, polycrystalline silicon or amorphous Si, and may also include other semiconductor materials, such as germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) or indium phosphide (InP).

[0033] In some embodiments, the active region 1021 in the substrate 101 is a conductive region, and may be a well doped with impurities, or other structures doped with impurities.

[0034] In some embodiments, the active region 1021 may have a regular shape, such as a strip shape, and be arranged in a regular manner. A gate structure is formed in the active region 1021 .

[0035] exist Figure 2 In the illustrated embodiment, an insulating region 103 is formed in the substrate 101 to divide the active regions 1021. Each active region 1021 may be arranged at equal intervals. In some embodiments, the insulating region 103 may include a shallow trench isolation region (STI), which is composed of a shallow trench and an insulating material filled in the shallow trench. The insulating material includes at least one of insulating dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0036] exist Figure 2 In the illustrated embodiment, a buried gate structure 102 is formed in the substrate 101 , and the buried gate structure 102 includes a dielectric layer 500 , a metal nitride layer 105 , a gate electrode 104 , and a gate cap layer 106 .

[0037] In some embodiments, the gate electrode 104 can be made of a metal conductive material such as copper, tungsten, or aluminum. Figure 2 In the illustrated embodiment, the gate electrode 104 is made of metal tungsten.

[0038] In some embodiments, the dielectric layer 500 includes at least one separate material layer, and the dielectric layer 500 and the metal nitride layer 105 are disposed around the gate electrode. The dielectric layer 500 includes at least one material layer of an oxide layer, a nitride layer, and a nitride oxide layer, and the metal nitride layer 105 includes titanium nitride, etc. In some embodiments, the dielectric layer includes two material layers, wherein the first insulating material layer is a silicon dioxide layer, and the second insulating material layer is a silicon nitride (SiN x ) layer, the first insulating material layer is the outermost layer.

[0039] In some embodiments, the buried gate structure is formed in the insulating region 103 , and a dielectric layer of the buried gate structure is formed by a trench formed by a dielectric material layer in the insulating region 103 .

[0040] In some embodiments, the gate cap layer 106 may be on the gate electrode and the dielectric layer, and may be buried inside the substrate 101. The gate cap layer 106 includes at least one material layer selected from the group consisting of an oxide layer, a nitride layer, and a nitride oxide layer. Figure 2 In the embodiment shown, the gate cap layer 106 is made of silicon nitride (SiN x )layer.

[0041] The first trench 200 exposes the active area 1021 and partially exposes the interior of the buried gate structure 102. Figure 2 In the illustrated embodiment, the first trench 200 is located between two adjacent buried gate structures 102, exposing the interior of the buried gate structure 102, and is used to form a polysilicon plug electrically connected to the buried gate structure 102, and the polysilicon formed in the first trench 200 covers multiple buried gate structures 102.

[0042] In this embodiment, since the first doping ions include at least carbon ions, the crystallization probability of the first material layer 300 after high-temperature treatment can be effectively reduced, thereby reducing the size of the grains in the first material layer 300 and optimizing the aspect ratio of the groove formed after the subsequent bit line junction etching.

[0043] The study found that when the material layer is doped with carbon ions, the probability of crystallization of the material layer after high-temperature treatment is greatly reduced, which can effectively prevent the increase in the grain size of the filling material after crystallization.

[0044] In some embodiments, the first doping ions further include phosphorus ions, the phosphorus ions are provided by phosphine, and the carbon ions in the first doping ions are provided by at least one of ethylene or methane.

[0045] In some embodiments, doping of phosphorus ions and carbon ions is achieved by introducing phosphine and methane, and the flow rate range of phosphine is 50 sccm to 500 sccm, and the flow rate range of methane is 20 sccm to 200 sccm; and / or: the carbon ions are provided by introducing a mixed gas of ethylene and methane, and the ratio of ethylene to methane is 5:1 to 1:20.

[0046] In fact, carbon ions used for doping can also be provided by introducing other carbon-containing molecules. When ion doping is performed, the introduced gas is ionized to convert carbon from an atomic state to an ionic state. This can usually be achieved using an ion doping machine. The ion doping machine can be used to provide doping ions, as well as control the injection energy, injection dose, and injection direction of the doping ions. Those skilled in the art can control the above parameters by controlling the electrical parameters of the ion doping machine and the corresponding amount of precursor introduced.

[0047] In some embodiments, when the first ion doping is performed, the carbon ions are provided only by ethylene. Studies have found that the more ethylene is introduced, the smaller the particle size of the grains. Specifically, studies have found that when 0 sccm of ethylene is provided, corresponding to no carbon ions being doped in the first material layer 300, the grain size of the first material layer 300 is about 314nm; when X sccm of ethylene is provided, thereby providing carbon ions, the grain size of the first material layer 300 is 278nm; when 5X sccm of ethylene is provided, the grain size of the first material layer 300 is 67nm; when 10X sccm of ethylene is provided, the grain size of the first material layer 300 is 19nm.

[0048] Therefore, those skilled in the art can control the doping amount of the carbon ions as needed. In some embodiments, 5X sccm of ethylene is provided, thereby having a smaller grain size and less ethylene usage.

[0049] See also Figure 3 , is a schematic structural diagram after a first stacking structure 107 is formed on the upper surface of the substrate 101 in one embodiment.

[0050] In this embodiment, the first stacking structure 107 includes a first isolation layer, a second isolation layer 1084 and a third isolation layer 1085, and the first stacking structure 107 is formed on the upper surface of the substrate 101 and the buried gate structure 102 based on the following steps; the first isolation layer, the second isolation layer 1084 and the third isolation layer 1085 are stacked in sequence on the upper surface of the substrate 101 and the buried gate structure 102, and the material of the second isolation layer is the same as the material of the first amorphous material filling layer 301.

[0051] The materials of the first barrier layer, the second barrier layer 1084 and the third barrier layer 1085 are adapted to the specific purpose of the semiconductor device. In some embodiments, the semiconductor device is used to prepare a memory, so the first barrier layer, the second barrier layer 1084 and the third barrier layer 1085 can be at least one of a variety of insulating materials such as a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, etc. When the semiconductor device is used for other purposes, the first barrier layer, the second barrier layer 1084 and the third barrier layer 1085 can also be modified as needed.

[0052] exist Figure 2 In the illustrated embodiment, the first isolation layer includes three sub-layers arranged in sequence, wherein the first sub-layer 1081 is arranged on the upper surface of the substrate 101 and covers the buried gate structure, the second sub-layer 1082 is located above the first sub-layer 1081, and the third sub-layer 1083 is located above the second sub-layer 1082.

[0053] The three sequentially arranged sub-layers may be composed of at least one of a variety of insulating materials such as a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, etc. In fact, the first isolation layer may also include only one film layer, or two film layers, or more than four film layers.

[0054] See also Figure 4 , is a schematic structural diagram of forming a first groove 200 in the first stacking structure 107 in one embodiment.

[0055] In this embodiment, a first trench 200 is formed in the first stacked structure 107 , and the first trench 200 is located between two adjacent buried gate structures and partially exposes the interior of the buried gate structure.

[0056] In some embodiments, when the first amorphous material filling layer 301 is filled in the first trench 200, the following steps are included: filling the first material layer 301 in the first trench 200, see Figure 5 ; Performing a first doping ion implantation on the first material layer 300 filled in the first trench 200, thereby forming the first amorphous material filling layer 301, see here Figure 6 .

[0057] In some embodiments, at least one of physical vapor deposition, chemical vapor deposition, atomic layer deposition and the like can be used to fill the first material layer 300 in the first trench 200. In some embodiments, a low-pressure chemical vapor deposition device with silane is used to fill the first material layer 300 in the first trench 200.

[0058] In some embodiments, before or after the first doping ion implantation, the upper surface of the first material layer 300 or the first amorphous material filling layer 301 may be masked and polished using a CMP (chemical mechanical polishing) method to obtain a relatively flat upper surface of the first material layer 300 or the first amorphous material filling layer 301.

[0059] In some embodiments, the material of the first amorphous material filling layer 301 includes at least one of amorphous silicon or polycrystalline silicon. This is related to the device itself that the semiconductor structure is ultimately to form. In some embodiments, the semiconductor structure is ultimately to form a semiconductor memory device, so the first amorphous material filling layer 301 includes amorphous silicon or polycrystalline silicon, thereby forming an amorphous silicon or polycrystalline silicon plug to achieve subsequent preparation processes.

[0060] In some embodiments, after the first amorphous material filling layer 301 is filled in the first trench 200, the following steps are further included: heat treating the first amorphous material filling layer 301, the heat treatment temperature is greater than or equal to 100° C., the heat treatment time is greater than or equal to 1 h, and the grain size range formed after the heat treatment is 1 nm-5 nm. Since the first doping ions contain carbon ions, the crystallization of the amorphous silicon material or polycrystalline silicon material caused by the heat treatment process can be effectively prevented.

[0061] In some embodiments, the temperature of the heat treatment is at least 550 degrees, and the heat treatment may include multiple heat treatments, such as rapid thermal processing (RTP) at a temperature of 1025°C, and heat treatment of the etch stop layer at 630°C, and annealing at 650°C, and heat treatment of the silicon nitride mask of the bit line at 550°C.

[0062] In some embodiments, after the first amorphous material filling layer 301 is filled in the first trench 200, the following steps are further included: forming a second stacking structure 110 on the surface of the first amorphous material filling layer 301, wherein the second stacking structure 110 includes at least a metal material layer, which can be referred to herein. Figure 7 A second groove is formed in the first stacking structure 107 and the second stacking structure 110, and the projection of the second groove on the upper surface of the substrate 101 at least partially overlaps with the projection of the first groove 200 on the upper surface of the substrate 101.

[0063] In some embodiments, the metal material layer includes at least one of a titanium silicon nitride layer, a tungsten silicon layer, or a tungsten layer. The metal material layer is directly formed on the surface of the first amorphous material filling layer 301, and the first ion doping in the first amorphous material filling layer 301 can also effectively reduce the contact impedance between the interface of the first amorphous material filling layer 301 and the metal material layer.

[0064] In some embodiments, before the first amorphous material filling layer 301 is filled in the first trench 200, the following steps are also included: forming a second filling layer in the first trench 200, the concentration of the first doping ion in the second filling layer is 0, the second filling layer includes a polysilicon layer, and the upper top surface of the second filling layer is lower than the upper surface of the substrate. The polysilicon layer has good electrical characteristics, so the first trench 200 can be filled with polysilicon first to ensure the conductivity of the plug formed based on the first trench 200 when conducting. The upper top surface of the second filling layer is lower than the upper surface of the substrate 101 to ensure that there is still space for the first amorphous material filling layer 301 to be filled in the first trench 200.

[0065] The above descriptions are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structural or equivalent process transformations made using the contents of the specification and drawings of the present application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for preparing a semiconductor device, characterized in that: The following steps are involved: Providing a substrate, the substrate comprising an active region, an insulating region, and a buried gate structure formed in the active region and the insulating region; forming a first stacked structure on the upper surface of the substrate and the buried gate structure; forming a first trench in the first stacked structure, wherein the first trench exposes an active area and a buried gate structure in the substrate; A first amorphous material filling layer is filled in the first trench, the first amorphous material filling layer is doped with at least first doping ions, and the first doping ions include at least carbon ions.

2. The preparation method according to claim 1, characterized in that: When the first amorphous material filling layer is filled in the first trench, the following steps are included: Filling the first groove with a first material layer; Performing first doping ion implantation on the first material layer filled in the first trench, thereby forming the first amorphous material filling layer.

3. The preparation method according to claim 1, characterized in that: The first doping ions further include phosphorus ions, which are provided by phosphine, and the carbon ions in the first doping ions are provided by at least one of ethylene or methane.

4. The preparation method according to claim 3, characterized in that: Doping of phosphorus ions and carbon ions is achieved by introducing phosphine and methane, wherein the flow rate of phosphine is in the range of 50 sccm to 500 sccm, and the flow rate of methane is in the range of 20 sccm to 200 sccm; and / or: The carbon ions are provided by introducing a mixed gas of ethylene and methane, wherein the ratio of ethylene to methane is 5:1 to 1:

20.

5. The preparation method according to claim 1, characterized in that: Based on the following steps, a first stacked structure is formed on the upper surface of the substrate and the buried gate structure; A first isolation layer, a second isolation layer and a third isolation layer are sequentially stacked on the upper surfaces of the substrate and the buried gate structure, and the material of the second isolation layer is the same as that of the first amorphous material filling layer.

6. The preparation method according to claim 1, characterized in that: A plurality of active regions and insulating regions are formed inside the substrate, and each of the active regions is separated by the insulating regions. The first trench exposes the active regions and partially exposes the inside of the insulating regions.

7. The preparation method according to claim 1, characterized in that: The material of the first amorphous material filling layer includes at least one of amorphous silicon and polycrystalline silicon.

8. The preparation method according to claim 1, characterized in that: After the first amorphous material filling layer is filled in the first trench, the following steps are also included: The first amorphous material filling layer is heat-treated at a temperature greater than or equal to 100° C., for a time greater than or equal to 1 hour, and a grain size range of 1-5 nm is formed after the heat treatment.

9. The preparation method according to claim 1, characterized in that: After the first amorphous material filling layer is filled in the first trench, the following steps are also included: forming a second stacking structure on the surface of the first amorphous material filling layer, wherein the second stacking structure at least includes a metal material layer; A second trench is formed in the first stacked structure and the second stacked structure, and a projection of the second trench on the upper surface of the substrate at least partially overlaps with a projection of the first trench on the upper surface of the substrate.

10. The preparation method according to claim 1, characterized in that: Before filling the first amorphous material filling layer in the first trench, the following steps are also included: A second filling layer is formed in the first trench, the concentration of the first doping ions in the second filling layer is 0, the second filling layer includes a polysilicon layer, and the upper top surface of the second filling layer is lower than the upper surface of the substrate.

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