Analog-to-digital conversion circuit and quantization method for ultra-large-scale image sensor
By using multiplexed C-DAC and multiplexer in ultra-large-scale CMOS image sensors, the problem of excessive area of traditional circuits is solved, and the multiplexing of C-DAC is realized, reducing power consumption and area, and supporting high-speed and high-speed Analog-to-digital conversion of precision.
Patent Information
- Application Number
- CN202210907663.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-07-29
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2042-07-29
AI Technical Summary
The traditional successive approximation analog-to-digital conversion circuit occupies too much area in ultra-large-scale CMOS image sensors, resulting in high power consumption and cannot meet the needs of high-speed imaging.
Multiplexed C-DAC and column-level arrangements are used to multiplex C-DACs to achieve multiplexing of C-DACs through multiplexers and logic control units, providing the reference level required for all columns of SAR ADCs, reducing each Number of built-in C-DACs for column SAR ADCs.
The area and power consumption of the analog-to-digital converter is greatly reduced, and the high-speed and high-precision column reading process is realized, providing a feasible solution for ultra-large-scale CMOS image sensors.
Smart Images
Figure CN115278130B_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of analog-digital conversion, and relates to any type of column-level successive approximation analog-to-digital conversion circuit and quantization method for CMOS image sensors. Background Art
[0002] CMOS image sensors have attracted a lot of attention due to their low power consumption and fast imaging speed. With the widespread development of image sensors, higher requirements are placed on the speed and accuracy of sensors in some high-speed cameras. The traditional successive approximation analog-to-digital conversion circuit used in CMOS image sensors cannot meet the requirements due to its large area.
[0003] The traditional successive approximation analog-to-digital conversion circuit structure is shown in the attached figure. Figure 1 As shown. It includes a comparator, a sampling and holding circuit, a SAR logic control unit, and a C-DAC. The sampling and holding circuit uses the analog signal output by the column-level readout circuit. The output end of the comparator is connected to the input end of the SAR logic control unit. The output end of the SAR logic control unit is connected to the control end of the sampling and holding circuit, the control end of the comparator, and the control end of the C-DAC. The reference level is connected to the input end of the C-DAC, the positive end of the comparator is connected to the output end of the C-DAC, and the negative end of the comparator is connected to the output end of the sampling and holding circuit.
[0004] In the above-mentioned traditional successive approximation analog-to-digital converter, the SAR ADC quantization process is mainly based on a binary search algorithm. First, the collected pixel voltage is input to the negative terminal of the comparator through the sample-and-hold circuit, and at the same time, the SAR logic control unit changes the logic level of the highest bit of the C-DAC to 1, and the logic level of the remaining bits is 0. The comparator compares the collected pixel voltage with the 1 / 2Vref generated by the C-DAC. If the output of the comparator is 1, the pixel voltage is less than 1 / 2Vref, and the logic control unit sets the highest bit of the C-DAC to 0, the second highest bit to 1, and the remaining bits to 0. At this time, the logic control unit controls the C-DAC output to 1 / 4Vref; if the output of the comparator is 0, the pixel voltage is greater than 1 / 2Vref, and the logic control unit sets the highest bit of the C-DAC to 1, the second highest bit to 1, and the remaining bits to 0. At this time, the logic control circuit controls the C-DAC output to 3 / 4Vref. Then the comparator compares the next bit, and the above process is repeated until all bits of the SAR ADC are fully quantized.
[0005] For the traditional column-level SAR ADC used in ultra-large-scale CMOS image sensors, a traditional N-bit SAR ADC only needs N clock cycles to quantize a pixel voltage, while the single-slope analog-to-digital converter currently mainly used in CMOS image sensors needs 2N clock cycles to complete the quantization of N bits, which greatly improves the speed of analog-to-digital conversion. However, since each column of SAR ADC requires a C-DAC to provide a reference level for the quantization process, the huge number of capacitors leads to a significant sacrifice in area cost and power consumption. For large-array CMOS image sensors, each column of the readout circuit requires a SAR ADC for analog-to-digital conversion, which causes the analog-to-digital converter of the entire CMOS image sensor to occupy too much area, so that it cannot be applied to actual design. For the successive approximation analog-to-digital converter to be applied to the column-level readout circuit of the ultra-large-scale CMOS image sensor, it must be improved to a certain extent to reduce the area loss of the column-level SAR ADC. Summary of the invention
[0006] In view of the problems existing in the prior art, the present invention provides an analog-to-digital conversion circuit and a quantization method for a very large-scale image sensor, which solves the area problem of the existing successive approximation analog-to-digital conversion circuit, thereby realizing the application of the successive approximation analog-to-digital conversion circuit in a very large-scale CMOS image sensor.
[0007] The present invention is achieved through the following technical solutions:
[0008] An analog-to-digital conversion circuit for an ultra-large-scale image sensor, comprising a column-level readout circuit, a multiplexed C-DAC, and a plurality of SAR ADC modules arranged in a column level; the SAR ADC module comprises a register, a sampling and holding unit, a multi-channel adder, a comparator, and a SAR logic control unit;
[0009] The input end of the column-level readout circuit is connected to the pixel unit, the output ends of each level of the column-level readout circuit are connected to the input end of the sampling and holding unit of each SARADC module, the output end of the sampling and holding unit is connected to the negative end of the comparator, the reference level output end of the multiplexed C-DAC is connected to the input end of the multi-channel adder, the output end of the multi-channel adder is connected to the positive end of the comparator, the output end of the comparator is connected to the multi-channel adder and the register, the SAR logic control unit is connected to the register and the multi-channel adder, and the SAR logic control unit controls the multi-channel adder to be connected to the multiplexed C-DAC.
[0010] Preferably, output terminals of the plurality of SAR ADC modules arranged in column level are connected to a counter.
[0011] Preferably, the pixel unit is an M×N pixel array.
[0012] A quantization method for an analog-to-digital conversion circuit of a super-large-scale image sensor, wherein the sampling and holding unit inputs a pixel voltage to a negative terminal of a comparator, a SAR logic control unit sets the highest position of a digital code to 1 and the remaining positions to 0, the SAR logic control unit controls a multi-channel adder to obtain a reference level from a multiplexed C-DAC and inputs the reference level to a positive terminal of the comparator, and the comparator compares the pixel voltage with 1 / 2Vref obtained from the multiplexed C-DAC;
[0013] When the output of the comparator is 1, the pixel voltage is less than 1 / 2Vref. The SAR logic control unit sets the highest bit of the digital code to 0, the second highest bit to 1, and the remaining bits to 0 and stores them in the register. At the same time, the SAR logic control unit controls the multi-channel adder to obtain 1 / 4Vref from the multiplexed C-DAC and inputs it to the positive end of the comparator. The comparator then compares the next bit and repeats the process until all bits of the SAR ADC module are quantized.
[0014] Preferably, when the output of the comparator is 0, the pixel voltage is greater than 1 / 2Vref, and the logic control unit stores the digital code with the highest bit as 1, the second highest bit as 1, and the remaining bits as 0 into the register, and at the same time, the SAR logic control unit controls the multi-channel adder of the SAR ADC column to obtain 3 / 4Vref from the multiplexed C-DAC and input it to the positive terminal of the comparator. Then the comparator compares the next bit, and the above process is repeated until all bits of the SAR ADC module are fully quantized.
[0015] Compared with the prior art, the present invention has the following beneficial technical effects:
[0016] The present invention provides an analog-to-digital conversion circuit for a very large-scale image sensor. The C-DAC in each column of SAR ADC is extracted, and a multiplexed C-DAC provides reference levels required by all columns of SAR ADC. N built-in C-DACs required by N columns of SAR ADC modules applied to the image sensor are replaced by one multiplexed C-DAC. While maintaining the accuracy and speed advantages of the original structure, the area cost is greatly reduced compared with the traditional column-level SAR ADC, and the application of the SAR ADC module in the very large-scale CMOS image sensor is realized.
[0017] The quantization method for the analog-to-digital conversion circuit of the ultra-large-scale image sensor adopts a multiplexed C-DAC that can simultaneously provide all the required reference level values of each column SAR ADC. When SAR ADC modules of different columns obtain reference levels from the multiplexed C-DAC, they do not affect each other and are independent of each other. Each column SAR ADC module obtains the required reference level from the multiplexed C-DAC through a multi-channel adder, completes the successive approximation process through a logic control unit, realizes the reuse of C-DAC, completes the high-speed and high-precision column reading process without sacrificing a large area, greatly reduces the overall area of the chip, and reduces the column-level power consumption, providing a feasible solution for the application of column-level SAR ADC on ultra-large-scale CMOS image sensors. The quantization method is used to obtain a design scheme of a column-level SAR ADC module with a smaller area applied to CMOS image sensors, providing a specific and feasible implementation plan for the application of SAR ADC modules on ultra-large-scale CMOS image sensors. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 It is a schematic diagram of a traditional successive approximation analog-to-digital conversion circuit;
[0019] Figure 2 A schematic diagram of a column-level successive approximation analog-to-digital conversion circuit for a super-large-scale image sensor according to the present invention;
[0020] Figure 3 It is a schematic diagram for explaining the quantification process of the present invention. DETAILED DESCRIPTION
[0021] The present invention will be further described in detail below in conjunction with the accompanying drawings, which are intended to explain the present invention rather than to limit it.
[0022] like Figure 2 As shown, an analog-to-digital conversion circuit for an ultra-large-scale image sensor includes a column-level readout circuit, a multiplexed C-DAC, a counter, and a plurality of SAR ADC modules arranged at the column level;
[0023] The SAR ADC module includes a register, a sampling and holding unit, a multi-channel adder, a comparator, and a SAR logic control unit for controlling the overall logic.
[0024] The input end of the column-level readout circuit is connected to the pixel unit, the output end of the column-level readout circuit is connected to the input end of the sampling and holding unit, the output end of the sampling and holding unit is connected to the negative end of the comparator, the reference level output of the multiplexed C-DAC is connected to the input end of the multi-channel adder, the output end of the multi-channel adder is connected to the positive end of the comparator, the output end of the comparator is connected to the multi-channel adder and the register, the SAR logic control unit is connected to the register and the multi-channel adder, the SAR logic control unit controls the multi-channel adder to be connected to the multiplexed C-DAC, and the output end of the SAR ADC module is connected to the counter.
[0025] The analog-to-digital conversion circuit for ultra-large-scale CMOS image sensors, the sampling and holding circuit, the comparator and the register in the SAR ADC module are consistent with the traditional SAR ADC structure, and the column-level readout circuit and the pixel unit are consistent with the traditional structure. The difference is that the built-in C-DAC is extracted from the SAR ADC structure and replaced by a multiplexed C-DAC to provide a reference level, and a multi-way adder is added to input the reference level provided by the multiplexed C-DAC into the SAR ADC.
[0026] See also Figure 3 The working method of the analog-to-digital conversion circuit for ultra-large-scale CMOS image sensors is as follows, wherein 1 / 2nVref is a reference level value generated by the multiplexed C-DAC. Different from the working process of the column-level SAR ADC of the traditional CMOS image sensor, the working process of the present invention includes: the first step of the preparation phase, the second step of the SAR ADC sampling phase, and the third step of the SAR ADC quantization phase, which are specifically as follows:
[0027] In the first step, the preparation stage, the multiplexed C-DAC generates all the reference levels required for the entire quantization process of the column-level successive approximation analog-to-digital conversion circuit. The reference levels generated in this stage remain unchanged in the subsequent working cycle, and the various reference levels do not affect each other and are independent of each other.
[0028] It is important to note that this first stage only needs to be performed once in a workflow.
[0029] The second step is the sampling and holding stage. In this stage, the column-level readout circuit reads the analog output value of each column pixel unit, performs sampling and amplification through the sampling and holding unit, and inputs the sampled analog signal to the negative terminal of the comparator. At this time, the SAR logic control unit sets the highest position of the digital code to 1 and the remaining positions to 0. The logic control unit controls the multi-channel adder to obtain the reference level required at this time from the multiplexed C-DAC and then inputs it to the positive terminal of the comparator. The comparator compares the pixel voltage with the obtained 1 / 2Vref.
[0030] The third step is the quantization stage, which is the most important part of the whole process. The SAR logic control unit first sets the highest position of the initial value of the digital code to 1 and the other positions to 0, and controls the multi-way adder to obtain 1 / 2Vref from the multiplexed C-DAC. The comparator in the SAR ADC module compares the pixel voltage with 1 / 2Vref.
[0031] At this time, if the comparison result of the comparator is output as a high level, the analog voltage of the column is less than 1 / 2Vref, and the logic control unit sets the highest position of the digital code to 0, the second highest position to 1, and the remaining positions to 0 and stores them in the register of the SAR ADC of the column. At the same time, the logic control unit controls the multi-way adder to input 1 / 4Vref to the positive terminal of the comparator of the SAR ADC module of the column;
[0032] If the comparison result of the comparator is low, the pixel voltage is greater than 1 / 2Vref, and the logic control unit digital code sets the highest bit to 1, the second highest bit to 1, and the remaining bits to 0 and stores them in the register. At the same time, the logic control unit controls the multiplexer to obtain 3 / 4Vref from the multiplexed C-DAC and inputs it to the positive terminal of the comparator. Then the comparator compares the next bit, and the above process is repeated until all bits of the SAR ADC are fully quantized.
[0033] In this stage, the multiplexed C-DAC can provide 1 / 2nVref at the same time. The SAR ADC module controls the multi-channel adder through the logic control unit to obtain the required reference level value from the multiplexed C-DAC, and then the SAR ADC completes the successive approximation process through the logic control unit.
[0034] The analog-to-digital conversion circuit for ultra-large-scale CMOS image sensors provided by the present invention has greatly reduced area and power consumption costs compared with traditional structures, and the proposed C-DAC multiplexing method has the following advantages: first, the use of multiplexed C-DAC can reduce N-1 C-DACs in N-column SAR ADCs, greatly reducing the area of the image sensor chip occupied by the analog-to-digital converter, so that a larger column reading can be performed under the same area requirements; second, the reduction in the area of the SAR ADC module enables the SAR ADC module to be better applied in image sensors, and at the same time, a higher-speed analog-to-digital conversion is achieved compared with the single-slope analog-to-digital conversion structure commonly used in ultra-large-scale CMOS image sensors. The method proposed in this article provides a specific and feasible implementation plan for the application of the SAR ADC module in ultra-large-scale CMOS image sensors.
[0035] The analog-to-digital conversion circuit for a super-large-scale CMOS image sensor of the present invention first generates the reference level required in the entire analog-to-digital conversion process by a multiplexed C-DAC and keeps it unchanged. The SAR ADC module controls the multi-channel adder through a logic circuit to obtain the required reference level from the multiplexed C-DAC, thereby realizing the multiplexing of the C-DAC in the SAR ADC module, and completing the high-speed and high-precision column reading process without sacrificing a large area. The present invention extracts the C-DAC from the SAR ADC module, and only provides the reference level required by all SAR ADC modules through a multiplexed C-DAC, and uses the logic control circuit inside the SAR ADC module to complete the process of successive approximation, thereby realizing the multiplexing of the C-DAC, greatly reducing the overall chip area, and reducing the column-level power consumption, providing a feasible solution for the application of column-level SAR ADC in super-large-scale CMOS image sensors.
[0036] The above contents are only for explaining the technical idea of the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.
Claims
1. An analog-to-digital conversion circuit for a very large-scale image sensor, characterized in that: The invention comprises a column-level readout circuit, a multiplexed C-DAC and a plurality of SAR ADC modules arranged in a column-level manner; the SAR ADC module comprises a register, a sampling and holding unit, a multi-way adder, a comparator and a SAR logic control unit; The input end of the column-level readout circuit is connected to the pixel unit, the output ends of each level of the column-level readout circuit are connected to the input end of the sampling and holding unit of each SAR ADC module, the output end of the sampling and holding unit is connected to the negative end of the comparator, the reference level output end of the multiplexed C-DAC is connected to the input end of the multi-way adder, the output end of the multi-way adder is connected to the positive end of the comparator, the output end of the comparator is connected to the multi-way adder and the register, the SAR logic control unit is connected to the register and the multi-way adder, and the SAR logic control unit controls the multi-way adder to be connected to the multiplexed C-DAC; The multiplexed C-DAC generates the reference level required in the entire analog-to-digital conversion process and remains unchanged, and the reference levels do not affect each other and are independent of each other. The SAR ADC module controls the multi-channel adder through the logic circuit to obtain the required reference level from the multiplexed C-DAC, thereby realizing the multiplexing of the C-DAC in the SAR ADC module.
2. The analog-to-digital conversion circuit for a very large-scale image sensor according to claim 1, characterized in that: Outputs of the plurality of SAR ADC modules arranged in the column level are connected to a counter.
3. The analog-to-digital conversion circuit for a very large-scale image sensor according to claim 1, characterized in that: The pixel unit is an M×N pixel array.
4. A quantization method for an analog-to-digital conversion circuit of a super-large-scale image sensor according to any one of claims 1 to 3, characterized in that: The sampling and holding unit inputs the pixel voltage to the negative terminal of the comparator, the SAR logic control unit sets the highest position of the digital code to 1 and the other positions to 0, the SAR logic control unit controls the multi-channel adder to obtain the reference level from the multiplexed C-DAC and inputs it to the positive terminal of the comparator, and the comparator compares the pixel voltage with 1 / 2Vref obtained from the multiplexed C-DAC; When the output of the comparator is 1, the pixel voltage is less than 1 / 2Vref. The SAR logic control unit sets the highest bit of the digital code to 0, the second highest bit to 1, and the remaining bits to 0 and stores them in the register. At the same time, the SAR logic control unit controls the multi-channel adder to obtain 1 / 4Vref from the multiplexed C-DAC and inputs it to the positive end of the comparator. The comparator then compares the next bit and repeats the process until all bits of the SAR ADC module are quantized.
5. The quantization method for the analog-to-digital conversion circuit of a super-large-scale image sensor according to claim 4, characterized in that: When the output of the comparator is 0, the pixel voltage is greater than 1 / 2Vref, and the logic control unit stores the digital code with the highest bit as 1, the second highest bit as 1, and the remaining bits as 0 into the register. At the same time, the SAR logic control unit controls the multi-channel adder of the SAR ADC column to obtain 3 / 4Vref from the multiplexed C-DAC and input it to the positive end of the comparator. Then the comparator compares the next bit and repeats the above process until all bits of the SAR ADC module are quantized.