A phase-locked method and phase-locked loop suitable for impedance scanning device

Abstract

The application discloses a phase-locked method and a phase-locked loop suitable for an impedance scanning device, samples voltage of an output port of the impedance scanning device, obtains parameters of a disturbance signal according to queue data obtained through sampling, a sampling frequency and a preset reference frequency of the disturbance signal, generates a corresponding active compensation signal, compensates the voltage containing the disturbance signal, and improves phase calculation precision.

Description

TECHNICAL FIELD

[0001] The application relates to a phase-locked method and a phase-locked loop suitable for an impedance scanning device and belongs to the field of phase-locked loops. BACKGROUND

[0002] With the gradual increase of the proportion of power electronic devices in the power system, the electromagnetic oscillation problem caused by the power electronic devices is increasingly obvious, which brings a serious challenge to the safety and stability of the power system. In order to monitor the stability of the power system, some scholars have proposed an impedance scanning method, which tests the impedance characteristics of the power grid and the inverter under different frequencies by injecting different frequency disturbance signals into the power grid and the inverter, and judges the stability margin of the system by combining the Nyquist diagram method.

[0003] The disturbance injection is divided into voltage injection and current injection, and the current injection method has less influence on the power grid and the device, and therefore has more application prospects. When the disturbance current is injected, the power frequency component often needs to be controlled to control the power flow direction, but due to the existence of the disturbance signal, the phase of the conventional phase-locked calculation has an error, which finally leads to a large error in the power control. SUMMARY

[0004] The application provides a phase-locked method and a phase-locked loop suitable for an impedance scanning device, and solves the problem of the phase error of the conventional phase-locked calculation due to the existence of the disturbance signal.

[0005] In order to solve the above technical problems, the technical scheme adopted by the application is:

[0006] A phase-locked method suitable for an impedance scanning device, comprising:

[0007] sampling the voltage of the output port of the impedance scanning device;

[0008] calculating the amplitude, phase and frequency of the disturbance signal according to the sampled voltage, the sampling frequency and the preset disturbance signal reference frequency;

[0009] generating an active compensation signal according to the amplitude, phase and frequency of the disturbance signal;

[0010] compensating the sampled voltage by using the active compensation signal;

[0011] performing dq coordinate transformation on the compensated sampled voltage to calculate the phase required for phase locking.

[0012] The calculation of the amplitude, phase and frequency of the disturbance signal according to the sampled voltage, the sampling frequency and the preset disturbance signal reference frequency comprises:

[0013] performing Fourier transform on the sampled voltage;

[0014] According to the Fourier transform spectrum, the sampling frequency and the preset disturbance signal reference frequency, searching the disturbance signal in the preset search window, and determining the disturbance signal amplitude;

[0015] According to the searched disturbance signal position, determining the disturbance signal phase and frequency.

[0016] According to the Fourier transform spectrum, the sampling frequency and the preset disturbance signal reference frequency, searching the disturbance signal in the preset search window, and determining the disturbance signal amplitude formula is:

[0017] [peak,loc]=max(abs(mag(floor(f_ref / fs×N-w):ceil(f_ref / fs×N+w))))

[0018] Wherein, peak is the disturbance signal amplitude, loc is the relative index position of the disturbance signal in the search window, max is the maximum value function, abs is the absolute value function, mag is the Fourier transform spectrum, floor is the floor function, f_ref is the preset disturbance signal reference frequency, fs is the sampling frequency, N is the queue data length, w is the preset search window width, ceil is the ceiling function.

[0019] According to the searched disturbance signal position, determining the disturbance signal phase and frequency, comprising:

[0020] According to the relative index position of the searched disturbance signal in the search window, determining the absolute index position of the disturbance signal in the spectrum;

[0021] According to the absolute index position of the disturbance signal in the spectrum, determining the disturbance signal phase and frequency.

[0022] According to the relative index position of the searched disturbance signal in the search window, determining the absolute index position of the disturbance signal in the spectrum formula is:

[0023] xloc=loc+floor(f_ref / fs×N-w)-1

[0024] Wherein, loc is the relative index position of the disturbance signal in the search window, floor is the floor function, xloc is the absolute index position of the disturbance signal in the spectrum, f_ref is the preset disturbance signal reference frequency, fs is the sampling frequency, N is the queue data length, w is the preset search window width;

[0025] According to the absolute index position of the disturbance signal in the spectrum, the formula for determining the disturbance signal phase and frequency is:

[0026] θ=phase(mag(xloc))

[0027] f = (xloc-1) / N x fs

[0028] Wherein, θ is the disturbance signal phase, phase is the phase calculation function, mag is the Fourier transform of the queue data, f is the disturbance signal frequency.

[0029] The compensated sampling voltage is subjected to dq coordinate transformation, and the phase required for phase locking is calculated, including:

[0030] The compensated sampling voltage is normalized and subjected to αβ coordinate transformation.

[0031] The voltage subjected to αβ coordinate transformation is subjected to dq coordinate transformation, and the self-disturbance controller is used to track and calculate the phase required for phase locking.

[0032] The formula for dq coordinate transformation is:

[0033]

[0034] Wherein, is the result of αβ coordinate transformation, Ua, Ub, Uc are the three-phase voltages compensated and normalized, is the result of dq coordinate transformation, θ d is the phase angle output by the traditional phase-locked loop, θ q is the auxiliary phase, reflecting the error between the voltage signal amplitude and the set value.

[0035] θ d , θ q The calculation formula is:

[0036]

[0037]

[0038] Wherein, z1 is the tracking value of the controller output, z2 is the observation value of the total disturbance, b0 is the compensation factor, k p is the proportional coefficient of the self-disturbance controller, and s is the integral symbol.

[0039] A phase-locked loop suitable for impedance scanning device, comprising:

[0040] A sampling module samples the voltage at the output port of the impedance scanning device;

[0041] A disturbance signal parameter acquisition module calculates the amplitude, phase and frequency of the disturbance signal according to the voltage obtained by sampling, the sampling frequency, and the preset disturbance signal reference frequency;

[0042] A compensation signal generation module generates an active compensation signal according to the amplitude, phase and frequency of the disturbance signal;

[0043] The compensation module compensates the sampled voltage by using an active compensation signal;

[0044] The phase calculation module performs dq coordinate transformation on the compensated sampled voltage and calculates the phase required for phase locking.

[0045] The disturbance signal parameter acquisition module performs Fourier transformation on the sampled voltage, searches for the disturbance signal in a preset search window according to the Fourier-transformed frequency spectrum, the sampling frequency and a preset disturbance signal reference frequency, determines the disturbance signal amplitude, determines the disturbance signal phase and frequency according to the searched disturbance signal position.

[0046] The phase calculation module performs normalization on the compensated sampled voltage, performs αβ coordinate transformation, performs dq coordinate transformation on the αβ coordinate-transformed voltage, and uses an active disturbance rejection controller to track and calculate the phase required for phase locking.

[0047] The present application has the following beneficial effects: 1. The present application compensates the voltage containing the disturbance signal, improves the phase calculation accuracy; 2. The present application uses small-range spectrum peak search to calculate the disturbance signal amplitude, phase and frequency, so that the phase calculation result is more accurate; 3. The present application uses the active disturbance rejection controller to perform closed-loop control on the phase tracking, has better disturbance rejection performance and easier parameter setting. BRIEF DESCRIPTION OF DRAWINGS

[0048] Figure 1 The flowchart of the method of the present application is shown in FIG. 1;

[0049] Figure 2 The flowchart of the disturbance signal parameter calculation is shown in FIG. 2;

[0050] FIG. 3(a) is the voltage waveform without compensation;

[0051] FIG. 3(b) is the voltage waveform after compensation;

[0052] Figure 4 The calculation principle block diagram of θ d , θ q is shown in FIG. 4;

[0053] Figure 5 The principle block diagram of the ADRC controller is shown in FIG. 5;

[0054] FIG. 6(a) is the phase result without compensation;

[0055] FIG. 6(b) is the phase result without compensation. DETAILED DESCRIPTION

[0056] The present application will be further described below in conjunction with the accompanying drawings. The following examples are only used to more clearly illustrate the technical solutions of the present application, and cannot be used to limit the protection scope of the present application.

[0057] As shown in Figure 1 A phase-locked method suitable for impedance scanning device, comprising:

[0058] Step 1, sampling the voltage of the output port of the impedance scanning device;

[0059] Step 2, according to the voltage obtained by sampling, the sampling frequency, and the preset reference frequency of the disturbance signal, calculating the amplitude, phase and frequency of the disturbance signal;

[0060] Step 3, generating an active compensation signal according to the amplitude, phase and frequency of the disturbance signal;

[0061] Step 4, using the active compensation signal to compensate the sampled voltage;

[0062] Step 5, performing dq coordinate transformation on the compensated sampled voltage to calculate the phase required for phase locking.

[0063] The above method samples the voltage of the output port of the impedance scanning device, obtains the parameters of the disturbance signal according to the queue data obtained by sampling, the sampling frequency and the preset reference frequency of the disturbance signal, generates the corresponding active compensation signal, compensates the voltage containing the disturbance signal, and improves the phase calculation accuracy.

[0064] The voltage sampling can be performed by a voltage transformer, the sampling frequency is more than 5 times the maximum disturbance frequency, the actual sampling error should be no more than 3%, the voltage time domain signal can be obtained by sampling, the voltage time domain signal obtained by each sampling is stored in the queue, the queue is updated at the sampling frequency, the queue is updated in a first-in first-out manner, and the queue length should be greater than the sampling frequency to ensure the calculation accuracy.

[0065] According to the voltage obtained by sampling, the sampling frequency and the preset reference frequency of the disturbance signal, the amplitude, phase and frequency of the disturbance signal can be calculated, and the specific process can be as shown in Figure 2

[0066] 1) Fourier transform is performed on the voltage obtained by sampling.

[0067] mag=fft(u) / N×2

[0068] Wherein, mag is the frequency spectrum obtained after Fourier transform, fft is the fast Fourier transform function, u is the queue data, i.e. the sampled voltage, N is the length of the queue data, and a one-dimensional complex array is obtained after Fourier transform.

[0069] 2) According to the frequency spectrum after Fourier transform, the sampling frequency and the preset reference frequency of the disturbance signal, searching for the disturbance signal in the preset search window, and determining the amplitude of the disturbance signal, which can be expressed by the formula: ​

[0070] [peak, loc] = max(abs(mag(floor(f_ref / fs x N-w):ceil(f_ref / fs x N+w))))

[0071] Where, peak is the disturbance signal amplitude, loc is the relative index position of the disturbance signal in the search window, max is the maximum function, abs is the absolute value function, floor is the floor function, f_ref is the preset disturbance signal reference frequency, fs is the sampling frequency, w is the preset search window width, which can be set to 10, ceil is the ceiling function.

[0072] 3) According to the relative index position of the searched disturbance signal in the search window, the absolute index position of the disturbance signal in the frequency spectrum is determined, which can be expressed by the formula:

[0073] xloc = loc + floor(f_ref / fs x N-w)-1

[0074] Where, xloc is the absolute index position of the disturbance signal in the frequency spectrum.

[0075] 4) According to the absolute index position of the disturbance signal in the frequency spectrum, the phase of the disturbance signal is determined, which can be expressed by the formula:

[0076] θ = phase(mag(xloc))

[0077] Where, θ is the phase of the disturbance signal.

[0078] 5) According to the absolute index position of the disturbance signal in the frequency spectrum, the frequency of the disturbance signal is determined, which can be expressed by the formula:

[0079] f = (xloc-1) / N x fs

[0080] Where, f is the frequency of the disturbance signal.

[0081] Here, the sampling uses a small range (search window) spectrum peak search to calculate the disturbance signal amplitude, phase and frequency, so that the subsequent phase calculation result is more accurate.

[0082] According to the obtained disturbance signal amplitude, phase and frequency, an active compensation signal can be generated, and the sampled voltage is compensated by sampling the active compensation signal. The compensated sampled voltage is normalized, as shown in FIG. 3(a) and FIG. 3(b).

[0083] The normalized voltage is subjected to αβ coordinate transformation, which can be expressed by the formula:

[0084]

[0085] Where, Ua, Ub, Uc are the results of the coordinate transformation of Ua, Ub, Uc, and the transformation is called Clarke transformation, which is essentially to convert the time domain components of the three-phase system (in abc coordinate system) into two components in the orthogonal stationary coordinate system (aβ), Ua, Ub, Uc are the three-phase voltages after compensation and normalization.

[0086] The voltage after aβ coordinate transformation is subjected to dq coordinate transformation, and a phase for phase-locked loop is tracked and calculated by using a disturbance-rejection controller;

[0087] The formula for dq coordinate transformation can be expressed as:

[0088]

[0089] wherein, Ud, Uq are the results of further transformation of Ua, Ub, and the essence is to convert the orthogonal stationary coordinate system into the synchronous rotating coordinate system, also called dq transformation or Park transformation, which is different from the traditional dq transformation in that It can play a role in decoupling dq axis and suppressing disturbance, that is, it helps to improve the frequency coupling phenomenon caused by disturbance injection, θ d is the phase angle output by the traditional phase-locked loop, θ q is an auxiliary phase, which reflects the error between the voltage signal amplitude and the set value, and is compensated into the dq transformation, which can play a role in decoupling.

[0090] As Figure 4 shown is the calculation process of θ d , θ q , which specifically calculates θ d , θ q by using a disturbance-rejection controller, and the disturbance-rejection controller is shown in Figure 5 The calculation expression of the output u of the disturbance-rejection controller is:

[0091] u=k p (v0-z1)-z2 / b0

[0092] wherein, k p is the proportional coefficient of the disturbance-rejection controller, v0 is the input given by the disturbance-rejection controller, z1, z2 are the solutions of the state space equation, and the expression is as follows:

[0093]

[0094] wherein, z1 is the tracking value of the controller output, z2 is the observation value of the total disturbance, b0 is the compensation factor, β1, β2 are the output error correction gains, and y is the output of the controlled object.

[0095] θd , θ q may be expressed as:

[0096]

[0097] Wherein, z1, z2 are solved by state space equation, at this time the output y of the controlled object is U d , s is integral symbol;

[0098]

[0099] Wherein, z1, z2 are solved by state space equation, at this time the output y of the controlled object is U q ;

[0100] In the application, the k d of θ p =100, β1=10kp, β2=25kp 2 , the k q of θ p =200, β1=10kp, β2=25kp 2 Adopting the active disturbance rejection controller to carry out closed-loop control on phase tracking is better in disturbance rejection performance and easier in parameter setting.

[0101] In order to verify the above method, see Figure 6(a) and 6(b) By comparison, it can be seen that, after active compensation, the disturbance signal in the sampling voltage signal gradually disappears, and the phase calculation accuracy is improved.

[0102] Based on the same technical scheme, the application further discloses a corresponding phase-locked loop, a phase-locked loop suitable for an impedance scanning device, comprising:

[0103] The sampling module samples the voltage of the output port of the impedance scanning device.

[0104] The disturbance signal parameter acquisition module calculates the amplitude, phase and frequency of the disturbance signal according to the sampled voltage, sampling frequency and preset disturbance signal reference frequency.

[0105] The disturbance signal parameter acquisition module performs Fourier transform on the sampled voltage, searches for the disturbance signal in a preset search window according to the frequency spectrum after Fourier transform, the sampling frequency and the preset disturbance signal reference frequency, and determines the amplitude of the disturbance signal, and determines the phase and frequency of the disturbance signal according to the searched disturbance signal position.

[0106] The compensation signal generation module generates an active compensation signal according to the amplitude, phase and frequency of the disturbance signal.

[0107] The compensation module compensates the sampled voltage by using an active compensation signal.

[0108] The phase calculation module normalizes the compensated sampled voltage, performs an alpha-beta coordinate transformation, performs a dq coordinate transformation on the voltage after the alpha-beta coordinate transformation, and calculates the phase required for phase locking.

[0109] In the phase-locked loop, the data processing procedures and methods of the modules are consistent, and thus are not repeatedly described herein.

[0110] Based on the same technical solution, the present application provides a computer readable storage medium storing one or more programs, the one or more programs including instructions that, when executed by a computing device, cause the computing device to perform a phase locking method applicable to an impedance scanning device.

[0111] Based on the same technical solution, the present application provides a computing device including one or more processors, one or more memories, and one or more programs, wherein the one or more programs are stored in the one or more memories and configured to be executed by the one or more processors, and the one or more programs include instructions for performing a phase locking method applicable to an impedance scanning device.

[0112] Those skilled in the art will understand that embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage, etc.) containing computer-usable program code.

[0113] The present application is described with reference to flowcharts and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, as well as combinations of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing apparatus produce a device that implements the functions specified in the flowcharts and / or block diagrams. Figure 1 An apparatus for performing one or more functions specified in one or more flows and / or blocks in the flowcharts and / or block diagrams. Figure 1 An apparatus for performing one or more functions specified in one or more flows and / or blocks in the flowcharts and / or block diagrams.

[0114] These computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture including instructions which implement the flow Figure 1 The flow or flows and / or blocks Figure 1 The flow or flows and / or blocks

[0115] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions that execute on the computer or other programmable apparatus provide steps for implementing the flow Figure 1 The flow or flows and / or blocks Figure 1 The flow or flows and / or blocks

[0116] The above merely provides an embodiment of the present application, but is not intended to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall fall within the scope of the claims of the present application.

Claims

1. A phase-locked method suitable for use in an impedance-sweeping apparatus, characterized by, The method comprises the following steps: sampling the voltage at the output port of the impedance scanning device; performing Fourier transform on the sampled voltage, searching for the disturbance signal in a preset search window according to the Fourier-transformed frequency spectrum, a preset reference frequency of the disturbance signal, and determining the amplitude of the disturbance signal, and determining the phase and frequency of the disturbance signal according to the searched position of the disturbance signal; generating an active compensation signal according to the amplitude, phase and frequency of the disturbance signal; compensating the sampled voltage by using the active compensation signal; performing dq coordinate transformation on the compensated sampled voltage to calculate the phase required for phase locking.

2. A phase-locked method suitable for use in an impedance scanning apparatus according to claim 1, characterized in that, The formula for searching for the disturbance signal in the preset search window according to the Fourier-transformed frequency spectrum, the preset reference frequency of the disturbance signal and the preset search window is: [peak,loc]=max(abs(mag(floor(f_ref / fs×N-w):ceil(f_ref / fs×N+w)))) Wherein, peak is the amplitude of the disturbance signal, loc is the relative index position of the disturbance signal in the search window, max is the maximum value function, abs is the absolute value function, mag is the Fourier-transformed frequency spectrum, floor is the floor function, f_ref is the preset reference frequency of the disturbance signal, fs is the sampling frequency, N is the queue data length, w is the preset search window width, and ceil is the ceiling function.

3. A phase-locked method for use in an impedance-scan apparatus according to claim 1, characterized in that, According to the searched position of the disturbance signal, the phase and frequency of the disturbance signal are determined, which comprises: determining the absolute index position of the disturbance signal in the frequency spectrum according to the relative index position of the searched disturbance signal in the search window; determining the phase and frequency of the disturbance signal according to the absolute index position of the disturbance signal in the frequency spectrum.

4. A phase-locked method suitable for use in an impedance scanning apparatus according to claim 3, characterized in that, The formula for determining the absolute index position of the disturbance signal in the frequency spectrum according to the relative index position of the searched disturbance signal in the search window is: xloc=loc+floor(f_ref / fs×N-w)-1 Wherein, loc is the relative index position of the disturbance signal in the search window, floor is the floor function, xloc is the absolute index position of the disturbance signal in the frequency spectrum, f_ref is the preset reference frequency of the disturbance signal, fs is the sampling frequency, N is the queue data length, and w is the preset search window width. The formula for determining the phase and frequency of the disturbance signal according to the absolute index position of the disturbance signal in the frequency spectrum is: θ=phase(mag(xloc)) f=(xloc-1) / N×fs Wherein, θ is the phase of the disturbance signal, phase is the phase calculation function, mag is the Fourier-transformed queue data, and f is the frequency of the disturbance signal.

5. A phase-locked method for use in an impedance-scan apparatus according to claim 1, characterized in that, The dq coordinate transformation of the compensated sampled voltage to calculate the phase required for phase locking comprises: normalizing the compensated sampled voltage and performing αβ coordinate transformation; performing dq coordinate transformation on the voltage after αβ coordinate transformation, tracking and calculating the phase required for phase locking by using an active disturbance rejection controller.

6. A phase-locked method suitable for use in an impedance scanning apparatus according to claim 5, characterized in that, The formula for dq coordinate transformation is: wherein, is the result of the αβ coordinate transformation, Ua, Ub, Uc are the three-phase voltages compensated and normalized, is the result of the dq coordinate transformation, θ d is the phase angle output by the conventional phase-locked loop, θ q is the auxiliary phase, which reflects the error between the voltage signal amplitude and the set value.

7. A phase-locked method suitable for use in an impedance scanning apparatus according to claim 6, characterized in that, θ d , θ q The calculation formula is: wherein z1 is a tracking value outputted by the controller, z2 is an observed value of the total disturbance, b0 is a compensation factor, k p is a proportional coefficient of the active disturbance rejection controller, and s is an integral symbol.

8. A phase locked loop suitable for use in an impedance scanning device, characterized in that, The method comprises the following steps: sampling the voltage at the output port of the impedance scanning device; The disturbance signal parameter acquisition module performs Fourier transform on the sampled voltage, searches for the disturbance signal in a preset search window according to the Fourier-transformed frequency spectrum, the sampling frequency and a preset disturbance signal reference frequency, determines the disturbance signal amplitude, determines the disturbance signal phase and frequency according to the searched disturbance signal position, and generates an active compensation signal according to the disturbance signal amplitude, phase and frequency. The compensation signal generation module generates an active compensation signal according to the disturbance signal amplitude, phase and frequency. The compensation module compensates the sampled voltage by using the active compensation signal. The phase calculation module performs dq coordinate transformation on the compensated sampled voltage to calculate the phase required for phase locking.

9. A phase locked loop suitable for use in an impedance scanning device according to claim 8, characterized in that, The phase calculation module is configured to normalize the compensated sampled voltage, perform αβ coordinate transformation, perform dq coordinate transformation on the voltage after αβ coordinate transformation, and track and calculate the phase required for phase locking by using an active disturbance rejection controller.

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