Gate-controlled diode unidirectional thyristor electrostatic protection device with NMOS and manufacturing method thereof

Abstract

The invention discloses a gate-controlled diode unidirectional thyristor electrostatic protection device with NMOS and a manufacturing method thereof. The invention selects a unidirectional thyristor structure, utilizes a gate-controlled diode with a forward bias and a reverse bias embedded at both ends of a floating P+ region bridging NW / PW, the gates of the two gate-controlled diodes are connected to the bridging P+ region through a metal connecting line, wherein the N+ region of the reverse-biased gate-controlled diode D1 located in the NW is in a floating state, and the N+ region of the forward-biased diode D2 located in the PW is connected to the NMOS tube embedded in the P well, and an additional surface ESD current discharge path is provided on the basis of a traditional unidirectional thyristor electrostatic protection device, which can effectively suppress the positive feedback effect of the SCR discharge path; the thyristor rectifier electrostatic release device of the invention has the characteristics of high holding voltage and high failure current, and can achieve a high protection level while effectively avoiding the latch effect.

Description

Technical Field

[0001] The invention relates to the field of electrostatic protection, and in particular to an enhanced high-robustness thyristor electrostatic protection device and a manufacturing method thereof. Background Art

[0002] With the advancement of semiconductor manufacturing technology, the failure of integrated circuit chips and electronic products caused by ESD has become more serious. ESD protection for electronic products and integrated circuit chips has become one of the main problems faced by product engineers. The ESD design window is an issue that product engineers need to focus on when designing ESD protection, including the trigger voltage V t1 , trigger current I t1 , Maintain voltage V h , Maintaining current I h , failure voltage V t2 , Failure current I t2 , on-resistance R on The trigger voltage of the ESD protection device must be lower than the maximum withstand voltage of the protected port of the core circuit, i.e., the drain-source breakdown voltage. Usually, the trigger voltage is 10% to 20% lower than the maximum withstand voltage. The maintenance voltage of the ESD protection device must be 1.1 to 1.2 times higher than the normal working voltage of the core circuit to protect the core circuit from latching up due to the ESD protection device always being turned on. The failure current I t2 It is one of the important parameters to measure the robustness of ESD protection devices. It indicates the maximum current that the ESD protection device can withstand. If the core circuit is to be effectively protected, the failure current I t2 When the ESD protection device is on, the clamping voltage must be less than the maximum withstand voltage of the protected port; the on-resistance R on It is the resistance characteristic of the device after entering the holding point, which is related to the holding voltage V h , Maintaining current I h , failure voltage V t2 , Failure current I t2 According to Ohm's law, the on-resistance R on Expressed as failure voltage V t2 , Maintain voltage V h Difference and fault current I t2 , Maintaining current I h The ratio of the difference; the human body model HBM regards the equivalent resistance of the human body as 1.5kΩ, and the HBM protection level is 1500 times I t2 .

[0003] The failure modes caused by ESD include hard failure, soft failure, and potential failure. The causes of these failures can be divided into electrical failure and thermal failure. Thermal failure refers to the current of several amperes to tens of amperes generated locally on the chip when the ESD pulse comes. It lasts for a short time but generates a lot of heat, causing the local metal connection to melt or causing hot spots on the chip, resulting in secondary breakdown. Electrical failure refers to the electric field strength formed by the voltage applied to the gate oxide layer being greater than the dielectric strength, causing surface breakdown or dielectric breakdown. As the threat posed by ESD to chips becomes more and more serious, research on its physical mechanism is receiving more and more attention.

[0004] Compared with other ESD devices, traditional unidirectional thyristor devices have a dual conductance modulation mechanism, high discharge efficiency per unit area, small unit parasitic capacitance, and the best robustness.

[0005] The cross-section diagram of the traditional unidirectional thyristor electrostatic protection device is shown in Figure 1 , its equivalent circuit diagram is shown in Figure 2 . When an ESD pulse is applied to the anode of the unidirectional SCR, the first N-well and the first P-well form a reverse-biased PN junction. When the pulse voltage is higher than the avalanche breakdown voltage of the PN junction, a large amount of avalanche current will be generated inside the device. The current flows through the first P-well and flows to the cathode through the parasitic resistance. The voltage drop across the parasitic resistance of the first P-well is equivalent to the base voltage drop of the transistor NPN. When this voltage is higher than the forward conduction voltage of the vertical NPN transistor, the transistor is turned on. After this transistor is turned on, it provides base current for the horizontal PNP transistor. After the horizontal PNP transistor is also turned on, it further provides base current for the vertical NPN transistor, forming a positive feedback mechanism to fully open the SCR path. Therefore, even if there is no avalanche current afterwards, the large current can be discharged due to the conduction of the transistor. Summary of the invention

[0006] In order to solve the above technical problems, the present invention provides a gate-controlled diode unidirectional thyristor electrostatic protection device with NMOS and a manufacturing method thereof, and is applied to the design of an ESD protection network with an operating voltage of 0 to 5.5V.

[0007] The technical solution of the present invention to solve the above problems is:

[0008] In a first aspect, an embodiment of the present invention provides a gate-controlled diode thyristor electrostatic protection device with NMOS, comprising a P-type substrate; an N-type buried layer is provided in the P-type substrate; an N-type deep well is provided above the N-type buried layer; a first N-well and a first P-well are provided on the N-type deep well; a first N-well and a first P-well are provided on the N-type deep well in sequence from left to right; a first N+ injection, a first P+ injection, a second N+ injection, a third N+ injection and a first gate are provided on the first N-well in sequence from left to right; a second P+ injection is provided between the first N-well and the first P-well; a second gate, a fourth N+ injection, a fifth N+ injection, a third gate, a sixth N+ injection and a third P+ injection are provided in sequence from left to right in the first P-well; the first gate is between the third N+ injection and the second P+ injection, the second gate is between the second P+ injection and the fourth N+ injection, and the third gate is between the fifth N+ injection and the sixth N+ injection;

[0009] The three electrodes of the first N+ injection, the second P+ injection and the third N+ injection in the first N-well are connected together and serve as the anode of the device; the six N+ injection and the third P+ injection in the first P-well are connected together and serve as the cathode of the device; the first gate in the first shallow N-well, the second P+ injection bridged between the first N-well and the first P-well, and the second gate in the first P-well are connected together through metal wires without connecting to a potential; the fourth N+ injection, the fifth N+ injection and the third gate in the first P-well are connected together through metal wires without connecting to a potential.

[0010] Preferably, there are five field oxygen isolation regions; the first field oxygen isolation region is between the first N+ injection and the first P+ injection region, the second field oxygen isolation region is between the first P+ injection and the second N+ injection, the third field oxygen is between the second N+ injection and the third N+ injection, the fourth field oxygen is between the fourth N+ injection and the fifth N+ injection, and the fifth field oxygen is between the sixth N+ injection and the third P+ injection.

[0011] Preferably, the first field oxygen isolation region, the second field oxygen isolation region and the third field oxygen isolation region are located on the surface of the first N-well; the fourth field oxygen isolation region and the fifth field oxygen isolation region are located on the surface of the first P-well.

[0012] Preferably, when the ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, its breakdown surface is between the first N well and the second P+ injection; at this time, the third N+ injection, the first gate, and the second P+ injection constitute a reverse biased gate-controlled diode D1, the second P+ injection, the second gate, and the fourth N+ injection constitute a forward biased gate-controlled diode D2, the fifth N+ injection, the third gate, the sixth N+ injection, and the third P+ injection constitute NMOS, and when D1 is turned on, it will constitute a Gate Diode-NMOS path with D2 and NMOS.

[0013] Preferably, when the ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first P+ injection, the first N-well / first deep N-well / N-type buried layer and the first P-well constitute a parasitic transistor PNP, and the first N-well / first deep N-well / N-type buried layer, the first P-well and the sixth N+ injection constitute a parasitic transistor NPN. When the voltage drop reaches 0.7V, the parasitic transistor NPN on the right is turned on and provides base current to the parasitic transistor PNP on the left, thereby promoting its conduction. When the parasitic transistor PNP and the parasitic transistor NPN are turned on, a forward SCR path is formed, forming a positive feedback effect. At this time, the device is successfully triggered, and its breakdown surface is between the first N-well and the second P+ injection.

[0014] Preferably, when the ESD pulse reaches the anode of the device and the cathode of the device is at ground potential, after the second P+ injection / first N-well junction is broken down, the ESD current in the first N-well will converge to the third N+ injection region because the floating N+ region is heavily doped. In addition, when the ESD current enters the first P-well through the bridged second P+ injection region, a voltage is applied to the gates of the gate-controlled diodes D1 and D2.

[0015] Preferably, the width S1 of the second P+ implant is adjustable, and when S1 increases, the sustain voltage increases.

[0016] In a second aspect, an embodiment of the present invention provides a method for manufacturing a gate-controlled diode thyristor electrostatic protection device with NMOS, comprising the following steps:

[0017] Step 1: forming an N-type buried layer in a P-type substrate;

[0018] Step 2: Generate an N-type deep well above the N-type buried layer;

[0019] Step 3: generating a first N-well and a first P-well in the first N-type deep well;

[0020] Step 4: Generate a first N+ injection, a first P+ injection, a second N+ injection, a third N+ injection and a first gate on the first N well from left to right; generate a second P+ injection region between the first N well and the first P well to bridge the two wells; generate a second gate, a fourth N+ injection, a fifth N+ injection, a third gate, a sixth N+ injection and a third P+ injection on the first P well from left to right;

[0021] Step 5: forming a first field oxygen isolation region between the first N+ implantation and the first P+ implantation on the first N well, generating a second field oxygen between the first P+ implantation and the second N+ implantation on the first N well, generating a third field oxygen between the second N+ implantation and the third N+ implantation on the first N well, generating a fourth field oxygen between the fourth N+ implantation and the fifth N+ implantation on the first P well, and generating a fifth field oxygen between the sixth N+ implantation and the third P+ implantation on the first P well;

[0022] Step 6: Anneal all implanted areas to eliminate the migration of impurities in the implanted areas;

[0023] Step seven: Connect the first N+ injection, the first P+ injection, and the second N+ injection together and use them as the anode of the device, connect the first gate, the second P+ injection, and the second gate together without connecting any potential, connect the fourth N+ injection, the fifth N+ injection, and the third gate together without connecting any potential, and connect the sixth N+ injection and the third P+ injection together and use them as the cathode of the device.

[0024] Preferably, before forming the N-type buried layer in the P-type substrate, the method further comprises:

[0025] A silicon dioxide film is grown on a P-type substrate, and then a silicon nitride layer is deposited; a photoresist layer is spin-coated on the wafer, and a mask is added to expose and develop it to form an isolation shallow groove; the silicon dioxide, silicon nitride and isolation shallow groove are etched to remove the photoresist layer, a silicon dioxide layer is deposited, and then chemical mechanical polishing is performed until the silicon nitride layer is reached to remove the silicon nitride layer.

[0026] The beneficial effects of the present invention are:

[0027] 1. The present invention adjusts the breakdown surface and, based on the traditional unidirectional thyristor electrostatic protection device, introduces a second P+ injection across the first N-well and the first P-well, thereby changing the breakdown surface from the well breakdown of the first N-well and the first P-well to the junction breakdown of the first N-well and the second P+ injection, thereby effectively reducing the trigger voltage of the device and making the device easier to turn on.

[0028] 2. In order to better exert the performance of the unidirectional thyristor, the present invention introduces two gate-controlled diodes and an NMOS structure. The third N+ injection, the first gate and the second P+ injection in the first N well together constitute a reverse-biased gate-controlled diode D1. The second P+ injection, the second gate and the fourth N+ injection in the first P well together constitute a forward-biased gate-controlled diode D2. The gates of D1 and D2 are connected to the second P+ injection through a metal wire without connecting the potential. When the ESD current enters the first P well through the second P+ injection region connected across the bridge, the ESD current flows to the first P well. Applying voltage to the gates of gate-controlled diodes D1 and D2 can increase the current discharge capacity of D1 on the one hand, and increase the current conduction speed of D2 on the other hand; for D1, the RC back-flow effect formed by the gate capacitance and the P-well resistance helps to turn on the device; the fifth N+ injection, the third gate, the sixth N+ injection and the third P+ injection located in the first P-well constitute NMOS. When D1 is turned on, a part of the current will return to the cathode through D2, the metal wire between the fourth N+ injection and the fifth N+ injection, the first P-well, and the sixth N+ injection, forming a Gate Diode-NMOS path. The formation of this path will weaken the positive feedback effect of the SCR path, thereby suppressing the latch effect, and thus can increase the holding voltage of the device.

[0029] 3. The width S1 of the second P+ injection of the present invention is adjustable. When S1 increases, it is equivalent to widening the base width of the parasitic transistor NPN and the parasitic transistor PNP, thereby weakening the emitter injection effect of the parasitic transistor, suppressing the positive feedback effect of the SCR path, and maintaining the voltage increase.

[0030] 4. The width S2 of the third N+ injection and the fourth N+ injection of the present invention is adjustable, which represents the width of the N-type region of the two gate-controlled diodes. Increasing its width can effectively suppress the current saturation effect, while improving the conductivity of the gate-controlled diode, thereby further increasing the failure current and reducing the on-resistance. As S2 increases, the base width of the two parasitic transistors increases, thereby reducing the current gain coefficient β, thereby increasing the holding voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a cross-sectional view of a traditional unidirectional SCR electrostatic protection device.

[0032] Figure 2 This is the equivalent circuit diagram of the traditional unidirectional SCR electrostatic protection device.

[0033] Figure 3 It is a cross-sectional view of an embodiment of the present invention.

[0034] Figure 4 2 is an equivalent circuit diagram of an embodiment of the present invention.

[0035] Figure 5 A total current density distribution simulation diagram of a gate-controlled diode unidirectional thyristor electrostatic protection device with NMOS provided in one embodiment of the present invention. DETAILED DESCRIPTION

[0036] The ESD protection design of the analog switch chip applied to the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0037] like Figure 3 As shown, a gate-controlled diode unidirectional thyristor electrostatic protection device with NMOS includes a P-type substrate 101; an N-type buried layer 201 is provided in the substrate; an N-type deep well 301 is provided above the N-type buried layer 201; a first N-well 401 and a first P-well 402 are provided on the N-type deep well; a first N+ injection 501, a first P+ injection 502, a second N+ injection 503, a third N+ injection 504, a first P+ injection 505, a second N+ injection 506, a third N+ injection 507, a first N+ injection 508, a first N+ injection 509, a first N+ injection 510, a first N+ injection 511, a first N+ injection 512, a first N+ injection 513, a first N+ injection 514, a first N+ injection 515, a first N The gate 701; a second P+ injection 505 is provided between the first N well 401 and the first P well 402, which is connected across the two wells; the first P well 402 is provided with a second gate 702, a fourth N+ injection 506, a fifth N+ injection 507, a third gate 703, a sixth N+ injection 508, and a third P+ injection 509 from left to right; the first gate 701 is between the third N+ injection 504 and the second P+ injection 505, and the second gate 702 is between the third N+ injection 504 and the second P+ injection 505. + injection 505 and the fourth N+ injection 506, the third gate 703 is between the fifth N+ injection 507 and the sixth N+ injection 508; the first N+ injection 501, the second P+ injection 502, and the second N+ injection 503 in the first N well 401 are connected together and serve as the anode of the device; the sixth N+ 508 injection and the third P+ injection 509 in the first P well 402 are connected together and serve as the cathode of the device; the first gate 701 in the first N well 401, the second P+ injection 505 connected between the first N well 401 and the first P well 402, and the second gate 702 in the first P well 402 are connected together through metal wires, without connecting potential; the fourth N+ injection 506 in the first P well 402, the fifth N+ injection 507 and the third gate 703 are connected together through metal wires, without connecting potential; in this way, after the SCR path is turned on, a Gate will appear on the surface of the device The Diode-NMOS path will discharge part of the current in the SCR path through this path, which will suppress the positive feedback effect in the original SCR path and thus increase the holding voltage.

[0038] In one embodiment, the gate-controlled diode unidirectional thyristor electrostatic protection device with NMOS has five field oxygen isolation regions; there are five field oxygen isolation regions; the first field oxygen isolation region 601 is between the first N+ injection 501 and the first P+ injection region 502, the second field oxygen isolation region 602 is between the first P+ injection 502 and the second N+ injection 503, the third field oxygen 603 is between the second N+ injection 503 and the third N+ injection 504, the fourth field oxygen 604 is between the fourth N+ injection 506 and the fifth N+ injection 507, and the fifth field oxygen is between the sixth N+ injection 508 and the third P+ injection 509.

[0039] In one embodiment, the first field oxygen isolation region 601 , the second field oxygen isolation region 602 , and the third field oxygen isolation region 603 are located on the surface of the first N-well 401 ; the fourth field oxygen isolation region 604 and the fifth field oxygen isolation region 605 are located on the surface of the first P-well 402 .

[0040] In one embodiment, if Figure 4 As shown, when the ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, its breakdown surface is between the first N well 401 and the second P+ injection 505; at this time, the third N+ injection 504, the first gate 701, and the second P+ 505 injection constitute a reverse biased gate-controlled diode D1, the second P+ injection 505, the second gate 702 and the fourth N+ injection 506 constitute a forward biased gate-controlled diode D2, the fifth N+ injection 507, the third gate 703, the sixth N+ injection 508 and the third P+ injection 509 constitute NMOS, and when D1 is turned on, it will form a Gate Diode-NMOS path with D2 and NMOS. On the one hand, the conduction of D1 can increase the current capacity, and on the other hand, the conduction of D2 can speed up the current flowing to the first P well 402, which can increase the failure current.

[0041] When the ESD pulse reaches the anode of the device and the cathode of the device is grounded, the first P+ injection 502, the first N-well 401 / the first deep N-well 301 / the N-type buried layer 201 and the first P-well 402 constitute a longitudinal parasitic transistor PNP, and the first N-well 401 / the first deep N-well 301 / the N-type buried layer 201, the first P-well 402 and the sixth N+ 508 injection constitute a lateral parasitic transistor NPN. When the voltage drop reaches 0.7V, the right lateral parasitic transistor NPN is turned on and provides base current to the left longitudinal parasitic transistor PNP to promote its conduction. When the longitudinal parasitic transistor PNP and the lateral parasitic transistor NPN are turned on, a forward SCR path is formed, forming a positive feedback effect. At this time, the device is successfully triggered, and its breakdown surface is between the first N-well 401 and the second P+ injection 505.

[0042] When the ESD pulse reaches the anode of the device and the cathode of the device is at ground potential, after the second P+ injection 505 / first N-well 401 junction is broken down, the ESD current in the first N-well 401 will converge to the third N+ injection 504 region because the floating N+ 504 region is heavily doped. In addition, when the ESD current enters the first P-well 402 through the bridged second P+ injection 505 region, a voltage is applied to the gates of the gate-controlled diodes D1 and D2. On the one hand, the current discharge capacity of the reverse-biased gate-controlled diode D1 can be increased, and on the other hand, the conduction current speed of the forward-biased gate-controlled diode D2 can be increased. For the gate-controlled diode D1, the RC coupling effect formed by the gate capacitance and the P-well resistance helps to turn on the device.

[0043] This device can be designed according to the requirements of the ESD design window in different application scenarios. The width S1 of the second P+ injection 505 is adjustable. When S1 increases, the maintenance voltage increases; the width S2 of the third N+ injection 504 and the fourth N+ injection 506 is adjustable. Increasing their widths can effectively suppress the current saturation effect and improve the conductivity of the gate-controlled diode, thereby further increasing the failure current and reducing the on-resistance. As S2 increases, the base widths of the two parasitic transistors increase, thereby reducing the current gain coefficient β, thereby increasing the maintenance voltage.

[0044] The embodiment of the present invention further provides a method for manufacturing a gate-controlled diode unidirectional thyristor electrostatic protection device with NMOS, comprising the following steps:

[0045] Step 1: forming an N-type buried layer 201 in a P-type substrate 101;

[0046] Step 2: generating an N-type deep well 301 above the N-type buried layer 201;

[0047] Step 3: generating a first N-well 401 and a first P-well 402 in the first N-type deep well 301;

[0048] Step 4: Generate the first N+ 501 injection, the first P+ injection 502, the second N+ injection 503, the third N+ injection 504 and the first gate 701 from left to right on the first N well 401; generate a second P+ injection region 505 between the first N well 401 and the first P well 402 to bridge the two wells; generate the second gate 702, the fourth N+ injection 506, the fifth N+ injection 507, the third gate 7003, the sixth N+ injection 508 and the third P+ injection 509 from left to right on the first P well 402;

[0049] Step 5: forming a first field oxygen isolation region 601 between the first N+ implant 501 and the first P+ implant 502 on the first N well 401, generating a second field oxygen 602 between the first P+ implant 502 and the second N+ implant 503 on the first N well 401, generating a third field oxygen 603 between the second N+ implant 503 and the third N+ implant 504 on the first N well 401, generating a fourth field oxygen 604 between the fourth N+ implant 506 and the fifth N+ implant 507 on the first P well 402, and generating a fifth field oxygen 605 between the sixth N+ implant 508 and the third P+ implant 509 on the first P well 402;

[0050] Step 6: Anneal all implanted areas to eliminate the migration of impurities in the implanted areas;

[0051] Step 7: Connect the first N+ injection 501, the first P+ injection 502, and the second N+ injection 503 together and use them as the anode of the device, connect the first gate 701, the second P+ injection 505, and the second gate 702 together without connecting to a potential, connect the fourth N+ injection 506, the fifth N+ injection 507, and the third gate 703 together without connecting to a potential, and connect the sixth N+ injection 508 and the third P+ injection 509 together and use them as the cathode of the device;

[0052] The manufacturing method of the gate-controlled diode unidirectional thyristor electrostatic protection device with NMOS of the present invention is simple and easy to operate. In order to better exert the performance of the unidirectional thyristor, the two gate-controlled diodes and NMOS structure introduced in the present invention generate a new surface path that weakens the positive feedback effect of the SCR path, thereby suppressing the latch effect, and can effectively improve the protection performance and failure level of the device. The device can be used in the ESD protection design of the I / O port of 0-5.5V. The example device of the present invention adopts a 0.25μm BCDMOS process.

[0053] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A gate-controlled diode unidirectional thyristor electrostatic protection device with NMOS, characterized in that: including a P-type substrate; An N-type buried layer is provided in the P-type substrate; An N-type deep well is located above the N-type buried layer; The N-type deep well is provided with a first N-well and a first P-well; The N-type deep well is provided with a first N-well and a first P-well from left to right in sequence; the first N-well is provided with a first N+ injection region, a first P+ injection region, a second N+ injection region, a third N+ injection region and a first gate from left to right in sequence; a second P+ injection region is provided between the first N-well and the first P-well; the first P-well is provided with a second gate, a fourth N+ injection region, a fifth N+ injection region, a third gate, a sixth N+ injection region and a third P+ injection region from left to right in sequence; The first gate is between the third N+ injection region and the second P+ injection region, the second gate is between the second P+ injection region and the fourth N+ injection region, and the third gate is between the fifth N+ injection region and the sixth N+ injection region; The first N+ injection region, the second P+ injection region and the third N+ injection region in the first N well are connected together and serve as the anode of the device; the sixth N+ injection region and the third P+ injection region in the first P well are connected together and serve as the cathode of the device; the first gate in the first N well, the second P+ injection region connected across the first N well and the first P well, and the second gate in the first P well are connected together through metal wires and are not connected to a potential; The fourth N+ injection region in the first P well, the fifth N+ injection region and the third gate are connected together through a metal wire and are not connected to a potential; It also includes five field oxygen isolation zones; The first field oxygen isolation zone is between the first N+ injection zone and the first P+ injection zone, the second field oxygen isolation zone is between the first P+ injection zone and the second N+ injection zone, the third field oxygen isolation zone is between the second N+ injection zone and the third N+ injection zone, the fourth field oxygen isolation zone is between the fourth N+ injection zone and the fifth N+ injection zone, and the fifth field oxygen isolation zone is between the sixth N+ injection zone and the third P+ injection zone.

2. The field oxygen isolation region according to claim 1, characterized in that: The first field oxygen isolation region, the second field oxygen isolation region, and the third field oxygen isolation region are located on the surface of the first N-well; the fourth field oxygen isolation region and the fifth field oxygen isolation region are located on the surface of the first P-well.

3. The gate-controlled diode unidirectional thyristor electrostatic protection device with NMOS according to claim 1, characterized in that: When the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, its breakdown surface is between the first N well and the second P+ injection region; at this time, the third N+ injection region, the first gate, and the second P+ injection region constitute a reverse-biased gate-controlled diode D1, the second P+ injection region, the second gate, and the fourth N+ injection region constitute a forward-biased gate-controlled diode D2, and the fifth N+ injection region, the third gate, the sixth N+ injection region, and the third P+ injection region constitute NMOS. When D1 is turned on, it will form a Gate Diode-NMOS path with D2 and the NMOS tube.

4. The gate-controlled diode unidirectional thyristor electrostatic protection device with NMOS according to claim 1, characterized in that: When the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first P+ injection region, the first N-well / first deep N-well / N-type buried layer and the first P-well constitute a parasitic transistor PNP, and the first N-well / first deep N-well / N-type buried layer, the first P-well and the sixth N+ injection region constitute a parasitic transistor NPN. When the voltage drop reaches 0.7V, the parasitic transistor NPN on the right is turned on and provides base current to the parasitic transistor PNP on the left, thereby promoting its conduction. When the parasitic transistor PNP and the parasitic transistor NPN are turned on, a forward SCR path is formed, forming a positive feedback effect. At this time, the device is successfully triggered, and its breakdown surface is between the first N-well and the second P+ injection region.

5. The gate-controlled diode unidirectional thyristor electrostatic protection device with NMOS according to claim 1, characterized in that: When a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is at ground potential, after the second P+ injection region / first N-well junction is broken down, the ESD current in the first N-well will converge to the third N+ injection region because the floating N+ region is heavily doped. In addition, when the ESD current enters the first P-well through the bridged second P+ injection region, a voltage is applied to the gates of the gate-controlled diodes D1 and D2; on the one hand, the capacity of the current flowing through the third N+ injection region of the gate-controlled diode D1 can be increased, and on the other hand, the conduction of D2 can speed up the speed at which the current passes through the gate-controlled diode D2, which can increase the failure current of the device to a certain extent.

6. The gate-controlled diode unidirectional thyristor electrostatic protection device with NMOS according to claim 1, characterized in that: The width S1 of the second P+ implantation region is adjustable, and when S1 increases, the sustaining voltage increases.

7. A method for manufacturing a gate-controlled diode unidirectional thyristor electrostatic protection device with NMOS according to any one of claims 1 to 6, comprising the following steps: Step 1: forming an N-type buried layer in a P-type substrate; Step 2: Generate an N-type deep well above the N-type buried layer; Step 3: generating a first N-well and a first P-well in the first N-type deep well; Step 4: Generate a first N+ implantation region, a first P+ implantation region, a second N+ implantation region, a third N+ implantation region and a first gate on the first N well from left to right; A second P+ implantation region is generated between the first N well and the first P well, bridging the two wells; On the first P well, a second gate, a fourth N+ injection region, a fifth N+ injection region, a third gate, a sixth N+ injection region and a third P+ injection region are sequentially generated from left to right; Step 5: forming a first field oxygen isolation region between the first N+ implantation region and the first P+ implantation region on the first N well, generating a second field oxygen isolation region between the first P+ implantation region and the second N+ implantation region on the first N well, generating a third field oxygen isolation region between the second N+ implantation region and the third N+ implantation region on the first N well, generating a fourth field oxygen isolation region between the fourth N+ implantation region and the fifth N+ implantation region on the first P well, and generating a fifth field oxygen isolation region between the sixth N+ implantation region and the third P+ implantation region on the first P well; Step 6: Anneal all implanted areas to eliminate the migration of impurities in the implanted areas; Step seven: Connect the first N+ injection region, the first P+ injection region, and the second N+ injection region together and use them as the anode of the device, connect the first gate, the second P+ injection region, and the second gate together without connecting any potential, connect the fourth N+ injection region, the fifth N+ injection region, and the third gate together without connecting any potential, and connect the sixth N+ injection region and the third P+ injection region together and use them as the cathode of the device.

8. The method for manufacturing a gate-controlled diode unidirectional thyristor electrostatic protection device with NMOS according to claim 7, characterized in that: The following steps are also included before step one: growing a layer of silicon dioxide film on a P-type substrate, and then depositing a layer of silicon nitride; spin-coating a photoresist layer on the wafer, exposing and developing it with a mask to form an isolation shallow groove; etching the silicon dioxide, silicon nitride and the isolation shallow groove to remove the photoresist layer, depositing a layer of silicon dioxide, and then performing chemical mechanical polishing until the silicon nitride layer is formed to remove the silicon nitride layer.

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