Unidirectional transient voltage suppression device

Abstract

The present disclosure relates to a unidirectional transient voltage suppression device, comprising: a single crystalline semiconductor substrate doped with a first conductivity type and comprising a first opposite surface and a second opposite surface; a semiconductor region doped with a second conductivity type opposite the first conductivity type extending into the substrate from the first surface; a first conductive electrode in contact with the semiconductor region on a first side; and a second conductive electrode in contact with the substrate on a second side; a first interface forming a junction of a TVS diode between the substrate and the semiconductor region; and a second interface forming a junction of a Schottky diode between the first conductive electrode and the semiconductor region or between the substrate and the second conductive electrode.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of French Patent Application No. 2104856, filed May 7, 2021, which is hereby incorporated by reference herein. TECHNICAL FIELD

[0003] The present disclosure relates generally to transient voltage suppression devices. BACKGROUND

[0004] A transient voltage suppression device, also called a TVS device, is a device used to protect one or more electronic elements from voltage spikes.

[0005] One example of a TVS device is a transient voltage suppression diode, also called a TVS diode. This is a diode made of a semiconductor material that limits surges caused by an avalanche effect, the sole purpose being to protect an electronic circuit. A TVS diode can be unidirectional, i.e. have a breakdown voltage in reverse bias and a threshold voltage in forward bias. A TVS diode can be bidirectional, i.e. have a symmetric or asymmetric breakdown voltage regardless of the bias direction.

[0006] To protect an electronic element from voltage spikes, a TVS device can be placed in parallel with the element to be protected. It is desirable that the TVS device does not interfere with the normal operation of the electronic element it protects. However, when the TVS device is a unidirectional TVS diode, this diode can conduct current when forward biased with a sufficient voltage, then possibly interfere with the normal operation of the electronic element it protects. SUMMARY

[0007] One embodiment addresses all or some of the shortcomings of known transient voltage suppression devices.

[0008] One embodiment provides a transient voltage suppression device comprising: a monocrystalline semiconductor substrate doped with a first conductivity type and comprising a first opposite surface and a second opposite surface; a semiconductor region doped with a second conductivity type opposite the first conductivity type, extending into the substrate from the first surface; a first conductive electrode contacting the semiconductor region on the first surface and a second conductive electrode contacting the substrate on the second surface; a first junction forming a junction of a TVS diode between the substrate and the semiconductor region; and a second junction forming a junction of a Schottky diode between the first conductive electrode and the semiconductor region or between the substrate and the second conductive electrode.

[0009] According to one embodiment, when the second junction is between the first conductive electrode and the semiconductor region, the doping concentration of the second conductivity type of the semiconductor region is between 1 x 1014at / cm3and 1 x 1018at / cm3. 16 at / cm 3 at / cm3and 1 x 1018at / cm3.17 at / cm 3 between 1 x 1010and 1 x 1011at / cm2, while when the second interface is between the substrate and the second conductive electrode, the doping concentration of the second conductivity type of the semiconductor region is between 1 x 1010and 1 x 1011at / cm2. 16 at / cm 3 and 1 x 1011at / cm2. 20 at / cm 3 between 1 x 1010and 1 x 1011at / cm2.

[0010] According to one embodiment, the doping concentration of the first conductivity type of the substrate at the first interface is between 2 x 1010and 3 x 1011at / cm2when the second interface is between the first conductive electrode and the semiconductor region, while the doping concentration of the first conductivity type of the substrate at the first interface is between 2 x 1010and 1 x 1011at / cm2when the second interface is between the substrate and the second conductive electrode. 14 at / cm 3 and 3 x 1011at / cm2. 16 at / cm 3 between 2 x 1010and 1 x 1011at / cm2. 14 at / cm 3 and 1 x 1011at / cm2. 17 at / cm 3 between 2 x 1010and 1 x 1011at / cm2.

[0011] According to one embodiment, the substrate comprises a stack of a first portion containing the semiconductor region and a second portion in contact with the second conductive electrode, the doping concentration of the first conductivity type of the first portion being strictly lower than the doping concentration of the first conductivity type of the second portion.

[0012] One embodiment provides an electronic circuit comprising a conductive substrate, an electronic component having first and second terminals, the second terminal being attached to the conductive substrate, and a transient voltage suppression device as previously described, wherein the second conductive electrode of the transient voltage suppression device is attached to the substrate.

[0013] According to one embodiment, the first conductive electrode of the transient voltage suppression device is connected to the first terminal of the electronic component.

[0014] One embodiment provides an electronic circuit comprising at least one electronic component and a transient voltage suppression device as previously described arranged in parallel with said electronic component.

[0015] According to one embodiment, the circuit comprises at least four electronic components and four transient voltage suppression devices connected in a bridge configuration, each transient voltage suppression device being arranged in parallel with one of the electronic components. BRIEF DESCRIPTION OF DRAWINGS

[0016] The above features and advantages, and other will be described in detail below with reference to specific embodiments given by way of illustration and not limitation, in which:

[0017] Figure 1is a schematic partial cross-sectional view of an embodiment of a TVS device;

[0018] Figure 2 is Figure 1 is a partial cross-sectional view of a variant of the TVS device shown;

[0019] Figure 3 is Figure 1 is a schematic partial cross-sectional view of another variant of the TVS device shown;

[0020] Figure 4 is Figure 1 is a schematic partial cross-sectional view of another variant of the TVS device shown;

[0021] Figure 5 shows the evolution of the current flowing in the TVS device of Figure 1 as a function of the voltage applied to the TVS device according to a first polarization direction;

[0022] Figure 6 shows the evolution of the current flowing in the TVS device of Figure 1 as a function of the voltage applied to the TVS device according to a second polarization direction;

[0023] Figure 7 is an electrical diagram showing an example of a TVS device assembly for protecting an electronic element;

[0024] Figure 8 is a schematic partial cross-sectional view of an electronic circuit according to the electrical diagram of Figure 7 ;

[0025] Figure 9 is a schematic partial cross-sectional view of another embodiment of a TVS device;

[0026] Figure 10 is Figure 9 is a schematic partial cross-sectional view of a variant embodiment of the TVS device of

[0027] Figure 11 is a schematic view of an example of a DC-DC voltage converter;

[0028] Figure 12 shows the voltage and current timeline of the converter in Figure 11 ;

[0029] Figure 13 is a circuit diagram of an example of a DC-DC voltage converter with TVS diode protection elements;

[0030] Figure 14 shows the voltage and current timeline of the converter in Figure 13 ;

[0031] Figure 15 is a circuit diagram of an example of a DC-DC voltage converter having elements protected by the TVS device shown and described above. Figure 1

[0032] Figure 16 shows voltage and current timelines for the converter. Figure 15 DETAILED DESCRIPTION

[0033] In the different figures, identical features have been designated by the same references. In particular, structural and / or functional features that are common to the various embodiments can have the same references and can be provided with the same structural, dimensional and material properties. For the sake of clarity, only the operations and elements useful for understanding the embodiments described herein have been detailed and described.

[0034] Unless otherwise stated, when two elements are referred to as being connected together, this means a direct connection with no intervening elements other than a conductor, while when two elements are referred to as being coupled together, this means that the two elements can be connected or they can be coupled through one or more other elements. Furthermore, "insulator" and "conductor" are understood herein to mean "electrically insulating" and "electrically conducting", respectively.

[0035] In the following disclosure, when referring to absolute position qualifiers, such as the terms "top", "bottom", etc., or to relative position qualifiers, such as the terms "higher", "lower", etc., reference is made to the orientation shown in the figures or to the electronic device as positioned during normal use, unless otherwise indicated. "About", "approximately", "substantially" and "in order" mean within 10%, preferably within 5%, unless otherwise stated.

[0036] Figure 1 is a schematic partial cross-sectional view of one embodiment of the TVS device 10. Figure 2 , Figure 3 and Figure 4 are schematic partial cross-sectional views of variant embodiments of the TVS device 10.

[0037] In Figures 1 to 4 ​​In a particular embodiment, the TVS device 10 comprises a semiconductor substrate 12, preferably a monocrystalline silicon substrate doped with a first conductivity type, having an upper surface 14 and a lower surface 16, the monocrystalline silicon substrate being divided into an upper portion 24 and a lower portion 26, the upper portion 24 being lightly doped with the first conductivity type on the upper surface 14, and the lower portion 26 being heavily doped with the first conductivity type on the lower surface 16. The device further comprises a lightly doped region 18 of a second conductivity type opposite to the first conductivity type, extending from the upper surface 14 into the upper portion 24 of the substrate 12, an upper electrode 20, for example of metal, in contact with the region 18 on the upper surface 14, and a lower electrode 22, for example of metal, in contact with the substrate 12 on the lower surface 16.

[0038] According to an embodiment, the surfaces 14 and 16 are planar. According to an embodiment, the surfaces 14 and 16 are parallel. According to an embodiment, the thickness of the substrate 12, i.e. the distance between the surfaces 14 and 16, is between 60 μm and 300 μm, preferably between 90 μm and 300 μm, more preferably between 150 μm and 300 μm. The region 18 can be formed by a step of implanting a dopant of the second conductivity type into the substrate 12.

[0039] For a TVS device 10 according to Figure 1 and Figure 3 , the lightly doped upper portion 24 of the first conductivity type forms the bulk of the substrate 12, and the thickness of the lower portion 26 is less than 5% of the total thickness of the substrate 12, for example. The heavily doped lower portion 26 of the first conductivity type can be formed by a step of implanting a dopant of the first conductivity type on the lower surface 16 side. The dopant concentration of the first conductivity type in the substrate 12 outside the region 18 and the lower portion 26 is substantially constant. For a TVS device 10 according to Figure 2 and Figure 4 , the thickness of the heavily doped lower portion 26 of the first conductivity type is greater than 10% of the total thickness of the substrate 12. According to an embodiment, the upper portion 24 of the substrate 12 is formed epitaxially on the lower portion 26 of the substrate 12.

[0040] For a TVS device 10 according to Figure 1 and Figure 2 , the first conductivity type is N-type and the second conductivity type is P-type. The concentration of P-type dopant in the region 18 is between 1 x 1017 at / cm3 and 1 x 1020 at / cm3. According to an embodiment, the maximum thickness of the region 18 is between 1 μm and 40 μm. The concentration of N-type dopant in the upper portion 24 of the substrate 12 outside the region 18 is between 2 x 1018 at / cm3 and 3 x 1019 at / cm3. 16 3 17 3 14 3 16 3 ​​​​​​​Between. The doping concentration in the lower part 26 of the heavily N-doped substrate 12 is 8 x 10. 18 at / cm 3 and 8x10 19 at / cm 3 Between. For Figure 2 The variant shown has a thickness of 5 μm to 100 μm for the upper portion 24 of the substrate 12, measured from the upper surface 14.

[0041] for Figure 3 and Figure 4 The TVS device 10 has a first conductivity type of P-type and a second conductivity type of N-type. The N-type doping concentration in region 18 is 1 x 10⁻⁶. 16 at / cm 3 Up to 1x10 17 at / cm 3 The maximum thickness of region 18 is between 1 μm and 40 μm, according to one embodiment. The concentration of p-type dopant in the upper portion 24 of substrate 12 outside region 18 is between 2 x 10⁻⁶. 14 at / cm 3 and 3x10 16 at / cm 3 Between. The dopant concentration in the lower p-doped portion 26 of substrate 12 is 8 x 10⁻⁶. 18 at / cm 3 and 8x10 19 at / cm 3 Between. For Figure 4 In the embodiment shown, the thickness of the upper portion 24 of the substrate 12, measured from the upper surface 14, is between 5 μm and 100 μm.

[0042] Figures 1 to 4 The TVS device 10 shown exhibits anti-serial behavior between the two terminals of the TVS diode and the Schottky diode integrated in a single semiconductor substrate. The terminals correspond to electrodes 20 and 22. The interface between electrode 20 and the lightly doped region 18 of the second conductivity type forms the junction of the Schottky diode. The junction between the lightly doped region 18 of the second conductivity type and the adjacent lightly doped portion of the substrate 12 of the first conductivity type forms the TVS diode junction. The lower electrode 22 forms an ohmic contact with the substrate 12.

[0043] Figure 5 The diagram shows the voltage V_TVS between electrodes 20 and 22 from... Figure 2 The CF curves depict the evolution of the current I_TVS flowing from electrode 20 to electrode 22 in the TVS device 10. For the simulation, the thickness of the upper portion 24 of substrate 12 is 18 μm, and the thickness of the lower portion 26 of substrate 12 is 10 μm. The CF curves obtained through simulation show that the maximum P-type doping concentration (exhibiting a Gaussian distribution) in region 18 is equal to 3.7 x 10⁻⁶.16 cm 3 The N-type doping concentration of the upper portion 24 of the substrate 12 is equal to 9x10 14 cm 3 The N-type doping concentration of the lower portion 26 of the substrate 12 is equal to 2x10 19 cm 3 .

[0044] This corresponds to a forward bias of the TVS diode of the TVS device 10 and a reverse bias of the Schottky diode of the TVS device 10. The CF curve successively comprises a portion CF1 in which the current I_TVS is substantially zero, a portion CF2 in which the current I_TVS increases rapidly with the voltage V_TVS when the forward biased TVS diode of the TVS device 10 becomes conductive and the saturation current of the Schottky diode has not yet been reached, and a portion CF3 in which the current I_TVS substantially corresponds to the reverse leakage current of the reverse biased Schottky diode of the TVS device 10 and increases with the voltage applied on the reverse biased Schottky diode of the TVS device 10. Preferably, the voltage applied to the TVS device 10 corresponding to the reverse biased Schottky diode of the TVS device 10 is less than the reverse breakdown voltage of the Schottky diode, which can be in the range of 1 V to 20 V depending on the doping and thickness of the region 18.

[0045] Figure 6 A CR curve showing the evolution of the current I_TVS flowing from the electrode 22 to the electrode 20 of the TVS device 10 as a function of the voltage V_TVS between the electrode 22 and the electrode 20 is shown in Figure 3. The CR curve is obtained by simulation at the same doping concentrations as the CF curve. Figure 1

[0046] This corresponds to a reverse bias of the TVS diode of the TVS device 10 and a forward bias of the Schottky diode of the TVS device 10. The CR curve successively comprises a portion CR1 in which the current I_TVS increases rapidly with the voltage V_TVS, then a portion CR2 in which the current I_TVS increases more slowly with the voltage V_TVS, and a portion CR3 in which the current I_TVS increases very rapidly with the voltage V_TVS. Portions CR1 and CR2 correspond to an increase in the current leakage of the diode TVS due to the expansion of the space charge region. The difference in current increase between CR1 and CR2 is due to the expansion of the space charge region. The portion CR3 corresponds to the avalanche operation of the TVS diode in the TVS device 10. Due to the fact that the saturation current Isat_Sch of the Schottky diode is much higher than the leakage current I_TVS of the TVS diode, the Schottky diode has a very low voltage on these terminals, which does not affect the electrical characteristics of the TVS diode before entering avalanche operation. The voltage V_Schottky on the Schottky diode can be written as follows: ​

[0047] V_Schottky = (kT / q) * ln(I_TVS / Isat_Sch + 1) (1)

[0048] where k is the Boltzmann constant, T is the absolute temperature, and q is the charge of an electron.

[0049] For I_TVS much lower than Isat_Sch, the voltage V_Schottky is approximately equal to kT / q * I_TVS / Isat_Sch, which is at most a few millivolts, and thus negligible compared to the voltage across the TVS diode. Therefore, the voltage V_TVS across the TVS device 10, which is the sum of the voltage V_Schottky across the Schottky diode and the voltage across the TVS diode, is approximately equal to the voltage across the TVS diode. When the current is higher than Isat_Sch, the Schottky diode voltage increases by about 60 mV per decade of current, which is added to the voltage across the TVS diode. This voltage corresponds to the Schottky diode threshold voltage and is typically lower than 1 V. In most cases, this voltage is negligible compared to the avalanche voltage of the TVS diode. Therefore, the presence of the Schottky diode has little impact on the TVS diode characteristics.

[0050] Figure 2 and Figure 4 The variants of the TVS device 10 shown advantageously allow to reduce the series resistance of the TVS device 10 between the terminals 20 and 22 due to the heavily doped lower portion 26 of the substrate 12 having a reduced resistivity. Therefore, these variants can have an increased power dissipation capability. For a given pulse, these variants dissipate less power and will be able to withstand a higher current overload.

[0051] Figure 7 is a schematic diagram showing an example of an arrangement of a TVS device 10 for protecting a diode in an electronic component 30, Figure 7 Typically, the electronic component 30 to be protected is a diode, such as a Schottky diode, a silicon carbide (SiC) diode, a power MOS transistor with an intrinsic diode, or an insulated gate bipolar transistor (IGBT) with an external diode in anti-parallel. According to one embodiment, the TVS device 10 is placed in parallel with the electronic component 30 to be protected. The TVS device 10 is schematically shown in Figure 7 is a TVS diode DT anti-series with a Schottky diode DS. The TVS device 10 is oriented so that the TVS diode DT of the TVS device 10 is forward biased when the electronic component 30 conducts a maximum intensity of current during normal operation. In the case where the electronic component 30 is a diode, the TVS device 10 is oriented so that the TVS diode DT of the TVS device 10 is forward biased when the electronic component 30 is forward biased.

[0052] Therefore, when electronic component 30 conducts the maximum current during normal operation, the Schottky diode of TVS device 10 blocks the current flowing through TVS device 10, thus preventing TVS device 10 from interfering with the normal operation of component 30. In the event of a reverse voltage spike, the TVS diode in TVS device 10 clips the voltage, thereby protecting component 30.

[0053] Figure 8 It is integrated with Figure 7 The diagram shows a schematic partial cross-sectional view of one embodiment of an electronic circuit 32 corresponding to a circuit diagram, the electronic circuit 32 including a TVS device 10 connected in parallel with an electronic element 30 corresponding to a diode. For example, the diode 30 includes a semiconductor substrate 36 (such as an N-doped single-crystal silicon substrate), an N-doped silicon layer 38 epitaxially formed on the substrate 36, a P-doped region 40 formed in the layer 38, an annular region 42 formed in the layer 38 and surrounding the P-doped region 40 and being lightly doped than the region 40, an insulating layer 44 covering the annular region 42 and defining an opening 50 that defines a portion of the exposed region 40, a conductive electrode 52 in contact with the region 40 in the opening 50, and a metal electrode 54 on the side of the substrate 36 opposite to the layer 38.

[0054] Circuit 32 also includes a conductive support 56 to which the TVS device 10 and diode 30 are attached, wherein the lower electrode 22 of the TVS device 10 is attached to the support 56, and the electrode 54 of the diode 30 is attached to the support 56. The support 56 forms a common cathode for the diode 30 and the TVS diode of the TVS device 10. Circuit 32 also includes a conductive pad 58, schematically shown as a square above the TVS device 10 and diode 30 for illustrative purposes, which is connected, for example, to the upper electrode 20 of the TVS device 10 and the electrode 52 of the diode 30 via a wire 60.

[0055] Therefore, electronic circuit 32 integrates TVS device 10 and electronic component 30 to be protected on the same support 56. This reduces the parasitic inductance between TVS device 10 and electronic component 30, thereby improving the protection of electronic component 30.

[0056] Furthermore, using a TVS device 10 that includes both a TVS diode and a Schottky diode is simpler than using TVS diodes and Schottky diodes as discrete components for protection.

[0057] Figure 9 This is a schematic partial cross-sectional view of another embodiment of the TVS device 70. Figure 10 This is a schematic partial cross-sectional view of a variant of the TVS device 70.

[0058] exist Figure 9 and Figure 10 In the TVS device 70, a semiconductor substrate 72 is included, preferably, a lightly doped single-crystal silicon substrate of a first conductivity type, having an upper surface 74 and a lower surface 76, a region 78 doped with a second conductivity type opposite to the first conductivity type, extending from the upper surface 74 through a portion of the thickness of the substrate 72 into the substrate 72, such as a conductive upper electrode 80 of metal located on the upper surface 74 and in contact with the region 78, and a conductive lower electrode 82 located on the lower surface 76 and in contact with the substrate 72.

[0059] According to one embodiment, surfaces 74 and 76 are planar. According to one embodiment, surfaces 74 and 76 are parallel. According to one embodiment, the thickness of the substrate 72, i.e., the distance between surfaces 74 and 76, is between 60 μm and 300 μm, preferably between 90 μm and 300 μm, and more preferably between 150 μm and 300 μm. Region 78 can be formed by implanting a dopant of a second conductivity type into the substrate 72.

[0060] for Figure 9 and Figure 10 In device 70, the concentration of dopant of the first conductivity type in substrate 72 outside region 78 is substantially constant.

[0061] for Figure 9 Device 70 has an N-type primary conductivity and a P-type secondary conductivity. The P-type doping concentration in region 78 is 1 x 10⁻⁶. 16 at / cm 3 Up to 1x10 20 at / cm 3 The maximum thickness of region 78 is between 1 μm and 40 μm, according to one embodiment. The N-type doping concentration in the substrate 72 outside region 78 is between 2 x 10⁻⁶. 14 at / cm 3 and 1x10 17 at / cm 3 between.

[0062] for Figure 10 Device 70 has a primary conductivity type of P-type and a secondary conductivity type of N-type. The N-type doping concentration in region 78 is 1 x 10⁻⁶. 16 at / cm 3 Up to 1x10 20 at / cm 3 The maximum thickness of region 78 is between 1 μm and 40 μm, according to one embodiment. The p-type doping concentration in the substrate 72 outside region 78 is between 2 x 10⁻⁶. 14 at / cm 3 and 1x10 17 at / cm3 between.

[0063] Figure 9 and Figure 10 The device 70 shown in FIG. 7 behaves as an anti- series connection between the two terminals of a TVS diode and a Schottky diode. The terminals correspond to electrodes 80 and 82. The junction between electrode 82 and the lightly doped substrate 72 of the first conductivity type forms the junction of the Schottky diode. The junction between the doped region 78 of the second conductivity type and the adjacent lightly doped portion of the substrate 72 of the first conductivity type forms the junction of the TVS diode. The upper electrode 80 forms an ohmic contact with the region 78.

[0064] The TVS device 10 or 70 can be used in any electronic circuit comprising electronic elements that need to be protected from voltage spikes. The electronic circuit is a DC-to-DC, AC-to-DC or DC-to-AC converter, operating in hard switching conditions at so-called high current levels, for example:

[0065] Figure 11is a circuit diagram of an example of a DC-to-DC voltage converter 90. The converter 90 comprises a source of direct voltage Vin 92, and first, second, third and fourth switching blocks SW1, SW2, SW3, SW4, each switching block SW1, SW2, SW3, SW4 comprising a switch S1, S2, S3, S4, a diode DSW1, DSW2, DSW3, DSW4 connected in parallel with the switch, and a capacitor CSW1, CSW2, CSW3, CSW4 connected in parallel with the switch, each switch S1, S2, S3, S4 being controlled by an optically isolated coupler, each switch S1, S2, S3, S4 being controlled by a square wave control voltage source V1, V2, V3, V4 using optically, magnetically or capacitively isolated couplers, the first and second switching blocks SW1 and SW2 being connected in series between the positive and negative terminals of the voltage source 92, the third and fourth switching blocks SW3 and SW4 being connected in series between the positive and negative terminals of the voltage source 92. The device further comprises a transformer T (the transformer T comprising a primary winding L1 and a secondary winding L2), an inductor L3 connected between the midpoint P+ between the first and second switching blocks SW1 and SW2 and a first terminal of the primary winding L1 (where a second terminal of the primary winding L1 is connected to the midpoint P- between the third and fourth switching blocks SW3 and SW4), an inductor L4 connected in parallel between the first and second terminals of the primary winding L1, a diode bridge rectifier connected to the secondary winding L2, comprising a diode D1, an anode of the diode D1 being connected to a first terminal of the secondary winding L2, a diode D2, an anode of the diode D2 being connected to a second terminal of the secondary winding L2, a diode D3, a cathode of the diode D3 being connected to the first terminal of the secondary winding L2, and a diode D4, a cathode of the diode D4 being connected to the second terminal of the secondary winding L2. The device further comprises: a capacitor Csnubber connected in series with a resistor Rsnubber between the first and second terminals of the secondary winding L2; an inductor L5 having a first terminal connected to the cathodes of the diodes D1 and D2; a capacitor Cout having one electrode connected to a second terminal of the inductor L5 and a second electrode connected to the anodes of the diodes D3 and D4; and a load Rload connected in parallel with the capacitor Cout.

[0066] The voltage between the midpoint P+ between the first and second switching blocks SW1 and SW2 and the midpoint P- between the third and fourth switching blocks SW3 and SW4 is referred to as VP, the voltage between the cathode and anode of the diode D1 is referred to as VD1, the voltage across the resistor Rload is referred to as VR, and the current flowing from the anode to the cathode of the diode D1 is referred to as ID1, and the current flowing through the resistor Rload is referred to as IR.

[0067] The capacitor Csnubber and the resistor Rsnubber constitute a transient overvoltage protection device. However, for Figure 11The electronic circuit 90 shown, diodes D1, D2, D3 and D4 are not individually protected by dedicated TVS devices.

[0068] Figure 12 A timeline of voltages VP, VD1 and VR and currents ID1 and IR obtained by simulation during operation of the converter 90 shown in Figure 11 For this simulation, the voltage Vin is constant and equal to 430 V. The switches S1, S2, S3 and S4 are successively closed with a defined time offset and timing to allow soft switching of the switches S1, S2, S3 and S4 at zero voltage. In Figure 12 In the example shown, each switch S1, S2, S3 and S4 remains closed for 5 μβ and then open for 5 μβ within a switching period of 10 μβ. The output voltage VR is substantially constant and equal to 360 V. The voltage VP substantially varies stepwise following the sequence of closing and opening of the switches S1, S3, S2 and S4. When the voltage VP reverses from +430 V to -430 V (associated with the switching of the switches S1, S2, S3 and S4), the current Id1 flowing through the diode D1 will decrease at a relatively high speed, which is defined by the inductance L3 and the turns ratio of the transformer T, when the current Id1 reaches zero, the diode D1 will open, resulting in a significant negative overvoltage and parasitic oscillations from the value of 0 V for the voltage VD1, with a maximum amplitude of 1350 V, which can be higher than the maximum reverse voltage acceptable for the diode D1.

[0069] Figure 13 is a circuit diagram of a DC-DC voltage converter 100. The converter 100 comprises Figure 11 all the elements of the converter 90 shown in and, for each diode Di, i being an integer in the range 1 to 4, further comprises a TVS diode DTi in parallel with the diode Di, the anode of the TVS diode DTi being connected to the anode of the diode Di and the cathode of the TVS diode DTi being connected to the cathode of the diode Di.

[0070] Figure 14 A timeline of voltages VP, VD1 and VR and currents ID1 and IR obtained by simulation during operation of the converter 100 shown in Figure 12 The operating conditions are the same as in Figure 14 for obtaining the timeline. The parasitic oscillations of the voltage VD1 are suppressed by the TVS diode DT1. However, Figure 12 There is a significant difference between the curves of the voltage VD1 and the current IR of Figure 15 due to the fact that when each TVS diode DT1, DT2, DT3, DT4 is forward biased, a current flows therein and a phenomenon of carrier recombination can occur.

[0071] Figure 11 This is the electrical diagram of a DC-DC voltage converter 110. Converter 110 includes... Figure 1 The converter 90 includes all its components, and for each diode Di, i is an integer varying from 1 to 4, and also includes diodes connected in parallel with Di. Figure 15 The structure of the TVS device 10 shown is represented by the TVS device DDi. Each TVS device DDi is in... Figure 16 The deserialization of the TVS diode DTi and the Schottky diode DSi shows that the cathode of the Schottky diode DSi is connected to the anode of the diode Di, while the cathode of the TVS diode DTi is connected to the cathode of the diode Di.

[0072] Figure 15 It shows in Figure 12 The timeline of voltages VP, VD1, and VR, and currents ID1 and IR, obtained through simulation during the operation of converter 110. Operating conditions and Figure 16 The operating conditions used to acquire the timeline are the same. Parasitic oscillations of voltage VD1 are suppressed. Furthermore, Figure 12 The evolution curves of voltage VD1 and current IR have the same characteristics as... ​ The evolution curves of voltage VD1 and current IR have the same general shape, which means that the operation of diodes D1, D2, D3 and D4 is not affected by TVS device DDi.

[0073] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these embodiments can be combined, and other variations will be readily apparent to them. Finally, practical implementations of the described embodiments and variations, based on the functional indications given above, are within the capabilities of those skilled in the art.

Claims

1. A transient voltage suppression device, comprising: A single-crystal semiconductor substrate, doped with a first conductivity type, and comprising a first surface and a second surface opposite to each other; A semiconductor region, doped with a second conductivity type opposite to the first conductivity type, and extending from the first surface into the substrate; A first conductive electrode contacts the semiconductor region on the first surface; The second conductive electrode contacts the substrate on the second surface; A first interface is formed between the substrate and the semiconductor region, creating a junction for a transient voltage suppression diode. A second interface is located between the first conductive electrode and the semiconductor region, wherein the doping concentration of the second conductivity type in the semiconductor region is 1x10⁻⁶. 16 at / cm 3 and 1x10 17 at / cm 3 Between; or the second interface forms a Schottky diode junction between the substrate and the second conductive electrode, wherein the doping concentration of the second conductivity type in the semiconductor region is 1x10⁻⁶. 16 at / cm 3 and 1x10 20 at / cm 3 between.

2. The device of claim 1, wherein the second interface is located between the first conductive electrode and the semiconductor region, and wherein the doping concentration of the first conductivity type of the substrate at the first interface is 2 x 10⁻⁶. 14 at / cm 3 With 3x10 16 at / cm 3 between.

3. The device of claim 1, wherein the second interface is located between the substrate and the second conductive electrode, and wherein the doping concentration of the first conductivity type of the substrate at the first interface is 2 x 10⁻⁶. 14 at / cm 3 With 1x10 17 at / cm 3 between.

4. The device of claim 1, wherein the substrate comprises a stack of a first portion and a second portion, wherein: The first portion includes the semiconductor region; The second portion is in contact with the second conductive electrode; and The first doping concentration of the first conductivity type in the first part is strictly lower than the second doping concentration of the first conductivity type in the second part.

5. An electronic circuit, comprising: Conductive support components; An electronic component having a first terminal and a second terminal, wherein the second terminal is attached to the conductive support; as well as Transient voltage suppression devices, including: A single-crystal semiconductor substrate, doped with a first conductivity type, and comprising a first surface and a second surface opposite to each other; A semiconductor region, doped with a second conductivity type opposite to the first conductivity type, and extending from the first surface into the substrate; A first conductive electrode contacts the semiconductor region on the first surface; The second conductive electrode contacts the substrate on the second surface and is attached to the conductive support; A first interface is formed between the substrate and the semiconductor region, creating a junction for a transient voltage suppression diode; and A second interface is located between the first conductive electrode and the semiconductor region, wherein the doping concentration of the second conductivity type in the semiconductor region is 1x10⁻⁶. 16 at / cm 3 With 1x10 17 at / cm 3 Between, or between the second interface and the substrate, a Schottky diode junction is formed, wherein the doping concentration of the second conductivity type in the semiconductor region is 1 x 10⁻⁶. 16 at / cm 3 With 1x10 20 at / cm 3 between.

6. The electronic circuit according to claim 5, wherein the first conductive electrode of the transient voltage suppression device is electrically connected to the first terminal of the electronic element.

7. The electronic circuit of claim 5, wherein the second interface is located between the first conductive electrode and the semiconductor region, and wherein the doping concentration of the first conductivity type of the substrate at the first interface is 2 x 10⁻⁶. 14 at / cm 3 With 3x10 16 at / cm 3 between.

8. The electronic circuit of claim 5, wherein the second interface is located between the substrate and the second conductive electrode, and wherein the doping concentration of the first conductivity type of the substrate at the first interface is 2 x 10⁻⁶. 14 at / cm 3 With 1x10 17 at / cm 3 between.

9. The electronic circuit of claim 5, wherein the substrate comprises a stack of a first portion and a second portion, wherein: The first portion includes the semiconductor region; The second portion is in contact with the second conductive electrode; and The first doping concentration of the first conductivity type in the first part is strictly lower than the second doping concentration of the first conductivity type in the second part.

10. An electronic circuit, comprising: At least one electronic component; as well as A transient voltage suppression device, connected in parallel with the electronic component, and comprising: A single-crystal semiconductor substrate, doped with a first conductivity type, and comprising a first surface and a second surface opposite to each other; A semiconductor region, doped with a second conductivity type opposite to the first conductivity type, and extending from the first surface into the substrate; A first conductive electrode contacts the semiconductor region on the first surface; The second conductive electrode contacts the substrate on the second surface; A first interface is formed between the substrate and the semiconductor region, creating a junction for a transient voltage suppression diode; and A second interface is located between the first conductive electrode and the semiconductor region, wherein the doping concentration of the second conductivity type in the semiconductor region is 1x10⁻⁶. 16 at / cm 3 With 1x10 17 at / cm 3 Between, or between the second interface and the substrate, a Schottky diode junction is formed, wherein the doping concentration of the second conductivity type in the semiconductor region is 1 x 10⁻⁶. 16 at / cm 3 With 1x10 20 at / cm 3 between.

11. The electronic circuit of claim 10 further comprises at least four bridging electronic components and four transient voltage suppression devices, each transient voltage suppression device being arranged in parallel with a corresponding bridging electronic component among the bridging electronic components.

12. The electronic circuit of claim 10, wherein the second interface is located between the first conductive electrode and the semiconductor region, and wherein the doping concentration of the first conductivity type of the substrate at the first interface is 2 x 10⁻⁶. 14 at / cm 3 With 3x10 16 at / cm 3 between.

13. The electronic circuit of claim 10, wherein the second interface is located between the substrate and the second conductive electrode, and wherein the substrate is located at the first interface. The doping concentration of the first conductivity type at the bottom is 2x10 14 at / cm 3 With 1x10 17 at / cm 3 between.

14. The electronic circuit of claim 10, wherein the substrate comprises a stack of a first portion and a second portion, wherein: The first portion includes the semiconductor region; The second portion is in contact with the second conductive electrode; and The first doping concentration of the first conductivity type in the first part is strictly lower than the second doping concentration of the first conductivity type in the second part.

Images