A cyclotron optimization startup method based on pulse closed-loop mode

Abstract

The present invention discloses a cyclotron optimization startup method based on a pulse closed-loop mode, which is characterized by: initialization preparation; entering a low-power tuning state in the pulse closed-loop mode and realizing a tuning closed-loop in the low-power tuning state; entering a pulse search state in the pulse closed-loop mode and realizing a tuning closed-loop in the pulse search state; entering a power boost state in the pulse closed-loop mode and realizing an amplitude closed-loop in the power boost state; entering a normal operating state in the pulse closed-loop mode and realizing cavity pressure balance in the normal operating state. The present invention adopts a pre-tuning point + pulse closed-loop mode, and adopts a pre-tuning point method, so that when entering the pulse search state and the power boost state, the input power to the cavity can be maximized, and the power reflected back by the cavity can be minimized; the pulse closed-loop mode is adopted to avoid the safety hazards caused by excessive power during the pulse search, power boost, and normal operation stages.

Description

Technical Field

[0001] The invention relates to a cyclotron high-frequency low-level system design technology, and in particular to a cyclotron optimization startup method based on a pulse closed-loop mode. Background Art

[0002] There are three difficulties in the startup process of the cyclotron high-frequency cavity: the first difficulty is to avoid the secondary electron multiplication effect area, because the secondary electron multiplication effect will limit the power increase of the high-frequency system; the second difficulty is to find the tuning point, because if the tuning point cannot be found, even if the secondary electron multiplication effect area is crossed, it will still limit the power increase of the high-frequency system. The difficulty in finding the tuning point lies in: the compact cyclotron designed by the China Institute of Atomic Energy has a lower starting point power in the secondary electron multiplication area, nearly tens of milliwatts, which is nearly 100 times the minimum starting point of the existing technical-level electron multiplication area of ​​1 watt. It is more difficult to find the tuning point at ultra-low power; the third difficulty is: even if the tuning point is found and the secondary electron multiplication effect area is crossed, new problems will be encountered in the high-level continuous signal stage after the power is increased: on the one hand, the signal is required to be a high-power signal, and on the other hand, when the signal power is too high, if the quality factor Q of the cavity is not high enough, it will cause the reflected power to be too large, thereby burning the transmitter and the coupling window. For example, after finding the tuning point, pulse stretching is used to cross the electron multiplication region. After the pulse is stretched to 50%, it becomes a continuous signal and enters the power boost and normal operation stages under the continuous signal. The latter two stages require the power to remain high, but because it is a continuous high-power signal, when it accumulates to a certain level, it is very likely to burn out the transmitter and coupling window. Summary of the invention

[0003] In view of the problems existing in the prior art, the present invention proposes a cyclotron optimization startup method based on a pulse closed-loop mode. The first purpose is to solve the problem of finding a tuning point under ultra-low power, and the second purpose is to solve the problem of easy breakdown and burning of the cavity under high-power continuous signals.

[0004] The present invention proposes the following technical solutions to solve the technical problems:

[0005] A cyclotron optimization startup method based on a pulse closed-loop mode is characterized by comprising the following steps:

[0006] Step 1: Initialization preparation

[0007] 1) Establish a one-button start-up process for the cyclotron low-level system;

[0008] 2) Establish a CPU state machine, the state of the state machine is S0~S4;

[0009] Step 2: Enter the low power tuning state in the pulse closed loop mode and realize the tuning closed loop in the low power tuning state;

[0010] Step 3: Enter the pulse search state in the pulse closed-loop mode and implement the tuning closed-loop in the pulse search state;

[0011] Step 4: Enter the power boost state in the pulse closed-loop mode and realize the amplitude closed-loop in the power boost state;

[0012] Step 5: Enter the normal operating state under the pulse closed-loop mode and achieve cavity pressure balance under the normal operating state.

[0013] Furthermore, the step 2 of entering the low-power tuning state in the pulse closed-loop mode and realizing the tuning closed-loop in the low-power tuning state is specifically performed as follows:

[0014] 1) The low-level modulation output module inputs a low-level pulse signal to the accelerator cavity, and the low-level pulse signal drives the accelerator cavity, and obtains the cavity forward signal Forward, cavity sampling signal Pickup1, and cavity sampling signal Pickup2 of the tuning module through the sampling cable from the accelerator;

[0015] 2) The CPU state machine changes from the shutdown state s0 to the low power tuning state s1 and sends s1 to the digital controller.

[0016] 3) The digital controller gives a low level signal to the high frequency switch 1 and high frequency switch 2 of the tuning module and the high voltage switch 3 of the low level modulation output module respectively;

[0017] 4) The forward signal Forward of the cavity and the cavity sampling signal Pickup1 are connected to their respective amplifiers through high-frequency switch 1 and high-frequency switch 2 to ensure that the low-power signal can enter the phase detector range; high-voltage switch 3 selects a 14db attenuator;

[0018] 5) performing a subtraction operation on the ADC analog signal derived from the phase detector and the tuning parameter setting value, and sending the operation result to the digital controller through the ADC in one way and to the tuning comparator in the other way;

[0019] 6) The PID tuning algorithm unit performs a tuning closed-loop operation under low-power tuning state: when it is determined that the cavity frequency and the high-frequency signal frequency are consistent, a tuning closed-loop signal PhaseOK is output to the CPU to implement the tuning closed-loop under low-power tuning state and enter the pulse search phase; under low-power tuning state, the tuning comparator determines the tuning closed-loop under continuous signals.

[0020] Furthermore, the step 3 of entering the pulse search state in the pulse closed-loop mode and realizing the tuning closed-loop in the pulse search state is specifically performed as follows:

[0021] 1) After receiving the tuning closed-loop signal PhaseOK in the low-power tuning state, the CPU sends the s2 signal to the digital controller;

[0022] 2) The digital controller sends a pulse signal with a fixed duty cycle to high-frequency switch 3, and to high-frequency switches 1 and 2 at the same time;

[0023] 3) The high-frequency switches 1 and 2 of the tuning module select one attenuator according to the high-level signal of the pulse signal with a fixed duty cycle. Since the power is increased in the pulse search state, the cavity forward signal Forward and the cavity sampling signal Pickup1 after the power is increased enter the phase detector through the attenuator; the high-frequency switch 3 selects one 3db attenuator when the pulse is at a high level and one 14db attenuator when the pulse is at a low level according to the pulse signal with a fixed duty cycle, thereby realizing equal-width pulses in the power search state;

[0024] 4) performing a subtraction operation on the ADC analog signal derived from the phase detector and the tuning parameter setting value, and sending the operation result to the digital controller through the ADC in one way and to the tuning comparator in the other way;

[0025] 5) The PID tuning algorithm unit performs a tuning closed-loop operation in the pulse search state: when it is determined that the cavity frequency and the high-frequency signal frequency are consistent, a pulse tuning closed-loop signal PhaseOK is output to the CPU to implement the pulse tuning closed-loop in the pulse search state, and the tuning comparator is closed to enter the power boost state; in the pulse search state, the tuning comparator determines the tuning point when the pulse is at a high level.

[0026] Furthermore, the step 4 of entering the power boost state in the pulse closed-loop mode and realizing the amplitude closed-loop in the power boost state is specifically performed as follows:

[0027] 1) After receiving the pulse tuning closed-loop signal PhaseOK in the power search state, the CPU sends the s3 signal to the digital controller;

[0028] 2) The digital controller sends a pulse signal with a fixed duty cycle to high-frequency switch 3, and to high-frequency switches 1 and 2 at the same time;

[0029] 3) The high-frequency switch 3 selects a 3db attenuator when the pulse is at a high level and a 14db attenuator when the pulse is at a low level according to the pulse signal with a fixed duty cycle, thereby realizing equal-width pulses in the power boost state; the high-frequency switches 1 and 2 of the tuning module select an attenuator when the pulse signal with a fixed duty cycle is at a high level and selects an amplifier when the pulse is at a low level.

[0030] 4) The digital controller controls the digital controlled attenuator to continuously reduce the attenuation, and then continuously increase the power, until the amplitude modulation comparator of the amplitude demodulation module outputs the pulse amplitude closed-loop VDeeOK signal to the CPU. At this time, the power boost stage is completed, the amplitude closed-loop is realized, and the normal operation state is entered.

[0031] Furthermore, the step 5 of entering the normal operation state under the pulse closed-loop mode and achieving cavity pressure balance under the normal operation state is specifically performed as follows:

[0032] 1) After receiving the pulse amplitude closed-loop signal VDee_OK in the power boost state, the CPU sends the s4 signal to the digital controller;

[0033] 2) The digital controller sends a pulse signal of equal width to high-frequency switch 3 and to high-frequency switches 1 and 2 at the same time;

[0034] 3) According to the pulse signal of fixed duty cycle, high frequency switch 3 selects one 3db attenuator when the pulse is at high level and one 14db attenuator when the pulse is at low level, so as to realize the pulse of fixed duty cycle under normal operation; high frequency switch 1 and high frequency switch 2 of the tuning module select one attenuator according to the high level signal of equal width pulse signal and select one amplifier when the pulse is at low level.

[0035] 4) The numerically controlled attenuator is a constant value;

[0036] 5) The digital controller starts the DSP balancing algorithm unit to balance the cavity pressure between the two cavities.

[0037] Furthermore, the digital controller of the process 5) starts the DSP balance algorithm unit to balance the cavity pressure between the two cavities, and the specific steps are as follows:

[0038] 1) When the two cavities of the accelerator are capacitively coupled, the voltage imbalance between the two cavities due to factors such as processing design is expressed by a ratio relationship:

[0039]

[0040] Among them, C 12 is the coupling capacitance between the two groups of cavities, which is divided into two parts C 12 ” and C 12 ', where C 12 ” is the capacitance of cavity D1, C 12 ' is the capacitance of cavity D2;

[0041] 2) Change C 12 ” and C 12The D voltage can be adjusted by the ratio of ', and the balance control algorithm is as follows: the phase detector output result Tphase determines the movement frequency of the capacitor motor, and the motor movement step setting value Dsteps determines the movement steps of the motor. When Dsteps>0, Tphase>0, the D1 cavity group motor moves in the positive direction at 2 times the speed, and the D2 cavity group motor stops; when Dsteps>0, Tphase<0, the D2 cavity group motor moves in the reverse direction at 2 times the speed, and the D1 cavity group motor does not move; when Dsteps<0, TPhase>0, the D2 cavity group motor moves in the positive direction at twice the speed, and the D1 cavity group motor does not move; when Dsteps<0, TPhase<0, the D1 cavity group motor moves in the reverse direction at twice the speed, and the D2 cavity group motor does not move.

[0042] Furthermore, the PID tuning algorithm unit performs a closed-loop tuning operation, and the implementation process is as follows:

[0043] 1) The digital PID algorithm is expressed as:

[0044] y(n)=y(n-1)+K0x(n)+K1x(n-1)+K2(n-2);

[0045] Where y(n) is the PID operation output, y(n-1) is the PID operation output at the previous moment, K0, K1, and K2 are PID adjustment coefficients, and x(n), x(n-1), and x(n-2) are the PID inputs at the current moment, the previous moment, and the previous two moments;

[0046] 2) Use R0 and R3 registers in the DSP's X memory, and read and write operations are performed by the global data bus;

[0047] 3) Store the PID inputs x(n), x(n-1) and x(n-2) of the current moment, the previous moment and the previous two moments into register R0, and store k0, k1, k2 into register R3;

[0048] 4) Use the global bus to read and write these two registers, and use the accumulator and multiplication functions in the DSP and assembly language to implement y(n)=y(n-1)+k0*x(n)+k1*x(n-1)+k2*x(n-2).

[0049] Advantages and effects of the present invention

[0050] 1. The present invention adopts the pre-tuning point + pulse closed-loop mode, which not only improves the quality factor during the cavity startup process, but also avoids the safety hazards caused by excessive power. The pre-tuning point is found before the power is increased in the two stages. The first pre-tuning point is found before the low-power tuning state enters the pulse search state, so that when entering the pulse search state to increase the power, the input power to the cavity can be maximized, and the power reflected back by the cavity can be minimized, that is, the quality factor Q value of the cavity is the highest. The second pre-tuning point is found before entering the power boosting state from the pulse search state, that is, the tuning point is found for the second time in the pulse search stage, so that when entering the power boosting state, the input power to the cavity can be maximized and the power reflected back by the cavity can be minimized; the pulse closed-loop mode uses a pulse with a fixed duty cycle to replace the high-level continuous mode under the pulse search, power boost, and normal operating conditions, thereby solving the problem of excessive power burning the transmitter and the coupling window during the debugging process. At the same time, since the tuning point is judged when the pulse is at a high level, it does not affect the judgment of the tuning closed loop and also takes into account the problem of avoiding excessive power burning the transmitter and the coupling window.

[0051] 2. The present invention solves the long-standing problem of finding the tuning point at ultra-low power during the start-up of the accelerator cavity by organically combining the tuning module, the low-level modulation output module, the amplitude demodulation module, the PID tuning algorithm unit of the digital controller, the DSP balancing algorithm unit, and the CPU state machine. It also solves the problem of needing to find the tuning point twice due to power changes during the cavity start-up process: by setting the high-frequency switch 1 and the high-frequency switch 2, the amplifier, the attenuator, and the phase detector of the tuning module, the problem that the low-power signal cannot be recognized by the phase detector at ultra-low power and the high-power signal exceeds the maximum input voltage range of the phase detector is solved; by organically combining the PID tuning algorithm unit, the tuning parameter setting module, and the tuning comparator of the tuning module, the problem that the PID operation rate cannot keep up with the state change when finding the tuning point is solved; The low-level output signal of the low-level modulation output module, the organic combination of 3, 3db attenuation and 14db attenuation of the high-frequency switch and the tuning module not only realizes the tuning closed loop in the low-power tuning state, but also realizes the tuning closed loop in the high-power pulse search state; through the tuning closed loop of the tuning module, the amplitude demodulation module, the amplitude closed loop signal and the CPU state machine, and the digital controller, the control problem of the high-frequency signals 1, 2, and 3 in the two stages of the tuning closed loop is solved, so that the three high-frequency switches select one amplifier and one 14db attenuator at ultra-low power, so that the low-power signal can enter the phase detection range of the phase detector; at high power, the high-frequency signals 1, 2, and 3 select one attenuator and one 3db attenuator, so that the high-power cavity sampling signal will not exceed the maximum input voltage range of the phase detector. In short, through the organic combination of various modules, mutual support and mutual dependence, new effects are produced. Substantial progress has been achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 It is a schematic diagram of the cyclotron optimization starting device based on the pulse closed-loop mode of the present invention;

[0053] Figure 2 Schematic diagram of the PID tuning algorithm for the invented optimized starting device.

[0054] Figure 3 The present invention is a flow chart of a cyclotron optimization startup method based on a pulse closed-loop mode. DETAILED DESCRIPTION

[0055] Design principle of the present invention

[0056] 1. The innovation of the present invention lies in: pre-tuning point + pulse closed-loop mode. The pre-tuning point is the pre-tuning point found before the power is increased in the two stages. The first pre-tuning point is the tuning point found before the low-power tuning state enters the pulse search state, so that when entering the pulse search state to increase the power, the input power to the cavity can be maximized and the power reflected back by the cavity can be minimized, that is, the Q value of the cavity is the highest. The second pre-tuning point is the tuning point found before entering the power increase state from the pulse search state, that is, the tuning point is found for the second time in the pulse search stage, so that when entering the power increase state, the input power to the cavity can be maximized and the power reflected back by the cavity can be minimized; the pulse closed-loop mode is to use a pulse with a fixed duty cycle to replace the high-level continuous mode under the pulse search, power increase, and normal operation state, thereby solving the problem of excessive power burning the transmitter and the coupling window during the debugging process. At the same time, since the tuning point is judged at the high level of the pulse, it does not affect the judgment of the tuning closed loop and also takes into account the problem of avoiding excessive power burning the transmitter and the coupling window.

[0057] 2. Difficulties in the design of the present invention: One of the difficulties is to achieve tuning under ultra-low power. 1) Compared with the lowest power of 1 watt in the prior art, the low power of the present invention is only tens of milliwatts, which is more than 100 times different. Because the cavity signal is weak under the ultra-low power signal, it cannot enter the phase detection range of the phase detector; 2) When tuning from low power to pulse search state, the tuning point will also change if the power changes, and it is necessary to find the tuning point again. When the tuning point is found again, the sampled cavity signal is a high-power signal, and the high-power signal will burn the phase detector when entering the phase detector; 3) The PID algorithm is required to adapt to the rate of state change and the requirements of the data processing speed of the previous state and the next state. The PID output result is used to control the motor of the cavity so that the cavity signal and the high-frequency signal are consistent, thereby realizing the tuning closed loop. Before the next state is reached, the PID is required to complete the processing of the data of the previous state, so as not to mix the data of the next state and the previous state together because the data of the previous state has not been processed, resulting in output errors. The second difficulty is that under high power conditions, it is necessary to meet high power requirements while preventing the cavity from being punctured and destroyed.

[0058] 3. Solution of the present invention: The solution to the first difficulty is: 1) Set up three high-frequency switches, set up high-frequency switch 1 and high-frequency switch 2 in the tuning module, and set up amplifiers and attenuators corresponding to high-frequency switches 1 and 2. Set up high-frequency switch 3 in the low-level modulation output module, and set up 3db and 14db attenuators. When in the low-power tuning state, the amplifier is selected through the high-frequency switches 1 and 2. The amplifier is 25db, so that the signal is amplified and enters the phase detector range, thereby solving the problem that the signal power is too low and it is not easy to enter the phase detector range. In order to ensure that the ultra-low power signal is input to the cavity in the low-power tuning state, the high-frequency switch 3 is also required to select a 14db attenuator to ensure that the signal output to the cavity is an ultra-low power signal of tens of millivolts; 2) When switching to the power search state, in order to prevent the cavity sampling signal from burning the phase detector, the high-frequency switches 1 and 2 select the attenuator. This attenuation is based on the standard of not burning the phase detector. Therefore, the attenuator should be designed moderately (23db attenuation); in order to ensure that the high-power signal is input to the cavity in the power search state, the high-frequency switch 3 is also required to select a 3db attenuator. Different attenuators are selected by the high-frequency switch 3 to increase or decrease the power. 3) Speed ​​up PID processing: Method 1 is to execute several instructions together, including addition instructions, multiplication instructions, input instructions, output instructions, and shift instructions, which speeds up the serial execution of instructions compared to conventional methods; Method 2 is to use assembly language, which is more basic than other languages, so it has a fast operation speed; Method 3 is to use a multi-bus architecture, which further highlights the effect of parallel processing compared to an architecture with only one bus. The above three methods support and depend on each other, and none of them can be missing. Only the combination of the three can achieve the best effect.

[0059] The solution to the second problem is: in the power search state, power boost state, and formal operation state, replace the high-power continuous signal with a pulse signal with a fixed duty cycle; in the power search state, use the high level of the pulse to judge the tuning closed loop; in the power boost state, use the high level of the pulse to judge the amplitude closed loop; in the formal operation state, change the high-power continuous signal into a pulse signal with a fixed duty cycle. In this way, a discrete high-power pulse signal is used to replace the high-power continuous signal, reducing the cumulative effect of the high-power signal. Since the power of the discrete pulse signal has not been reduced, it also meets the high power requirements of the power search state, power boost state, and formal operation state. Among them, the power of the power boost state and the formal operation state is higher than the power of the pulse search state, because this power is the power after the power boost after the pulse search state.

[0060] 4. The present invention provides a cyclotron optimization startup device based on a pulse closed-loop mode, such as Figure 1As shown, the device includes a tuning module based on a pulse closed-loop mode for finding a tuning point, a low-level modulation output module based on a pulse closed-loop mode, an amplitude demodulation module based on a pulse closed-loop mode, a CPU based on a pulse closed-loop mode, and a digital controller based on a pulse closed-loop mode; the CPU based on the pulse closed-loop mode is provided with a state machine for controlling the high-frequency cavity startup process, and the state machine includes a shutdown state s0, a low-power tuning state s1, a pulse search state s2, a power boost state s3, and a normal operation state s4 during the high-frequency cavity startup process; the digital controller based on the pulse closed-loop mode is provided with a PID tuning algorithm unit, a DSP balancing algorithm unit, and a signal receiving unit from an analog circuit and realizing communication with the CPU; the PID tuning algorithm unit avoids cavity detuning by accelerating the PID operation rate; the DSP balancing algorithm unit ensures the cavity pressure balance of the two groups of cavities by adjusting the capacitor motor;

[0061] Its characteristics are: the tuning module for finding tuning points based on the pulse closed-loop mode makes the cavity frequency and the high-frequency signal frequency consistent by finding the tuning points in the low-power tuning stage and the pulse search stage to meet the conditions for accelerating particles, wherein the pulse search stage crosses the electron multiplication effect region by outputting a high-power pulse signal; the pulse closed-loop mode, that is, the closed-loop mode of the low-power tuning state is a continuous closed-loop mode, and the closed-loop mode of the pulse search state and the power boost state is a pulse closed-loop mode.

[0062] Supplementary Note 1:

[0063] 1. Figure 1 It is divided into three parts: upper, middle and lower. The top layer is the tuning module, the bottom layer is the amplitude demodulation module, and the middle layer is the low-level output module. The top and bottom layers are sampling from the cavity, and the middle layer is inputting high-frequency signals to the cavity. The purpose of sampling from the cavity is to perform tuning closed loop and amplitude closed loop; the purpose of inputting high-frequency signals to the cavity is to increase the power of the cavity to the voltage that can accelerate particles, and to ensure that the cavity frequency is stable at the high-frequency signal frequency, so as to achieve the purpose of accelerating particles.

[0064] 2. However, the power increase must meet two conditions. The first is to find the tuning point, that is, the tuning closed loop. At this time, the signal output to the cavity can increase the power; the second is the amplitude closed loop. Although the tuning closed loop finds the tuning point, the power may still not reach the set height, so it is necessary to realize the amplitude closed loop, that is, the amplitude reaches the set height. Therefore, the low-level output signal of the middle layer is a process of power from low to high.

[0065] The pulse closed-loop mode sets only the low-power tuning state as the continuous signal operation mode, while the power search state, power boost state, and normal operation state are all pulse signal operation modes, and only the tuning closed loop in the low-power tuning state is a closed loop in the continuous signal operation mode, while the tuning closed loop in the power search state and the amplitude modulation closed loop under power boost are all closed loops under pulse signals, and the closed loop under the pulse signal is determined to be closed when the pulse is at a high level.

[0066] Supplementary Note 2

[0067] The pulse closed-loop mode means that except for the low-power tuning state which is a continuous closed-loop, the power search state and the power boost state are all closed-loop under the high level of the pulse signal.

[0068] The tuning module for finding the tuning point based on the pulse closed-loop mode is provided with a cavity forward signal Forward, a cavity sampling signal Pickup1, a high-frequency switch 1 and a high-frequency switch 2, an amplifier and an attenuator, a phase detector, a tuning parameter setting module and a tuning comparator in sequence between the accelerator cavity and the CPU; in the low-power tuning state, the CPU state machine turns from the off state s0 to the low-power tuning state s1, and sends s1 to the digital controller, and the digital controller gives the high-frequency switch 1 and the high-frequency switch 2 of the tuning module, and the high-voltage switch of the low-level modulation output module. Switch 3 is a low-level signal, the forward signal Forward of the cavity and the cavity sampling signal Pickup1 are selected to connect to their respective amplifiers through high-frequency switch 1 and high-frequency switch 2, and the high-voltage switch 3 selects a 14db attenuator; in the power search state, power boost state, and normal operation state, the CPU state machine respectively switches s2, s3, and s4 according to the continuous tuning closed-loop signal PhaseOK in the low-power tuning state, the pulse amplitude closed-loop signal PhaseOK in the pulse search state, and the pulse amplitude closed-loop signal VDeeOK in the power boost state. The s4 signal is sent to the digital controller, and the digital controller gives a high level to the high-frequency switch 1 and high-frequency switch 2 of the tuning module and the high-voltage switch 3 of the low-level modulation output module. The forward signal Forward of the cavity and the cavity sampling signal Pickup1 are selected to connect to their respective attenuators through the high-frequency switch 1 and the high-frequency switch 2, and the high-voltage switch 3 is connected to a 3db attenuator; the ADC analog signal derived from the phase detector is subtracted from the tuning parameter setting value, and the operation result is sent to the digital controller through the ADC and the other way to the tuning comparator; in the low-power tuning state, the tuning comparator of the tuning module uses a continuous signal to judge the tuning closed loop, and in the pulse search state, the tuning comparator of the tuning module uses a pulse high-level signal to judge the tuning closed loop. When the tuning comparator judges that the cavity frequency and the high-frequency signal frequency are consistent, the tuning closed loop signal PhaseOK is output respectively, and the signal is sent to the CPU through the digital controller; the cavity forward signal Forward and the cavity sampling signal Pickup1 are obtained by sampling the sampling cable after the low-level modulation output module drives the accelerator cavity.

[0069] Supplementary Note 3

[0070] The relationship between the tuning module and the other two modules. Although it is an independent module, the tuning module is inseparable from the low-level output signal of the low-level output module: the low-level output signal drives the accelerator cavity to generate the cavity forward signal Forward and the cavity sampling signal Pickup1; the tuning module is also inseparable from the control of the CPU state machine. The CPU state machine controls the high-frequency switches 1 and 2 of the tuning module, and controls the high-frequency switch 3 at the same time. Although the high-frequency switch 3 belongs to the low-level output module, it will also affect the tuning closed loop of the second stage of the tuning module, that is, the power search stage: specifically, in the power search stage, the power of the cavity signal entering the high-frequency switches 1 and 2 is enhanced. At this time, it is not necessary to select an amplifier but an attenuator, because the signal is too strong, so it needs to be attenuated to facilitate the phase detection of the phase detector. Only when it enters the phase detection range of the phase detector can the tuning closed loop judgment under the subsequent power search state be performed. The power of the cavity signal entering the high-frequency switches 1 and 2 is enhanced because the high-frequency switch selects a 3db attenuator to enhance the power of the signal entering the cavity. In short, the tuning module is inseparable from the other two modules because the tuning module serves two stages. Only when the tuning module is organically combined with the other two modules can the tuning closed-loop judgment of the two stages be realized.

[0071] Furthermore, the amplitude demodulation module based on the pulse closed-loop mode is sequentially provided with a cavity sampling signal Pickup2, a detector, a pulse-to-continuous circuit, an amplitude modulation parameter setting module and an amplitude comparator between the accelerator cavity and the CPU; after the cavity sampling signal Pickup2 is two centimeters, one path passes through a differential circuit for ignition detection judgment, and the other path passes through a detector for amplitude closed-loop judgment; in the power boost state, when the voltage value of the detector detection result is subtracted from the amplitude modulation parameter setting and it is judged to be within the allowable range, it is judged to be an amplitude closed-loop, and a pulse amplitude closed-loop signal VDee_OK is output to the CPU.

[0072] Furthermore, the low-level modulation output module based on the pulse closed-loop mode is provided with a high-frequency signal digital-to-analog module, an amplitude-phase modulation module, a 3db attenuator and a 14db attenuator, a high-frequency switch 3, a digitally controlled attenuator, and a low-level output signal in sequence along the direction from the digital controller to the accelerator cavity; in the low-power tuning state, the low-level output signal drives the accelerator cavity, thereby obtaining the cavity forward signal Forward and the cavity sampling signal Pickup1 of the tuning module through the sampling cable; in the power search state, after the CPU receives the continuous tuning closed-loop PhaseOK signal of the low-power tuning state, the CPU state machine sends an s2 signal to the digital controller, and the digital controller sends a pulse with a certain duty cycle to the high-frequency switch 3, and the high-frequency switch 3 performs the sampling according to the fixed duty cycle. Compared with the pulse, when the pulse is at a high level, a 3db attenuator is connected, and when the pulse is at a low level, a 14db attenuator is connected. At this time, the digitally controlled attenuator is a fixed value and remains unchanged; in the power boost state, after the CPU receives the pulse tuning closed-loop signal PhaseOK of the pulse search state, its state machine sends an s3 signal to the digital controller, and the digital controller sends a pulse with a certain duty cycle to the high-frequency switch 3. The high-frequency switch 3 connects a 3db attenuator when the pulse is at a high level and a 14db attenuator when the pulse is at a low level according to the fixed duty cycle pulse. At the same time, the digital controller controls the digitally controlled attenuator to continuously reduce the attenuation, and then continuously increase the power until the amplitude modulation comparator of the amplitude demodulation module outputs a pulse amplitude closed-loop signal VDeeOK to the CPU. At this time, the power boost stage is completed and the normal operation stage is entered.

[0073] Supplementary Note 5

[0074] 1. The relationship between the low-level modulation output module and the other two types of modules: The purpose of setting the low-level modulation output module is to input signals of different powers to the cavity in different states. At the same time, the low-level modulation output module also requires the cooperation of the other two modules: in the low-power tuning state, since the signal power output to the cavity is very low, the high-frequency switches 1 and 2 of the tuning module are required to amplify the signal through the amplifier, and the high-frequency switch 3 of the low-power output module is required to select 14db attenuation all the way; in the power search stage, power boost state, and normal operation state, since the signal power output to the cavity is enhanced, the three high-frequency switches are required to select the filter all the way or the 3db attenuator;

[0075] 2. The low-level modulation output module also controls the signal power output to the cavity in four states through the combination of high-frequency switch 3 and digitally controlled attenuator. When in the low-power tuning state, high-frequency switch 3 selects 14db attenuator and the digitally controlled attenuator remains constant; in the pulse search state, high-frequency switch 3 selects 3db attenuator and the digitally controlled attenuator remains constant; in the power boost state, the digital controller controls the digitally controlled attenuator to continuously reduce the attenuation and high-frequency switch 3 selects 3db attenuator; in the normal operating stage, high-frequency switch 3 selects 3db attenuator and the digitally controlled attenuator remains constant.

[0076] Furthermore, when the CPU receives the pulse amplitude closed-loop signal VDeeOK in the power boost state, its state machine sends an s4 signal to the digital controller, and the digital controller gives a high-level signal to high-frequency switches 1, 2, and 3 respectively. High-frequency switches 1 and 2 select one attenuator respectively, and high-frequency switch 3 selects a 3db attenuator. The digital controller sends a pulse with a certain duty cycle to high-frequency switch 3. High-frequency switch 3 is connected to a 3db attenuator when the pulse is high level, and is connected to a 14db attenuation when the pulse is low level. The digitally controlled attenuator remains unchanged at a fixed value. At the same time, the digital controller starts the DSP balancing algorithm unit to balance the cavity pressure between the two cavities.

[0077] Furthermore, the PID tuning algorithm is provided with a PID operation module, a data arithmetic logic module, and a multi-bus architecture; the data arithmetic logic module is used to realize the addition and multiplication functions in the PID operation, and the PID operation module describes the PID digital operation algorithm in the assembly language of DSP and uses parallel processing instructions under the multi-bus architecture to realize the synchronous execution of multiple operation instructions, thereby speeding up the PID operation rate and avoiding cavity detuning.

[0078] Further, the PID numerical operation module is provided with a PID operation output y(n) submodule, a PID operation output y(n-1) submodule at the previous moment, a PID adjustment coefficient K0, K1, K2 submodule, and a PID input submodule of x(n), x(n-1) and x(n-2) at the current moment, the previous moment and the previous two moments; the data arithmetic logic module includes a DSP5600 series digital signal processor, which stores the PID input x(n), x(n-1) and x(n-2) at the current moment, the previous moment and the previous two moments in register R0, stores the PID adjustment coefficients k0, k1, k2 in register R3, uses a global bus to read and write these two registers, and uses the accumulator and multiplication functions in the DSP to implement y(n)=y(n-1)+k0*x(n)+k1*x(n-1)+k2*x(n-2) using assembly instructions;

[0079] Supplementary Note 6

[0080] This parallel assembly instruction effectively improves the operation rate of the PID algorithm. The output result of the y(n) submodule is used to tune the movement of the motor to change the resonant frequency of the cavity, thereby affecting the phase difference between the cavity sampling signal and the forward signal, so that the output voltage of the phase detector approaches the set voltage of the parameter setting module. The set voltage of the parameter setting module is the voltage of the phase difference between the cavity sampling signal and the cavity forward signal when the preset cavity frequency and the high-frequency signal frequency are consistent. The output voltage of the phase detector is the voltage of the actual phase difference between the cavity sampling signal and the cavity forward signal.

[0081] Furthermore, the DSP balancing algorithm unit is provided with a voltage balancing ratio calculating unit and a voltage balancing adjusting unit; the voltage balancing ratio calculating unit is used for the ratio relationship: Among them, C12 is the coupling capacitance value between the two groups of cavities, which is divided into two parts C12" and C12', wherein C12" is the capacitance of the D1 cavity, and C12' is the capacitance of the D2 cavity; the voltage balancing unit can adjust the cavity D plate voltage by changing the ratio of C12" and C12'.

[0082] Furthermore, the CPU based on the pulse closed-loop mode uses the s1, s2, s3, and s4 states of the state machine to control the digital controller, and the digital controller then controls the high-frequency switches 1, 2, and 3.

[0083] Supplementary Note 7

[0084] In the low-power tuning stage, the CPU determines that the current accelerator cavity is in the power-on state, changes s0 of the state machine to s1 and sends s1 to the digital controller. The digital controller sends low-level signals to high-frequency switches 1, 2, and 3. High-frequency switches 1 and 2 select amplifiers respectively, and high-frequency switch 3 selects a 14db attenuator.

[0085] In the power search phase, after the CPU receives the tuning closed-loop signal PhaseOK from the tuning module, it converts s1 to s2 and sends s2 to the digital controller. The digital controller gives the high-frequency switches 1, 2, and 3 a pulse signal with a fixed width. The high-frequency switches 1 and 2 select one amplifier when the pulse is at a low level, and one attenuator when the pulse is at a low level. The high-frequency switch 3 selects one 14db attenuator when the pulse is at a low level, and selects one 3db attenuator when the pulse is at a high level.

[0086] In the power boost stage, after the CPU receives VDeeOK from the amplitude demodulation module, it converts s2 to s3 and sends s3 to the digital controller. The digital controller gives a widened pulse signal to high-frequency switches 1, 2, and 3. High-frequency switches 1 and 2 select one amplifier when the pulse is at a low level, and one attenuator when the pulse is at a low level. High-frequency switch 3 selects one 14db attenuator when the pulse is at a low level, and selects one 3db attenuator when the pulse is at a high level. At the same time, the digital controller also controls the digital attenuator to reduce attenuation.

[0087] During the normal operation stage, after the CPU has received the secondary tuning closed-loop signal PhaseOK from the tuning module and the amplitude demodulation module VDeeOK, it converts s3 into s4 and sends s4 to the digital controller. The digital controller gives a fixed-width pulse signal to high-frequency switches 1, 2, and 3. High-frequency switches 1 and 2 select one amplifier when the pulse is at a low level, and one attenuator when the pulse is at a low level. High-frequency switch 3 selects one 14db attenuator when the pulse is at a low level, and selects one 3db attenuator when the pulse is at a high level. At the same time, the digital controller controls the digital attenuator to a fixed value.

[0088] The present invention designs a cyclotron optimization startup method based on a pulse closed-loop mode. The method is based on a cyclotron optimization startup device based on a pulse closed-loop mode of the present invention. The device is described in detail in point 4 of [Design Principle of the Present Invention].

[0089] The method is characterized in that it comprises the following steps:

[0090] Step 1: Initialization preparation

[0091] 1) Establish a one-button start-up process for the cyclotron low-level system;

[0092] 2) Establish a CPU state machine, the state of the state machine is S0~S4;

[0093] Step 2: Enter the low power tuning state in the pulse closed loop mode and realize the tuning closed loop in the low power tuning state;

[0094] Step 3: Enter the pulse search state in the pulse closed-loop mode and implement the tuning closed-loop in the pulse search state;

[0095] Step 4: Enter the power boost state in the pulse closed-loop mode and realize the amplitude closed-loop in the power boost state;

[0096] Step 5: Enter the normal operating state under the pulse closed-loop mode and achieve cavity pressure balance under the normal operating state.

[0097] Furthermore, the step 2 of entering the low-power tuning state in the pulse closed-loop mode and realizing the tuning closed-loop in the low-power tuning state is specifically performed as follows:

[0098] 1) The low-level modulation output module inputs a low-level pulse signal to the accelerator cavity, and the low-level pulse signal drives the accelerator cavity, and obtains the cavity forward signal Forward, cavity sampling signal Pickup1, and cavity sampling signal Pickup2 of the tuning module through the sampling cable from the accelerator;

[0099] 2) The CPU state machine changes from the shutdown state s0 to the low power tuning state s1 and sends s1 to the digital controller.

[0100] 3) The digital controller gives a low level signal to the high frequency switch 1 and high frequency switch 2 of the tuning module and the high voltage switch 3 of the low level modulation output module respectively;

[0101] 4) The forward signal Forward of the cavity and the cavity sampling signal Pickup1 are connected to their respective amplifiers through high-frequency switch 1 and high-frequency switch 2 to ensure that the low-power signal can enter the phase detector range; high-voltage switch 3 selects a 14db attenuator;

[0102] 5) performing a subtraction operation on the ADC analog signal derived from the phase detector and the tuning parameter setting value, and sending the operation result to the digital controller through the ADC in one way and to the tuning comparator in the other way;

[0103] 6) The PID tuning algorithm unit performs a tuning closed-loop operation under low-power tuning state: when it is determined that the cavity frequency and the high-frequency signal frequency are consistent, a tuning closed-loop signal PhaseOK is output to the CPU to implement the tuning closed-loop under low-power tuning state and enter the pulse search phase; under low-power tuning state, the tuning comparator determines the tuning closed-loop under continuous signals.

[0104] Supplementary Note 1

[0105] The digital controller is provided with a PID tuning algorithm unit and a DSP balancing algorithm unit. The PID tuning algorithm unit avoids cavity detuning by accelerating the PID operation rate; the DSP balancing algorithm unit ensures the cavity pressure balance of the two groups of cavities by adjusting the capacitor motor; the PID tuning algorithm unit tunes the movement of the cavity motor through the output result of the y(n) submodule to change the resonant frequency of the cavity, thereby affecting the phase difference between the cavity sampling signal and the forward signal, so that the output voltage of the phase detector approaches the set voltage of the parameter setting module, the set voltage of the parameter setting module is the voltage of the phase difference between the cavity sampling signal and the cavity forward signal when the preset cavity frequency and the high-frequency signal frequency are consistent, and the output voltage of the phase detector is the voltage of the actual phase difference between the cavity sampling signal and the cavity forward signal.

[0106] Furthermore, the step 3 of entering the pulse search state in the pulse closed-loop mode and realizing the tuning closed-loop in the pulse search state is specifically performed as follows:

[0107] 1) After receiving the tuning closed-loop signal PhaseOK in the low-power tuning state, the CPU sends the s2 signal to the digital controller;

[0108] 2) The digital controller sends a pulse signal with a fixed duty cycle to high-frequency switch 3, and to high-frequency switches 1 and 2 at the same time;

[0109] 3) The high-frequency switches 1 and 2 of the tuning module select one attenuator according to the high-level signal of the pulse signal with a fixed duty cycle. Since the power is increased in the pulse search state, the cavity forward signal Forward and the cavity sampling signal Pickup1 after the power is increased enter the phase detector through the attenuator; the high-frequency switch 3 selects one 3db attenuator when the pulse is at a high level and one 14db attenuator when the pulse is at a low level according to the pulse signal with a fixed duty cycle, thereby realizing equal-width pulses in the power search state;

[0110] 4) performing a subtraction operation on the ADC analog signal derived from the phase detector and the tuning parameter setting value, and sending the operation result to the digital controller through the ADC in one way and to the tuning comparator in the other way;

[0111] 5) The PID tuning algorithm unit performs a tuning closed-loop operation in the pulse search state: when it is determined that the cavity frequency and the high-frequency signal frequency are consistent, a pulse tuning closed-loop signal PhaseOK is output to the CPU to implement the pulse tuning closed-loop in the pulse search state, and the tuning comparator is closed to enter the power boost state; in the pulse search state, the tuning comparator determines the tuning point when the pulse is at a high level.

[0112] Furthermore, the step 4 of entering the power boost state in the pulse closed-loop mode and realizing the amplitude closed-loop in the power boost state is specifically performed as follows:

[0113] 1) After receiving the pulse tuning closed-loop signal PhaseOK in the power search state, the CPU sends the s3 signal to the digital controller;

[0114] 2) The digital controller sends a pulse signal with a fixed duty cycle to high-frequency switch 3, and to high-frequency switches 1 and 2 at the same time;

[0115] 3) The high-frequency switch 3 selects a 3db attenuator when the pulse is at a high level and a 14db attenuator when the pulse is at a low level according to the pulse signal with a fixed duty cycle, thereby realizing equal-width pulses in the power boost state; the high-frequency switches 1 and 2 of the tuning module select an attenuator when the pulse signal with a fixed duty cycle is at a high level and selects an amplifier when the pulse is at a low level.

[0116] 4) The digital controller controls the digital controlled attenuator to continuously reduce the attenuation, and then continuously increase the power, until the amplitude modulation comparator of the amplitude demodulation module outputs the pulse amplitude closed-loop VDeeOK signal to the CPU. At this time, the power boost stage is completed, the amplitude closed-loop is realized, and the normal operation state is entered.

[0117] Supplementary Note 2:

[0118] Furthermore, the step 5 of entering the normal operation state under the pulse closed-loop mode and achieving cavity pressure balance under the normal operation state is specifically performed as follows:

[0119] 1) After receiving the pulse amplitude closed-loop signal VDee_OK in the power boost state, the CPU sends the s4 signal to the digital controller;

[0120] 2) The digital controller sends a pulse signal of equal width to high-frequency switch 3 and to high-frequency switches 1 and 2 at the same time;

[0121] 3) According to the pulse signal of fixed duty cycle, high frequency switch 3 selects one 3db attenuator when the pulse is at high level and one 14db attenuator when the pulse is at low level, so as to realize the pulse of fixed duty cycle under normal operation; high frequency switch 1 and high frequency switch 2 of the tuning module select one attenuator according to the high level signal of equal width pulse signal and select one amplifier when the pulse is at low level.

[0122] 4) The numerically controlled attenuator is a constant value;

[0123] 5) The digital controller starts the DSP balancing algorithm unit to balance the cavity pressure between the two cavities.

[0124] Furthermore, the digital controller of the process 5) starts the DSP balance algorithm unit to balance the cavity pressure between the two cavities, and the specific steps are as follows:

[0125] 1) When the two cavities of the accelerator are capacitively coupled, the voltage imbalance between the two cavities due to factors such as processing design is expressed by a ratio relationship:

[0126]

[0127] Among them, C 12 is the coupling capacitance between the two groups of cavities, which is divided into two parts C 12 ” and C 12 ', where C 12 ” is the capacitance of cavity D1, C 12 ' is the capacitance of cavity D2;

[0128] 2) Change C 12 ” and C 12 The D voltage can be adjusted by the ratio of ', and the balance control algorithm is as follows: the phase detector output result Tphase determines the movement frequency of the capacitor motor, and the motor movement step setting value Dsteps determines the movement steps of the motor. When Dsteps>0, Tphase>0, the D1 cavity group motor moves in the positive direction at 2 times the speed, and the D2 cavity group motor stops; when Dsteps>0, Tphase<0, the D2 cavity group motor moves in the reverse direction at 2 times the speed, and the D1 cavity group motor does not move; when Dsteps<0, TPhase>0, the D2 cavity group motor moves in the positive direction at twice the speed, and the D1 cavity group motor does not move; when Dsteps<0, TPhase<0, the D1 cavity group motor moves in the reverse direction at twice the speed, and the D2 cavity group motor does not move.

[0129] Furthermore, it is characterized in that: the PID tuning algorithm unit performs tuning closed-loop operation, and the implementation process is as follows:

[0130] 1) The digital PID algorithm is expressed as:

[0131] y(n)=y(n-1)+K0x(n)+K1x(n-1)+K2(n-2);

[0132] Where y(n) is the PID operation output, y(n-1) is the PID operation output at the previous moment, K0, K1, and K2 are PID adjustment coefficients, and x(n), x(n-1), and x(n-2) are the PID inputs at the current moment, the previous moment, and the previous two moments;

[0133] 2) Use R0 and R3 registers in the DSP's X memory, and read and write operations are performed by the global data bus;

[0134] 3) Store the PID inputs x(n), x(n-1) and x(n-2) of the current moment, the previous moment and the previous two moments into register R0, and store k0, k1, k2 into register R3;

[0135] 4) Use the global bus to read and write these two registers, and use the accumulator and multiplication functions in the DSP and assembly language to implement y(n)=y(n-1)+k0*x(n)+k1*x(n-1)+k2*x(n-2).

[0136] It should be emphasized that the above specific embodiments are merely explanations of the present invention, and they are not limitations of the present invention. After reading this specification, those skilled in the art can make modifications to the above embodiments without any creative contribution as needed, but as long as they are within the scope of the claims of the present invention, they are protected by patent law.

Claims

1. A cyclotron optimization startup method based on a pulse closed-loop mode, characterized in that: The following steps are involved: Step 1: Initialization preparation 1) Establish a one-button start-up process for the cyclotron low-level system; 2) Establish a CPU state machine, the state of the state machine is S0~S4; Step 2: Enter the low power tuning state in the pulse closed loop mode and realize the tuning closed loop in the low power tuning state; Step 3: Enter the pulse search state in the pulse closed-loop mode and implement the tuning closed-loop in the pulse search state; Step 4: Enter the power boost state in the pulse closed-loop mode and realize the amplitude closed-loop in the power boost state; Step 5: Enter the normal operation state under the pulse closed loop mode and achieve cavity pressure balance under the normal operation state; The specific process of step 2 of entering the low-power tuning state in the pulse closed-loop mode and realizing the tuning closed-loop in the low-power tuning state is as follows: 1) The low-level modulation output module inputs a low-level pulse signal to the accelerator cavity, and the low-level pulse signal drives the accelerator cavity, and obtains the cavity forward signal Forward, cavity sampling signal Pickup1, and cavity sampling signal Pickup2 of the tuning module through the sampling cable from the accelerator; 2) The CPU state machine changes from the shutdown state s0 to the low power tuning state s1 and sends s1 to the digital controller. 3) The digital controller gives a low level signal to the high frequency switch 1 and high frequency switch 2 of the tuning module and the high voltage switch 3 of the low level modulation output module respectively; 4) The forward signal Forward of the cavity and the cavity sampling signal Pickup1 are connected to their respective amplifiers through high-frequency switch 1 and high-frequency switch 2 to ensure that the low-power signal can enter the phase detector range; high-voltage switch 3 selects a 14db attenuator; 5) Subtract the ADC analog signal from the phase detector from the tuning parameter setting value, and send the result of the operation to the digital controller through the ADC and to the tuning comparator through the other path; 6) The PID tuning algorithm unit performs tuning closed-loop operation in the low-power tuning state: when it is determined that the cavity frequency and the high-frequency signal frequency are consistent, the tuning closed-loop signal PhaseOK is output to the CPU to achieve tuning closed-loop in the low-power tuning state and enter the pulse search phase; in the low-power tuning state, the tuning comparator determines the tuning closed-loop under the continuous signal; The specific process of step 3 of entering the pulse search state in the pulse closed-loop mode and realizing the tuning closed-loop in the pulse search state is as follows: 1) After receiving the tuning closed-loop signal PhaseOK in the low-power tuning state, the CPU sends the s2 signal to the digital controller; 2) The digital controller sends a pulse signal with a fixed duty cycle to high-frequency switch 3, and to high-frequency switches 1 and 2 at the same time; 3) The high-frequency switches 1 and 2 of the tuning module select one attenuator according to the high-level signal of the pulse signal with a fixed duty cycle. Since the power is increased in the pulse search state, the cavity forward signal Forward and the cavity sampling signal Pickup1 after the power is increased enter the phase detector through the attenuator; the high-frequency switch 3 selects one 3db attenuator when the pulse is at a high level and one 14db attenuator when the pulse is at a low level according to the pulse signal with a fixed duty cycle, thereby realizing equal-width pulses in the power search state; 4) The ADC analog signal derived from the phase detector is subtracted from the tuning parameter setting value, and the calculation result is sent to the digital controller through the ADC and to the tuning comparator in another way; 5) The PID tuning algorithm unit performs tuning closed-loop operation in the pulse search state: when it is determined that the cavity frequency and the high-frequency signal frequency are consistent, it outputs the pulse tuning closed-loop signal PhaseOK to the CPU to implement the pulse tuning closed-loop in the pulse search state, and closes the tuning comparator to enter the power boost state; In the pulse search state, the tuning comparator determines the tuning point when the pulse is high level; The specific process of step 4 of entering the power boost state in the pulse closed-loop mode and realizing the amplitude closed-loop in the power boost state is as follows: 1) After receiving the pulse tuning closed-loop signal PhaseOK in the power search state, the CPU sends the s3 signal to the digital controller; 2) The digital controller sends a pulse signal with a fixed duty cycle to high-frequency switch 3, and to high-frequency switches 1 and 2 at the same time; 3) According to the pulse signal of the fixed duty cycle, the high-frequency switch 3 selects one 3db attenuator when the pulse is at a high level, and selects one 14db attenuator when the pulse is at a low level, so as to realize the equal-width pulse in the power boost state; the high-frequency switches 1 and 2 of the tuning module select one attenuator according to the high-level signal of the pulse signal of the fixed duty cycle, and select one amplifier according to the low-level signal; 4) The digital controller controls the digital controlled attenuator to continuously reduce the attenuation, and then continuously increase the power, until the amplitude modulation comparator of the amplitude demodulation module outputs the pulse amplitude closed loop VDeeOK signal to the CPU. At this time, the power boost stage is completed, the amplitude closed loop is realized, and the normal operation state is entered; The step 5 enters the normal operation state under the pulse closed loop mode and realizes the cavity pressure balance under the normal operation state. The specific process is as follows: 1) After receiving the pulse amplitude closed-loop signal VDee_OK in the power boost state, the CPU sends the s4 signal to the digital controller; 2) The digital controller sends a pulse signal of equal width to high-frequency switch 3 and to high-frequency switches 1 and 2 at the same time; 3) According to the pulse signal of the fixed duty cycle, the high-frequency switch 3 selects a 3db attenuator when the pulse is at a high level, and selects a 14db attenuator when the pulse is at a low level, thereby realizing a pulse of the fixed duty cycle under normal operating conditions; The high-frequency switch 1 and the high-frequency switch 2 of the tuning module select one attenuator according to the high-level signal of the equal-width pulse signal, and select one amplification channel when the signal is at a low level; 4) The numerically controlled attenuator is a constant value; 5) The digital controller starts the DSP balancing algorithm unit to balance the cavity pressure between the two cavities.

2. The cyclotron optimization startup method based on the pulse closed-loop mode according to claim 1, characterized in that: The digital controller of step 5) starts the DSP balance algorithm unit to balance the cavity pressure between the two cavities. The specific steps are as follows: 1) When the two cavities of the accelerator are capacitively coupled, the voltage imbalance between the two cavities due to processing design factors is expressed by a ratio relationship: Among them, C 12 is the coupling capacitance between the two groups of cavities, which is divided into two parts C 12 ” and C 12 ', where C 12 ” is the capacitance of cavity D1, C 12 ' is the capacitance of cavity D2; 2) Change C 12 ” and C 12 The D voltage can be adjusted by the ratio of ', and the balance control algorithm is as follows: the phase detector output result Tphase determines the movement frequency of the capacitor motor, and the motor movement step setting value Dsteps determines the movement steps of the motor. When Dsteps>0, Tphase>0, the D1 cavity group motor moves in the positive direction at 2 times the speed, and the D2 cavity group motor stops; when Dsteps>0, Tphase<0, the D2 cavity group motor moves in the reverse direction at 2 times the speed, and the D1 cavity group motor does not move; when Dsteps<0, TPhase>0, the D2 cavity group motor moves in the positive direction at twice the speed, and the D1 cavity group motor does not move; when Dsteps<0, TPhase<0, the D1 cavity group motor moves in the reverse direction at twice the speed, and the D2 cavity group motor does not move.

3. The cyclotron optimization startup method based on the pulse closed-loop mode according to claim 1, characterized in that: The PID tuning algorithm unit performs a closed-loop tuning operation in a low-power tuning state, and the implementation process is as follows: 1) The digital PID algorithm is expressed as: y(n)=y(n-1)+K0x(n)+K1x(n-1)+K2(n-2); Where y(n) is the PID operation output, y(n-1) is the PID operation output at the previous moment, K0, K1, and K2 are PID adjustment coefficients, and x(n), x(n-1), and x(n-2) are the PID inputs at the current moment, the previous moment, and the previous two moments; 2) Use R0 and R3 registers in the DSP's X memory, and read and write operations are performed by the global data bus; 3) Store the PID inputs x(n), x(n-1) and x(n-2) of the current moment, the previous moment and the previous two moments into register R0, and store k0, k1, k2 into register R3; 4) Use the global bus to read and write these two registers, and use the accumulator and multiplication functions in the DSP and assembly language to implement y(n)=y(n-1)+k0*x(n)+k1*x(n-1)+k2*x(n-2).

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