A tunneling power device and a manufacturing method thereof

Abstract

The present invention discloses a tunneling power device and a manufacturing method thereof. It includes an N-type substrate, an N-type epitaxial layer, a first source region with an inclined sidewall, a P-type region is provided below the first source region, a gate oxide layer and a gate electrode are provided above the epitaxial layer, a passivation layer is provided above the gate electrode, a second source region is provided on the upper surface of the first source region, and a drain metal is provided on the lower surface of the substrate. The advantages of the present invention are that the tunneling power device reduces the leakage current when the device is turned off; the Schottky contact formed by the first source region and the drift region improves the third quadrant characteristics of the device and reduces the dynamic power consumption of the device; significantly reduces the cell width of the power device, has a lower on-resistance, and reduces the static power consumption of the device; the first source region with an inclined sidewall weakens the depletion effect of the tunneling point and at the same time weakens the electrostatic shielding effect, improving the forward conduction current of the device.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor power devices, and particularly relates to a tunneling power device and a manufacturing method thereof. Background Art

[0002] Power semiconductor devices play a crucial role in the power electronics industry and have wide applications in automobiles, household appliances, high-speed railways, and power grids. The demand for power devices is increasing. However, traditional power devices have many disadvantages, such as large on-resistance, high threshold voltage, large subthreshold swing, complex manufacturing process, and the doping process is prone to generating damage to form traps, which affect the device performance.

[0003] The tunneling field effect transistor (TFT) is a new type of device that conducts current using the quantum tunneling mechanism. Compared with traditional MOSFETs, due to its different conduction mechanism, it has advantages such as lower subthreshold swing and better performance in the low-power field. The structure of TFET is similar to that of MOSFET, and the technical concepts used to improve the performance of MOSFET are also applicable to optimizing TFET, which can reduce the R & D cost and cycle. In addition, only the carriers in the tunneling window (the energy interval between the valence band quasi-Fermi level of the source region and the conduction band quasi-Fermi level of the channel) in TFET can undergo the tunneling effect, while the carriers with higher energy are all "filtered" and cannot enter the channel. Therefore, TFET can effectively suppress the hot carrier effect, and the reliability of the device is relatively high. Figure 1 It is a structural diagram of a unit cell of a conventional vertical-channel planar-gate tunneling silicon carbide power semiconductor device. However, in the actual application of TFET, due to the electrostatic interaction between the metal gate and the source region metal, the electron concentration in the accumulation layer is reduced, thereby affecting the tunneling effect of TFET and ultimately resulting in a decrease in the operating current of the device. Summary of the Invention

[0004] The purpose of the present invention is to provide a tunneling power device and a manufacturing method thereof to solve the technical problem that in the actual application of TFET, due to the electrostatic interaction between the metal gate and the source region metal, the electron concentration in the accumulation layer is reduced, thereby affecting the tunneling effect of TFET and ultimately resulting in a decrease in the operating current of the device.

[0005] To solve the above technical problem, the specific technical solution of the present invention is as follows:

[0006] A tunneling power device, comprising: an N-type substrate, a drain metal provided on one surface of the N-type substrate, an N-type epitaxial layer provided on the other surface of the N-type substrate, a P-type region provided on the N-type epitaxial layer, a first source region with inclined sidewalls provided on the P-type region, a second source region and a gate oxide layer connected to the first source region, a gate electrode provided above the gate oxide layer, and a passivation layer provided above the gate electrode, the passivation layer separating the gate electrode and the second source region.

[0007] Further, the sidewalls of the first source region are inclined, forming a first angle and a second angle with the gate electrode, wherein the first angle is an acute angle and the second angle is an obtuse angle.

[0008] Further, the P-type region withstands the breakdown voltage when the device is reverse-biased, and its doping concentration typical value is 1×10 17 cm -3 .

[0009] Further, the material of the first source region uses polysilicon, metal, graphene, molybdenum disulfide or other materials that can form the source region of a tunneling power semiconductor device.

[0010] Further, the doping concentration typical value of the N-type epitaxial layer is 1×10 15 ~1×10 17 cm -3 , and the material of the N-type epitaxial layer uses silicon carbide, gallium oxide, silicon, diamond or other materials that can form the drift region of a tunneling power semiconductor device.

[0011] Further, the material of the N-type substrate uses silicon carbide, gallium oxide, silicon, diamond or other materials that can form the substrate of a tunneling power semiconductor device.

[0012] The present invention also discloses a manufacturing method of a tunneling power device, comprising the following steps:

[0013] Step 1: Take an N-type substrate and form an N-type epitaxial layer on one surface of the N-type substrate;

[0014] Step 2: Use an ion implantation process to form a P-type region;

[0015] Step 3: Use an etching process to etch the inclined angle of the N-type substrate multiple times to form a trench of the first source region;

[0016] Step 4: Use a sputtering process or a CVD process to fill the trench of the first source region with a first source material;

[0017] Step 5: Use an etching process to etch the excess first source material on the surface of the trench of the first source region to form the first source region;

[0018] Step 6: Deposit an oxide layer on the N-type epitaxial layer using the CVD process;

[0019] Step 7: Use an etching process to etch the excess oxide layer in Step 6 to form a gate oxide layer;

[0020] Step 8: Use the CVD process to form a gate electrode above the gate oxide layer;

[0021] Step 9: Use the CVD process to form a passivation layer above the gate electrode;

[0022] Step 10: Use a sputtering process to form the second source region and drain metal.

[0023] A tunneling power device and its manufacturing method according to the present invention have the following advantages:

[0024] 1. Compared with a conventional metal-semiconductor field-effect transistor (MOSFET), the tunneling field-effect transistor (TFET) of the present invention can achieve a lower subthreshold swing, reduce the leakage current at low voltages, reduce the power consumption of the device during the switching process, and improve the switching characteristics of the device. At the same time, when the device is turned off, the P-type region under the first source region will form a depletion layer as shown in the figure with the N-type drift layer, and the depletion layer boundary formed therein is as Figure 3 shown by the dashed line 13 in the figure. This depletion layer reduces the reverse leakage current of the device and improves the blocking characteristics of the device. In addition, in the device structure of the present invention, a Schottky contact is formed between the first source region and the drift layer. This structure improves the third quadrant characteristics of the device, has a lower turn-on voltage compared to the body diode freewheeling of a conventional MOSFET, reduces the reverse recovery current of the device during the switching process, reduces the dynamic power consumption of the device, and has better switching characteristics.

[0025] At the same time, the present invention can significantly reduce the cell width of the power device. In a conventional MOSFET, the P-type region is arranged around the N+ source region. Due to the limitation of the channel length, the width of the P-type region is about half of the cell width; in the device of the present invention, due to the different conduction principles, the P-type region is not limited by the channel. Therefore, under the condition of the same JFET region width, a narrower cell size can be achieved, thereby having a lower on-resistance and reducing the static power consumption of the device. Secondly, the channel of the device of the present invention is a triple contact surface of the first source region, the N-type epitaxial layer, and the gate insulating layer, without the need for the channel of a conventional MOS, simplifying the manufacturing process of the device, reducing the device cost, and greatly increasing the number of cells per unit area.

[0026] 2. For the conventional vertical-channel tunneling power device of the present invention, a Schottky contact is formed between the first source region and the drift region, as Figure 4As shown, a space charge layer with a certain width will be formed on one side of the drift region. When the device is operating normally, the high voltage of the gate will attract electrons on the upper surface of the N-type epitaxial layer, forming a high-concentration N+ electron accumulation layer. However, due to the influence of the space charge region, the concentration of the electron accumulation layer near the first source region will decrease. In addition, there will be an electrostatic shielding effect when the tunneling device is operating normally: the high gate voltage of the tunneling device will generate an electric field perpendicular to the first source region, the second source region, and the surface of the epitaxial layer. However, since the potential of the source region is zero and the epitaxial layer has a high potential, the electric field lines at the edge of the epitaxial layer will be more attracted by the metal, which also leads to a decrease in the electron concentration near the tunneling point compared to the electron concentration at the center. At this time, the energy band at the interface between the first source region and the drift region is as Figure 6 shown by curve a in

[0027] The first source region in the device structure of the present invention has a structure with an inclined sidewall, as Figure 5 shown. The beveled terminal not only weakens the depletion effect at the tunneling point, but also significantly reduces the thickness of the depletion region compared to the conventional vertical-channel tunneling power device; at the same time, the inclined first source region is thinner at the same position compared to the vertical first source region, and its attraction effect on the electric field lines is weaker, thereby weakening the electrostatic shielding effect. As Figure 6 shown by curve b in Figure 7 the inclined first source region will cause the energy band on the semiconductor side to decrease compared to curve a, that is, the electron concentration at the tunneling point is increased, which will make the tunneling effect of the inclined sidewall stronger than that of the vertical sidewall. Therefore, the present invention has a larger operating current during forward conduction, and the device has better forward characteristics, as Figure 7 shown, the device with an inclined sidewall of the present invention has a stronger current-carrying ability under a high gate voltage compared to the conventional device with a vertical sidewall.

[0028] In summary, the present invention suppresses the depletion effect of the first source region on the drift region, weakens the electrostatic shielding ability of the vertical-channel tunneling device at the same time, increases the electron concentration at the tunneling point, increases the tunneling probability, and improves the current-carrying ability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a cell structure diagram of a conventional vertical-channel planar-gate tunneling silicon carbide power semiconductor device.

[0030] Figure 2 is a cell structure diagram of a planar-gate tunneling power semiconductor device with an inclined first source region according to the present invention.

[0031] Figure 3 is a schematic diagram of the depletion layer of the P-type region in the device when it is turned off according to the present invention.

[0032] Figure 4 is a schematic diagram of the electrostatic shielding effect of a conventional vertical-channel planar-gate tunneling power semiconductor device under a high gate voltage.

[0033] Figure 5 It is a schematic diagram showing the weakening of the electrostatic shielding effect of the first source region-tilted planar gate tunneling power semiconductor device of the present invention under high gate voltage.

[0034] Figure 6 It is a schematic energy band diagram of a conventional vertical channel device and the first source region-tilted planar gate tunneling power semiconductor device of the present invention in the flat band state.

[0035] Figure 7 It is a schematic comparison diagram of the transfer characteristic curves of the tilted sidewall device of the present invention and the conventional vertical sidewall device.

[0036] Figure 8 It is a schematic diagram of forming a P+ region on the upper surface of the epitaxial layer by using an ion implantation process in the manufacturing method of the present invention.

[0037] Figure 9 It is a schematic diagram of growing an oxide layer on the upper surface of the epitaxial layer and performing left trench etching by using an inclined ion beam in the manufacturing method of the present invention.

[0038] Figure 10 It is a schematic diagram of using the oxide layer to protect the left trench and performing right trench etching by using an inclined ion beam in the manufacturing method of the present invention.

[0039] Figure 11 It is a schematic diagram of depositing the first source region material in the trench in the manufacturing method of the present invention.

[0040] Figure 12 It is a schematic diagram of forming an inclined trench by using an etching process and forming the first source region by using a sputtering process or a CVD process in the manufacturing method of the present invention.

[0041] Figure 13 It is a schematic diagram of forming an oxide layer and a polysilicon gate electrode on the outer surface of the epitaxial layer by using a CVD process and forming a passivation layer in the manufacturing method of the present invention.

[0042] Figure 14 It is a schematic diagram of forming a drain metal and a second source region by using a sputtering process in the manufacturing method of the present invention;

[0043] Explanation of the marks in the figure: 1. N-type substrate; 2. N-type epitaxial layer; 3. P-type region; 4. First source region; 5. Second source region; 6. Passivation layer; 7. Gate electrode; 8. Gate oxide layer; 9. Drain metal; 10. First included angle; 11. Second included angle; 12. Oxide layer. Detailed implementation manners

[0044] In order to better understand the purpose, structure and function of the present invention, the following further describes in detail a tunneling power device and its manufacturing method of the present invention with reference to the accompanying drawings.

[0045] A tunneling power device, such as Figure 2 shown, comprising: an N-type substrate 1, a drain metal 9 is provided on one surface of the N-type substrate 1, an N-type epitaxial layer 2 is provided on the other surface of the N-type substrate 1, a P-type region 3 is provided on the N-type epitaxial layer 2, a first source region 4 is provided on the P-type region 3, a second source region 5 is connected above the first source region 4, a gate oxide layer 8 and a gate electrode 7 are provided on the N-type epitaxial layer 2, and a passivation layer 6 is provided on the gate electrode 7, characterized in that the side wall of the first source region 4 is inclined, forming a first angle 10 and a second angle 11 with the gate, wherein the first angle 10 is an acute angle, including but not limited to 20° to 30°, and the second angle 11 is an obtuse angle, including but not limited to 150° to 160°.

[0046] A manufacturing method of a tunneling power device

[0047] Step 1, as Figure 8 shown, take an N-type substrate 1, and form an N-type epitaxial layer 2 on one surface of the N-type substrate 1;

[0048] Step 2, use the ion implantation process to implant a P-type region 3 with a concentration of 5×10 17 cm -3 in the N-type epitaxial layer 2;

[0049] Step 3, as Figure 9 shown, first grow an oxide layer 12 on the surface of the epitaxial layer, then etch out the window of the left trench, and use the oxide layer to protect other parts of the device; use the reactive ion etching (RIE) process, tilt the ion beam at a certain angle for etching to form the left trench, and finally remove the oxide layer on the surface;

[0050] As Figure 10 shown, use the oxide layer 12 to protect the left trench, use the RIE process to tilt the ion beam for secondary etching to form the right trench, and finally remove the oxide layer on the surface;

[0051] Step 4, as Figure 11 shown, use the CVD process or the sputtering process to deposit source material on the trench of the first source region (4);

[0052] Step 5, then etch and remove the excess source material on the surface to form the first source region 4 as Figure 12 shown;

[0053] Step 6, as Figure 13 shown, use the CVD process to deposit an oxide layer on the N-type epitaxial layer 2;

[0054] Step 7, use the etching process to etch the excess oxide layer in Step 6 to form the gate oxide layer 8;

[0055] Step 8: Use the CVD process to form a gate electrode 7 above the gate oxide layer 8;

[0056] Step 9: Use the CVD process to form a passivation layer 6 above the gate electrode 7;

[0057] Step 10: As shown in Figure 14 , use the sputtering process to form a second source region 5 above the first source region 4 respectively, and fabricate a drain metal 9 on one surface of the N-type substrate 1.

[0058] The working principle and process of the present invention are as follows:

[0059] The cell structure of the tunneling power device includes an N-type substrate, an N-type epitaxial layer, a first source region with an inclined sidewall, a P-type region is provided below the first source region, a gate oxide layer and a gate electrode are provided above the epitaxial layer, a passivation layer is provided above the gate electrode, a second source region is provided on the upper surface of the first source region, and a drain metal is provided on the lower surface of the substrate. As the gate voltage increases, an electron accumulation layer will be formed on the surface of the semiconductor epitaxial layer, and the concentration of this electron accumulation layer will increase with the increase of the gate voltage. As the drain voltage increases, a band-to-band tunneling effect will occur between the first source region and the semiconductor epitaxial layer, and electrons will tunnel from the metal side to the semiconductor side, thereby forming a tunneling current and the device is turned on. When the device is turned off, the depletion layer formed by the P-type region below the first source region will shield the contact between the first source region and the semiconductor, improving the turn-off characteristics of the device. At the same time, when the device is in the third quadrant, a Schottky junction will be formed between the first source region and the semiconductor. This Schottky junction can reduce the turn-on voltage of the device in the third quadrant, reduce the reverse recovery current during the switching process of the device, and thus reduce the dynamic power consumption of the device.

[0060] A tunneling power device and its manufacturing method of the present invention have the following advantages:

[0061] 1. Compared with a conventional metal-semiconductor field effect transistor (MOSFET), the tunneling field effect transistor (TFET) of the present invention can achieve a lower subthreshold swing, reduce the leakage current at low voltages, reduce the power consumption during the switching process of the device, and improve the switching characteristics of the device. At the same time, when the device is turned off, the P-type region below the first source region will form a depletion layer with the N-type drift layer as shown in Figure 3 . The formed depletion layer boundary is as shown by the dashed line 13 in Figure 3 . This depletion layer reduces the reverse leakage current of the device and improves the blocking characteristics of the device. In addition, a Schottky contact is formed between the first source region and the drift layer in the device structure of the present invention. This structure improves the characteristics of the device in the third quadrant, has a lower turn-on voltage compared with the body diode freewheeling of a conventional MOSFET, reduces the reverse recovery current during the switching process of the device, reduces the dynamic power consumption of the device, and has better switching characteristics.

[0062] Meanwhile, the present invention can significantly reduce the cell width of power devices. In a conventional MOSFET, the P-type region is disposed around the N+ source region. Due to the limitation of the channel length, the width of the P-type region is about half of the cell width. In the device of the present invention, due to the different conduction principles, the P-type region is not limited by the channel. Therefore, in the case of the same JFET region width, a narrower cell size can be achieved, thereby having a lower on-resistance and reducing the static power consumption of the device. Secondly, the channel of the device of the present invention is a triple contact surface of the first source region, the N-type epitaxial layer and the gate oxide layer, and does not require the channel of a conventional MOS, which simplifies the manufacturing process of the device, reduces the device cost, and greatly increases the number of cells per unit area.

[0063] 2. For the conventional vertical-channel tunneling power device of the present invention, a Schottky contact is formed between the first source region and the drift region. As Figure 4 shown, a space charge layer with a certain width will be formed on one side of the drift region. When the device is operating normally, the high voltage of the gate will attract electrons on the upper surface of the N-type epitaxial layer to form a high-concentration N+ electron accumulation layer. However, due to the influence of the space charge region, the concentration of the electron accumulation layer near the first source region will be reduced. In addition, there will be an electrostatic shielding effect when the tunneling device is operating normally: the high gate voltage of the tunneling device will generate an electric field perpendicular to the surfaces of the first source region, the second source region and the epitaxial layer. However, since the potential of the source region is zero and the epitaxial layer is at a high potential, the electric field lines at the edge of the epitaxial layer will be more attracted by the metal, which also causes the electron concentration near the tunneling point to be lower than that at the center. At this time, the energy band at the interface of the first source region - drift region is as Figure 6 shown by curve a in

[0064] The first source region in the device structure of the present invention has a structure with an inclined sidewall. As Figure 5 shown, the beveled terminal not only weakens the depletion effect at the tunneling point, but also the thickness of the depletion region is significantly reduced compared with that of the conventional vertical-channel tunneling power device; at the same time, the inclined first source region is thinner than the vertical first source region at the same position, and its attraction effect on the electric field lines is weaker, thereby weakening the electrostatic shielding effect. As Figure 6 shown by curve b in Figure 7 the inclined first source region will reduce the energy band on the semiconductor side compared with curve a, that is, the electron concentration at the tunneling point is increased, which will make the tunneling effect of the inclined sidewall stronger than that of the vertical sidewall. Therefore, the present invention has a larger working current during forward conduction, and the device has better forward characteristics. As

[0065] In summary, the present invention suppresses the depletion effect of the first source region on the drift region, weakens the electrostatic shielding ability of the vertical channel tunneling device, increases the electron concentration at the tunneling point, increases the tunneling probability, and improves the current-carrying capacity of the device.

[0066] It can be understood that the present invention is described through some embodiments. Those skilled in the art know that various changes or equivalent replacements can be made to these features and embodiments without departing from the spirit and scope of the present invention. Additionally, under the teaching of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application belong to the scope protected by the present invention.

Claims

1. A tunneling power device, characterized in that, It includes: an N-type substrate (1), a drain metal (9) is provided on one surface of the N-type substrate (1), an N-type epitaxial layer (2) is provided on the other surface of the N-type substrate (1), a P-type region (3) is provided on the N-type epitaxial layer (2), a first source region (4) with an inclined sidewall is provided on the P-type region (3), a second source region (5) and a gate oxide layer (8) are connected to the first source region (4), a gate electrode (7) is provided above the gate oxide layer (8), a passivation layer (6) is provided above the gate electrode (7), and the passivation layer (6) separates the gate electrode (7) and the second source region (5).

2. The tunneling power device according to claim 1, wherein The sidewall of the first source region (4) is inclined, forming a first angle (10) and a second angle (11) with the gate electrode (7), where the first angle (10) is an acute angle and the second angle (11) is an obtuse angle.

3. The tunneling power device according to claim 1, characterized in that, The P-type region (3) withstands the breakdown voltage when the device is reverse-biased, and its typical doping concentration is 1×10 17 cm -3 .

4. The tunneling power device according to claim 1, wherein The material of the first source region (4) uses polysilicon, metal, graphene, molybdenum disulfide or other materials that can form the source region of a tunneling power semiconductor device.

5. The tunneling power device according to claim 1, characterized in that The doping concentration of the N-type epitaxial layer (2) typically ranges from 1×10 15 to 1×10 17 cm -3 . The material of the N-type epitaxial layer (2) is silicon carbide, gallium oxide, silicon, diamond, or other materials that can form the drift region of a tunneling power semiconductor device.

6. The tunneling power device according to claim 1, wherein The material of the N-type substrate (1) uses silicon carbide, gallium oxide, silicon, diamond or other materials that can form the substrate of a tunneling power semiconductor device.

7. The manufacturing method of a tunneling power device according to claim 1, characterized in that, It includes the following steps: Step 1: Take an N-type substrate (1) and form an N-type epitaxial layer (2) on one surface of the N-type substrate (1); Step 2: Use the ion implantation process to form a P-type region (3); Step 3: Use the etching process to etch the inclined angle of the N-type substrate (1) multiple times to form a trench of the first source region (4); Step 4: Use the sputtering process or the CVD process to fill the trench of the first source region (4) with the first source material; Step 5: Use the etching process to etch the excess first source material on the surface of the trench of the first source region (4) to form the first source region (4); Step 6: Use the CVD process to deposit an oxide layer on the N-type epitaxial layer (2); Step 7: Use the etching process to etch the excess oxide layer in Step 6 to form the gate oxide layer (8); Step 8: Use the CVD process to form a gate electrode (7) above the gate oxide layer (8); Step 9: Use the CVD process to form a passivation layer (6) above the gate electrode (7); Step 10: Use the sputtering process to form the second source region (5) and the drain metal (9).

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