A charge pump circuit structure with low power consumption, low starting current and high precision PWM modulation for AMOLED

Abstract

This invention proposes a charge pump circuit structure for AMOLED displays with low power consumption, low startup current, and high precision PWM modulation. It comprises five main modules: a charge pump module, a pulse width modulation module (PWM), a slope generation module, a logic module, and a driver module. Under light load, it can achieve low power consumption with a 0% duty cycle, offering advantages such as high efficiency, small area, and simple structure. It also features low startup current and high precision, with only one set of bus widths (FB), ensuring that FB equals VREF. Compared to digital adjustment methods, it achieves higher precision.

Description

Technical Field

[0001] The present invention relates to the technical field of charge pumps, and in particular to an AMOLED charge pump circuit structure with low power consumption, low starting current and high precision PWM modulation. Background Art

[0002] AMOLED stands for Active Matrix Organic Light Emitting Device display. Advantages of this display over traditional LCDs include low power consumption, manufacturing flexibility, and faster refresh rates. Compared to traditional LCDs, AMOLED displays do not have a backlight, so each pixel consists of a different color OLED that emits light independently. OLEDs emit light based on the current provided through a drive transistor, which is controlled by a programmed voltage.

[0003] The transistor itself is a nonlinear device and will show a certain resistance effect in the circuit. The resistance value of this resistor changes nonlinearly and varies according to the size of the current passing through. Studies have shown that when a MOSFET with lower on-resistance (RDSON) replaces a diode, the forward voltage drop is much lower than the forward voltage drop of a diode rectifier, so the conduction loss of the rectifier is greatly reduced.

[0004] Since the PWM modulator is used to generate adjustment signals to adjust the brightness of each OLED light-emitting unit, a charge pump circuit is required to provide a high voltage or negative voltage higher than the external power supply voltage when the load is heavy. However, according to the charge pump characteristics: when the charge pump duty cycle is from 0 to 50%, the output voltage is from low to high, and when it is from 50% to 100%, the output voltage is from high to low. Even if the charge pump reaches the maximum output energy, it cannot meet the load requirements, and the output energy of the charge pump will decrease. The above two reasons will lead to unstable performance and high power consumption of the PWM modulation circuit.

[0005] The present invention designs a charge pump circuit structure of low power consumption, low starting current and high precision PWM modulation for AMOLED, which can reduce vgh through logic control to offset the process of load lightening, thereby ensuring high precision. There is only one set of FB, which ensures that FB is equal to VREF, and can achieve higher precision than the digital adjustment method. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide an AMOLED charge pump circuit structure with low power consumption, low starting current and high precision PWM modulation, including: a charge pump module, a pulse width modulation module, a ramp generation module, a logic module and a driving module.

[0007] Among them, the charge pump module consists of five Pmos tubes, namely Pmos2, Pmos3, Pmos4, Pmos5 and Pmos6, plus a flying capacitor C2 and a capacitor C3. The positive end of the flying capacitor C2 is connected to the drain end of Pmos2, the drain end of Pmos6 and the source end of Pmos3, and the negative end of the flying capacitor C2 is connected to the drain end of Pmos5 and the source end of Pmos4; the driving signal PH1_s is connected to the gate end of Pmos2 and the gate end of Pmos5. The drive signal PH1 is connected to the gate terminal of Pmos6, the drive signal PH2 is connected to the gate terminal of Pmos3 and the gate terminal of Pmos4, the input signal AVDD is connected to the source terminal of Pmos2 and the source terminal of Pmos6, the input signal vicb is connected to the drain terminal of Pmos4, the ground signal gnd is connected to the source terminal of Pmos5, the output signal vgh is connected to the drain terminal of pmos3 and the positive terminal of the filter capacitor C3, and the negative terminal of the filter capacitor C3 is connected to the ground signal gnd.

[0008] Among them, the pulse width modulation module is composed of a voltage-dividing resistor R2, a resistor R3, an error amplifier EA and a comparator COMP. The output signal vgh of the charge pump module is connected to one end of the voltage-dividing resistor R2, the other end of the voltage-dividing resistor R2 is connected to the input signal FB and one end of the voltage-dividing resistor R3, the other end of the voltage-dividing resistor R3 is connected to the ground signal gnd, the positive input of the error amplifier EA is connected to the input signal vref that is independent of temperature, the negative input of the error amplifier EA is connected to the input signal FB, the output end VC of the error amplifier EA is connected to the negative input end of the comparator COMP, the positive input end of the comparator COMP is connected to the slope signal slope, and the output end of the comparator COMP is connected to the input end R of the RS trigger to provide an R signal for the RS trigger.

[0009] Among them, the slope signal slope is generated by the slope generating module, and the slope generating module is composed of an nmos tube nmos1, a Pmos tube Pmos1, a resistor R1 and a capacitor C1. The rising edge signal CK2 with a duty cycle of 0.1% is connected to the gate end of Pmos1 and the gate end of nmos1, the source end of Pmos1 is connected to the power signal, the drain end of Pmos1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the positive end of the capacitor C1 and the drain end of nmos1. The node signal at the connection is the slope signal slope with a duty cycle of 99.9% input to the positive end of the comparator COMP, the negative end of the capacitor C1 is grounded, and the source end of nmos1 is grounded.

[0010] The logic module is composed of a D flip-flop, a rising edge capture module, an RS flip-flop, an AND gate, an NOR gate and an inverter inv1. The clock input signal CLK is connected to the input clk terminal of the D flip-flop. The input terminal D and the output terminal QB of the D flip-flop are short-circuited together. The output terminal Q outputs a divided clock signal CK2_A with a duty cycle of 50%. The divided clock signal CK2_A is used as the input signal of the rising edge capture module. The rising edge capture module outputs the rising edge signal CK2 of the divided clock signal CK2_A. The input terminal of the RS trigger The S terminal is connected to the rising edge signal CK2, the RS triggered input terminal R is connected to the output terminal of the comparator COMP in the pulse width modulation module, the output terminal PH1_ii of the RS trigger is connected to the input terminal of the inverter inv1 and one input terminal of the AND gate, the other input terminal of the AND gate is connected to one input terminal of the NOR gate and connected to the divided clock signal CK2_A with a duty cycle of 50%, the other input terminal of the NOR gate is connected to the output terminal of the inverter inv1, the output signal of the AND gate is PH1_i_s, and the output signal of the NOR gate is PH1_i.

[0011] The driving module is composed of three driving devices and a group of staggered clock generators. The output terminal PH1_i_s signal of the AND gate is connected to the input terminal of the staggered clock generator to generate two groups of non-overlapping staggered clock signals. The two groups of signals are respectively connected to the input terminals of the first and second driving devices, and the output terminals of the first and second driving devices output driving signals PH1_s and PH2 respectively; the output terminal PH1_i signal of the NOR gate is connected to the input terminal of the third driving device, and the output terminal of the third driving device outputs the driving signal PH1. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 Shown is a circuit diagram of the present invention;

[0013] Figure 2 Shown is a working timing diagram of the PWM modulation of the present invention. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0015] See also Figure 1The present invention provides a charge pump circuit structure with low power consumption, low starting current and high precision PWM modulation for AMOLED, including: a charge pump module (chargepump), a pulse width modulation module (PWM), a slope generation module (slope_gen), a logic module (logic) and a driver module (driver).

[0016] Among them, the charge pump module consists of five Pmos tubes, namely Pmos2, Pmos3, Pmos4, Pmos5 and Pmos6, plus a flying capacitor C2 and a capacitor C3. The positive end of the flying capacitor C2 is connected to the drain end of Pmos2, the drain end of Pmos6 and the source end of Pmos3, and the negative end of the flying capacitor C2 is connected to the drain end of Pmos5 and the source end of Pmos4; the driving signal PH1_s is connected to the gate end of Pmos2 and the gate end of Pmos5. The drive signal PH1 is connected to the gate terminal of Pmos6, the drive signal PH2 is connected to the gate terminal of Pmos3 and the gate terminal of Pmos4, the input signal AVDD is connected to the source terminal of Pmos2 and the source terminal of Pmos6, the input signal vicb is connected to the drain terminal of Pmos4, the ground signal gnd is connected to the source terminal of Pmos5, the output signal vgh is connected to the drain terminal of pmos3 and the positive terminal of the filter capacitor C3, and the negative terminal of the filter capacitor C3 is connected to the ground signal gnd.

[0017] Among them, the pulse width modulation module is composed of a voltage-dividing resistor R2, a resistor R3, an error amplifier EA and a comparator COMP. The output signal vgh of the charge pump module is connected to one end of the voltage-dividing resistor R2, the other end of the voltage-dividing resistor R2 is connected to the input signal FB and one end of the voltage-dividing resistor R3, the other end of the voltage-dividing resistor R3 is connected to the ground signal gnd, the positive input of the error amplifier EA is connected to the input signal vref that is independent of temperature, the negative input of the error amplifier EA is connected to the input signal FB, the output end VC of the error amplifier EA is connected to the negative input end of the comparator COMP, the positive input end of the comparator COMP is connected to the slope signal slope, and the output end of the comparator COMP is connected to the input end R of the RS trigger to provide an R signal for the RS trigger.

[0018] Among them, the slope signal slope is generated by the slope generating module, and the slope generating module is composed of an nmos tube nmos1, a Pmos tube Pmos1, a resistor R1 and a capacitor C1. The rising edge signal CK2 with a duty cycle of 0.1% is connected to the gate end of Pmos1 and the gate end of nmos1, the source end of Pmos1 is connected to the power signal, the drain end of Pmos1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the positive end of the capacitor C1 and the drain end of nmos1. The node signal at the connection is the slope signal slope with a duty cycle of 99.9% input to the positive end of the comparator COMP, the negative end of the capacitor C1 is grounded, and the source end of nmos1 is grounded.

[0019] The logic module is composed of a D flip-flop, a rising edge capture module (posedge), an RS flip-flop, an AND gate, and an NOR gate, and an inverter inv1. The clock input signal CLK is connected to the input clk terminal of the D flip-flop. The input terminal D and the output terminal QB of the D flip-flop are short-circuited together. The output terminal Q outputs a divided clock signal CK2_A with a duty cycle of 50%. The divided clock signal CK2_A is used as the input signal of the rising edge capture module. The rising edge capture module outputs a rising edge signal CK2 (duty cycle of about 0.1%) of the divided clock signal CK2_A. ), the input terminal S of the RS trigger is connected to the rising edge signal CK2, the input terminal R of the RS trigger is connected to the output terminal of the comparator COMP in the pulse width modulation module, the output terminal PH1_ii of the RS trigger is connected to the input terminal of the inverter inv1 and one input terminal of the AND gate, the other input terminal of the AND gate is connected to one input terminal of the NOR gate and is connected to the divided clock signal CK2_A with a duty cycle of 50%, the other input terminal of the NOR gate is connected to the output terminal of the inverter inv1, the output signal of the AND gate is PH1_i_s, and the output signal of the NOR gate is PH1_i.

[0020] The driving module is composed of three driving devices (dr) and a group of staggered-phase clock generators (phase_gen). The output terminal PH1_i_s signal of the AND gate is connected to the input terminal of the staggered-phase clock generator to generate two groups of non-overlapping staggered-phase clock signals. The two groups of signals are respectively connected to the input terminals of the first and second driving devices, and the output terminals of the first and second driving devices output driving signals PH1_s and PH2 respectively; the output terminal PH1_i signal of the NOR gate is connected to the input terminal of the third driving device, and the output terminal of the third driving device outputs the driving signal PH1.

[0021] How it works:

[0022] 1. ClK generation: ring oscillator generation;

[0023] 2. CK2_A generates: the divided frequency signal of CLK, whose duty cycle is fixed at 50%;

[0024] 3. Generation of CK2: Capture the rising edge of CK2_A;

[0025] 4. Generation of FB: partial pressure of vgh, FB = K*vgh;

[0026] 5. Generation of VC: Output of the error amplifier, vc = K*(VREF-FB1);

[0027] 6. Generation of Slope signal: fixed slope signal with a duty cycle of 99.9% (controlled by CK2);

[0028] 7. Generation of R signal: VC is compared with the slope signal. When VC is higher, the R signal moves further back, away from CK2. When VC is lower, the R signal moves forward, closer to CK2.

[0029] 8. PH1_ii signal generation: its high level time is from the rising edge of CK2 signal to the rising edge of R signal, and its low level time is from the rising edge of R signal to the rising edge of CK2 signal. Since the rising edge of CK2 is fixed and VC controls the rising edge of R signal, the duty cycle of PH1_ii signal can be changed by VC (the maximum duty cycle is 99.9%).

[0030] 9. PH1_s (PH1) signal generation: PH1_s controls the small charging MOS tube, and PH1 controls the large charging MOS tube. Due to the characteristics of the charge pump, when the duty cycle is from 0 to 50%, the output voltage is from low to high; when it is from 50% to 100%, the output voltage is from high to low, and PH1 can only be turned on when PH1_s is turned on, otherwise there will be backflow, so when the PH1_ii signal duty cycle is from 0 to 50%, the PH1_s signal is adjusted from 100% to 50% and the PH1 signal is fixed at a duty cycle of 0% (Example 1: When the PH1_ii duty cycle is 0, the PH1_s duty cycle is 100% and the PH1 signal is fixed at a duty cycle of 0%; Example 2: When the PH1_ii duty cycle is 25%, the PH1_s duty cycle is 25%. Example 3: when PH1_ii duty cycle is 50%, PH1_s duty cycle is 50% and PH1 signal duty cycle is fixed to 0%), when ph1_ii is between 50% and 99.9%, PH1_s signal remains at 50%, PH1 signal is adjusted from 0 to 49.9% (Example 4: when PH1_ii duty cycle is 60%, PH1_s duty cycle is 50%, PH1 signal duty cycle is 10%; Example 5: when PH1_ii duty cycle is 99.9%, PH1_s duty cycle is 50%, PH1 signal duty cycle is 49.9%), which ensures that ph1_ii changes linearly with vgh within 0 to 99.9%. At startup, only the small charging MOS tube is turned on to reduce the starting current. When stable, the duty cycle of the large and small tubes is automatically determined according to the load conditions to achieve the effect of low power consumption. The automated process: when the load becomes heavier, FB decreases, VC output is high, PH1_ii duty cycle increases, causing VGH to increase, achieving an automatic adjustment process;

[0031] 10. PH2 signal generation: opposite to PH1_s.

[0032] Feedback control working process:

[0033] PH1_s controls the small charging MOS tube, and PH1 controls the large charging MOS tube. Due to the characteristics of the charge pump, when the duty cycle is from 0 to 50%, the output voltage is from low to high; when it is from 50% to 100%, the output voltage is from high to low, and PH1 can only be turned on when PH1_s is turned on, otherwise there will be backflow. Therefore, when the duty cycle of the PH1_ii signal is between 0 and 50%, the PH1_s signal is adjusted from 100% to 50% and the PH1 signal is fixed at a duty cycle of 0% (Example 1: When the PH1_ii duty cycle is 0, the PH1_s duty cycle is 100% and the PH1 signal is fixed at a duty cycle of 0%; Example 2: When the PH1_ii duty cycle is 25%, the PH1_s duty cycle is 75% and PH 1 signal has a fixed duty cycle of 0%; Example 3: when the duty cycle of PH1_ii is 50%, the duty cycle of PH1_s is 50% and the duty cycle of PH1 signal is fixed to 0%), when ph1_ii is between 50% and 99.9%, the PH1_s signal remains at 50%, and the PH1 signal is adjusted from 0 to 49.9% (Example 4: when the duty cycle of PH1_ii is 60%, the duty cycle of PH1_s is 50%, and the duty cycle of PH1 signal is 10%; Example 5: when the duty cycle of PH1_ii is 99.9%, the duty cycle of PH1_s is 50%, and the duty cycle of PH1 signal is 49.9%), which ensures that ph1_ii changes linearly with vgh within 0 to 99.9%. At startup, only the small charging MOS tube is turned on to reduce the starting current. When stable, the duty cycle of the large and small tubes is automatically determined according to the load conditions to achieve the effect of low power consumption. The automated process: when the load becomes heavier, FB decreases, VC output is high, PH1_ii duty cycle increases, causing VGH to increase, achieving an automatic regulation process.

[0034] See also Figure 2 The ring oscillator always generates a fixed frequency clock CIK, which is divided by two by the D flip-flop to generate a clock signal CK2_A with a fixed duty cycle of 50%. The rising edge extraction module extracts the rising edge clock signal CK2 of CK2_A as the S end of the RS flip-flop. The CK2 signal also controls the slope signal generation module, that is, the slope signal can be a low signal for 0.1% of the time and a triangular wave signal for 99.9% of the time. When overloaded, the duty cycle of PH1_ii is higher than 50%. At this time, PH1_s maintains a 50% duty cycle, and ph1 maintains a ph1_ii duty cycle of -50%. When the load gradually becomes lighter, vgh increases, vc decreases, and the duty cycle of PH1_ii decreases, that is, the duty cycle of ph1 gradually decreases, and PH1_s maintains a 50% duty cycle. As the load gradually decreases again, the duty cycle of PH1_ii is lower than 50%, that is, the duty cycle of ph1 decreases to 0, and ph1_s gradually increases from 50%, so that vgh decreases to offset the process of load lightening. This ensures that vgh remains unchanged.

[0035] The present invention provides an AMOLED low-power, low-startup current, high-precision PWM modulation charge pump circuit structure, which has the following advantages:

[0036] 1. Low power consumption: When lightly loaded, low power consumption can be achieved through 0% duty cycle;

[0037] 2. Simple structure: The error amplifier and comparator are reused, the structure is simple, the error amplifier is saved, and the comparator has lower power consumption;

[0038] 3. High efficiency and small area: Compared with the fixed duty cycle, changing rdson reduces one rdson regulating tube, thus reducing the area and avoiding energy loss on the rdson tube, thus improving efficiency;

[0039] 4. Low starting current;

[0040] 5. High precision, there is only one set of FB, which ensures that FB is equal to VREF. Compared with the digital adjustment method, higher precision can be achieved.

[0041] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0042] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is limited by the appended claims and their equivalents.

Claims

1. A charge pump circuit structure with low power consumption, low starting current and high precision PWM modulation for AMOLED, characterized in that: include: Charge pump module, pulse width modulation module, ramp generation module, logic module and drive module; The charge pump module is composed of five Pmos tubes, namely Pmos2, Pmos3, Pmos4, Pmos5 and Pmos6, plus a flying capacitor C2 and a capacitor C3, the positive end of the flying capacitor C2 is connected to the drain end of the Pmos2, the drain end of the Pmos6 and the source end of the Pmos3, the negative end of the flying capacitor C2 is connected to the drain end of the Pmos5 and the source end of the Pmos4; the driving signal PH1_s is connected to the gate end of the Pmos2 and the gate end of the Pmos5 e terminal, the driving signal PH1 is connected to the gate terminal of Pmos6, the driving signal PH2 is connected to the gate terminal of Pmos3 and the gate terminal of Pmos4, the input signal AVDD is connected to the source terminal of Pmos2 and the source terminal of Pmos6, the input signal vicb is connected to the drain terminal of Pmos4, the ground signal gnd is connected to the source terminal of Pmos5, the output signal vgh is connected to the drain terminal of Pmos3 and the positive terminal of the filter capacitor C3, and the negative terminal of the filter capacitor C3 is connected to the ground signal gnd; The pulse width modulation module is composed of a voltage-dividing resistor R2, a resistor R3, an error amplifier EA and a comparator COMP. The output signal vgh of the charge pump module is connected to one end of the voltage-dividing resistor R2, the other end of the voltage-dividing resistor R2 is connected to the input signal FB and one end of the voltage-dividing resistor R3, the other end of the voltage-dividing resistor R3 is connected to the ground signal gnd, the positive input of the error amplifier EA is connected to the input signal vref that is independent of temperature, the negative input of the error amplifier EA is connected to the input signal FB, the output end VC of the error amplifier EA is connected to the negative input end of the comparator COMP, the positive input end of the comparator COMP is connected to the slope signal slope, and the output end of the comparator COMP is connected to the input end R of the RS trigger to provide an R signal for the RS trigger; The slope signal slope is generated by the slope generating module, which is composed of an nmos tube nmos1, a Pmos tube Pmos1, a resistor R1 and a capacitor C1. The rising edge signal CK2 with a duty cycle of 0.1% is connected to the gate end of the Pmos1 and the gate end of the nmos1. The source end of the Pmos1 is connected to the power signal. The drain end of the Pmos1 is connected to one end of the resistor R1. The other end of the resistor R1 is connected to the positive end of the capacitor C1 and the drain end of the nmos1. The node signal at the connection is the slope signal slope with a duty cycle of 99.9% input to the positive end of the comparator COMP. The negative end of the capacitor C1 is grounded, and the source end of the nmos1 is grounded. The logic module is composed of a D flip-flop, a rising edge capture module, an RS flip-flop, an AND gate, and an NOR gate, and an inverter inv1. The clock input signal CLK is connected to the input clk terminal of the D flip-flop. The input terminal D and the output terminal QB of the D flip-flop are short-circuited together. The output terminal Q outputs a divided clock signal CK2_A with a duty cycle of 50%. The divided clock signal CK2_A is used as the input signal of the rising edge capture module. The rising edge capture module outputs the rising edge signal CK2 of the divided clock signal CK2_A. The input terminal S of the RS trigger is connected to the upper Rising edge signal CK2, the input terminal R of the RS trigger is connected to the output terminal of the comparator COMP in the pulse width modulation module, the output terminal PH1_ii of the RS trigger is connected to the input terminal of the inverter inv1 and one input terminal of the AND gate, the other input terminal of the AND gate is connected to an input terminal of the NOR gate and is connected to the divided clock signal CK2_A with a duty cycle of 50%, the other input terminal of the NOR gate is connected to the output terminal of the inverter inv1, the output signal of the AND gate is PH1_i_s, and the output signal of the NOR gate is PH1_i.

2. According to claim 1, a charge pump circuit structure of low power consumption, low starting current and high precision PWM modulation for AMOLED, characterized in that: The driving module is composed of three driving devices and a group of staggered clock generators. The output terminal PH1_i_s signal of the AND gate is connected to the input terminal of the staggered clock generator to generate two groups of non-overlapping staggered clock signals. The two groups of signals are respectively connected to the input terminals of the first and second driving devices, and the output terminals of the first and second driving devices output driving signals PH1_s and PH2 respectively; the output terminal PH1_i signal of the NOR gate is connected to the input terminal of the third driving device, and the output terminal of the third driving device outputs the driving signal PH1.

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