A bidirectional TVS device and its preparation method

Abstract

Disclosed are a bidirectional TVS device and a preparation method thereof. The device comprises: a substrate of a first doping type; an epitaxial layer of a second doping type located on the substrate, wherein the second doping type is opposite to the first doping type; an isolation structure extending from the surface of the epitaxial layer into the substrate, defining a first region, a second region, a third region, a fourth region and a fifth region isolated from each other in the epitaxial layer; wherein a first diode, a second diode, a third diode and a fourth diode are respectively formed in the first region, the second region, the third region and the fourth region, and a triode is formed in the fifth region; and a metal interconnection structure connecting the cathodes of the first diode and the third diode to the first potential of the triode, and connecting the anodes of the second diode and the fourth diode to the second potential of the triode.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a bidirectional TVS device and a preparation method thereof. Background Art

[0002] A transient voltage suppressor (TVS) device or electro-static discharge (ESD) protection device is a voltage clamping overvoltage protection device used to protect electronic equipment from damage caused by transient high-energy impacts. It can convert the high impedance between its two poles into low impedance at a speed of picoseconds, absorbing surge power of up to several kilowatts, thereby avoiding damage to electronic equipment.

[0003] Traditional TVS devices are basically voltage regulator type structures with relatively simple manufacturing processes. Generally, PN junctions are directly formed on P+ substrate / N+ substrate through heterogeneous doping. Traditional TVS devices are mainly used in power, switch, and audio ports in consumer electronic products (such as mobile phones, computers, digital cameras, etc.). This is because such ports are slow and the capacitance requirements of TVS devices are not high, generally above 20pF. However, for the protection of high-speed communication ports (such as USB3.0 ports, DisplayPort ports, SATA3.0 ports, and HDMI2.0 ports), traditional TVS devices are not suitable. This is because high-speed communication has extremely high data transmission rates. For example, the data transmission rate of industrial automation networks is greater than 480M / s, and some high-speed data transmission rates reach more than 10G / s. This requires that the capacitance of the TVS device for line protection is extremely low, not greater than 1.0pF, otherwise it will cause data transmission to be lost and the circuit cannot work properly. At the same time, the ESD capability requirements are extremely high and cannot be lower than 12kV.

[0004] Another type of TVS device uses a silicon controlled rectifier (SCR) structure. Although the SCR structure has the advantages of high current discharge efficiency, strong anti-static ability, low static leakage, and small parasitic capacitance, its trigger voltage is high, the opening speed is slow, and the holding voltage (VH) is only 1 to 2V, which is lower than the operating voltage of the protected device and can easily cause latching problems, making it unsuitable for use in power protection circuits. The operating voltage of the power protection circuit is generally around 5V, so SCR devices with large hysteresis cannot be used. Therefore, it is necessary to develop a new type of ultra-low capacitance TVS device that not only meets the requirements of low parasitic capacitance of high-speed communication ports, but also meets the requirements of low clamping voltage and peak current I PP High, high ESD capability and holding voltage (VH) greater than the operating voltage requirements. Summary of the invention

[0005] In view of the above problems, the object of the present invention is to provide a bidirectional TVS device and a method for preparing the same, which has low clamping voltage, I PP The advantages are high, high ESD capability and a sustaining voltage greater than the operating voltage.

[0006] A first aspect of the present invention provides a bidirectional TVS device, comprising:

[0007] a substrate of a first doping type;

[0008] an epitaxial layer of a second doping type located on the substrate, wherein the second doping type is opposite to the first doping type;

[0009] an isolation structure extending from the surface of the epitaxial layer into the substrate, defining a first region, a second region, a third region, a fourth region and a fifth region isolated from each other in the epitaxial layer; wherein a first diode, a second diode, a third diode and a fourth diode are formed in the first region, the second region, the third region and the fourth region respectively, and a triode is formed in the fifth region; and

[0010] The metal interconnection structure connects the cathodes of the first diode and the third diode to the first potential of the triode, and connects the anodes of the second diode and the fourth diode to the second potential of the triode.

[0011] Preferably, the anode of the first diode and the cathode of the second diode are connected to the first channel; the cathode of the first diode, the cathode of the third diode and the collector of the transistor are connected to the power supply terminal; the anode of the second diode, the emitter of the transistor and the anode of the fourth diode are grounded; the anode of the third diode and the cathode of the fourth diode are connected to the second channel.

[0012] Preferably, it also includes:

[0013] a well region, located in the epitaxial layer of the fifth region, the well region having a first doping type;

[0014] A first doping region of a first doping type is located in the epitaxial layers of the first region, the second region, the third region, and the fourth region; and

[0015] A second doping region of a second doping type is located in the epitaxial layer of the first region, the second region, the third region, the fourth region, and in the well region of the fifth region;

[0016] In the first region, the second region, the third region and the fourth region, the first doped region, the second doped region and the epitaxial layer constitute a first diode, a second diode, a third diode and a fourth diode respectively; in the fifth region, the second doped region and the well region constitute a triode.

[0017] Preferably, the first doped region of the first doping type is also located in the well region of the fifth region, and the first doped region in the fifth region is short-circuited with the second doped region forming the transistor emitter to form a transistor with a short-circuited base and emitter in the fifth region.

[0018] Preferably, the first region, the second region, the third region and the fourth region further include a well region, the well region is located in the epitaxial layer, the first doped region is located in the well region, and the second doped region is located outside the well region.

[0019] Preferably, an isolation layer is included, and the isolation layer is located between the substrate and the epitaxial layer. The isolation structure penetrates the epitaxial layer and the isolation layer from the surface of the epitaxial layer and extends into the substrate.

[0020] Preferably, the isolation layer is an intrinsic semiconductor layer or an insulating layer.

[0021] Preferably, the first doped region comprises:

[0022] implanted region of a first doping type; and / or

[0023] a deep trench filled with a semiconductor material of a first doping type;

[0024] The second doped region comprises:

[0025] implanted region of a second doping type; and / or

[0026] A deep trench is filled with a semiconductor material of a second doping type.

[0027] Preferably, the width of the first doping region and the second doping region is 1.5um-20um, and the junction depth is 0.3um-2um.

[0028] Preferably, the width of the top of the first doping region and the second doping region is 1 um to 3 um, and the depth is 2 um to 6 um.

[0029] Preferably, in the first region, the second region, the third region and the fourth region, the first doping regions and the second doping regions are arranged alternately.

[0030] Preferably, in the fifth region, the top-view shape of the first doping region and the second doping region is a strip, a rectangle, a U-shape, a ring shape, or a combination thereof.

[0031] Preferably, the first region, the second region, the third region and the fourth region are arranged in a matrix, and the fifth region is located in a central region of the matrix.

[0032] Preferably, the area and structure of the third diode are completely identical to those of the second diode, and the area and structure of the fourth diode are completely identical to those of the first and second diodes.

[0033] A second aspect of the present invention provides a method for preparing a bidirectional TVS device, comprising:

[0034] forming an epitaxial layer of a second doping type on a substrate of the first doping type, wherein the second doping type is opposite to the first doping type;

[0035] forming an isolation structure, the isolation structure extending from the surface of the epitaxial layer into the substrate, defining a first region, a second region, a third region, a fourth region and a fifth region isolated from each other in the epitaxial layer; wherein a first diode, a second diode, a third diode and a fourth diode are formed in the first region, the second region, the third region and the fourth region respectively, and a triode is formed in the fifth region; and

[0036] A metal interconnection structure is formed, wherein the metal interconnection structure connects the cathodes of the first diode and the third diode to the first potential of the triode, and connects the anodes of the second diode and the fourth diode to the second potential of the triode.

[0037] Preferably, the anode of the first diode and the cathode of the second diode are connected to the first channel; the cathode of the first diode, the cathode of the third diode and the collector of the transistor are connected to the power supply terminal; the anode of the second diode, the emitter of the transistor and the anode of the fourth diode are grounded; the anode of the third diode and the cathode of the fourth diode are connected to the second channel.

[0038] Preferably, before or after forming the isolation structure, the method further comprises:

[0039] forming a well region in the epitaxial layer of the fifth region, wherein the well region has a first doping type;

[0040] forming a first doping region of a first doping type in the epitaxial layers of the first region, the second region, the third region, and the fourth region; and

[0041] forming a second doping region of a second doping type in the epitaxial layers of the first region, the second region, the third region, and the fourth region and in the well region of the fifth region;

[0042] In the first region, the second region, the third region and the fourth region, the first doped region, the second doped region and the epitaxial layer constitute a first diode, a second diode, a third diode and a fourth diode respectively; in the fifth region, the second doped region and the well region constitute a triode.

[0043] Preferably, before or after forming the isolation structure, it also includes: forming a first doping region of the first doping type in the fifth region, the first doping region in the fifth region is short-circuited with the second doping region forming the emitter of the transistor, so as to form a transistor with the base and the emitter short-circuited in the fifth region.

[0044] Preferably, before or after forming the isolation structure, it also includes: forming a well region in the epitaxial layer in the first region, the second region, the third region, and the fourth region, the first doped region is located in the well region, and the second doped region is located outside the well region.

[0045] Preferably, before forming the epitaxial layer, the method further comprises: forming an isolation layer on the substrate, wherein the isolation structure penetrates the epitaxial layer and the isolation layer from the surface of the epitaxial layer and extends into the substrate.

[0046] Preferably, the isolation layer is an intrinsic semiconductor layer or an insulating layer.

[0047] Preferably, the first doped region comprises:

[0048] An implanted region of a first doping type; and / or

[0049] a deep trench filled with a semiconductor material of a first doping type;

[0050] The second doped region comprises:

[0051] implanted region of a second doping type; and / or

[0052] A deep trench is filled with a semiconductor material of a second doping type.

[0053] Preferably, the implantation region of the first doping type or the implantation region of the second doping type is formed by ion implantation.

[0054] Preferably, the method of forming a deep trench filled with a semiconductor material of a first doping type or a semiconductor material of a second doping type comprises:

[0055] forming a deep trench extending from a surface of the epitaxial layer to an interior of the epitaxial layer; and

[0056] The deep trench is filled with a semiconductor material of a first doping type or a semiconductor material of a second doping type to form a first doping region or a second doping region.

[0057] Preferably, the semiconductor material of the first doping type is boron-doped polysilicon with a doping concentration of 1E17 to 1E20 cm-3; the semiconductor material of the second doping type is phosphorus-doped polysilicon with a doping concentration of 1E17 to 1E20 cm-3.

[0058] Preferably, the width of the first doping region and the second doping region is 1.5um-20um, and the junction depth is 0.3um-2um.

[0059] Preferably, the width of the top of the first doping region and the second doping region is 1 um to 3 um, and the depth is 2 um to 6 um.

[0060] Preferably, in the first region, the second region, the third region and the fourth region, the first doping regions and the second doping regions are arranged alternately.

[0061] Preferably, in the fifth region, the top-view shape of the first doping region and the second doping region is a strip, a rectangle, a U-shape, a ring shape, or a combination thereof.

[0062] Preferably, the first region, the second region, the third region and the fourth region are arranged in a matrix, and the fifth region is located in a central region of the matrix.

[0063] Preferably, the area and structure of the third diode are completely identical to those of the second diode, and the area and structure of the fourth diode are completely identical to those of the first and second diodes.

[0064] The bidirectional TVS device and preparation method thereof provided by the present invention integrate a diode and a voltage-stabilizing transistor into a bidirectional TVS device, integrating the advantages of the small capacitance of the diode and the Snapback effect of the short circuit between the base and the emitter of the transistor, taking into account the advantages of both the diode and the transistor, and having the characteristics of small capacitance, low residual voltage and appropriate voltage.

[0065] In a preferred embodiment, a triode with a base and an emitter short-circuited constitutes a voltage regulator part of the bidirectional TVS device, and compared with the bidirectional TVS device in the prior art, it has a snapback characteristic.

[0066] Optionally, a transistor constitutes the voltage regulator part of the bidirectional TVS device, the base of the transistor is open, holes cannot flow out through the base, and the PN junction formed by the base and emitter of the transistor has a small current when turned on, generally at the uA level.

[0067] Furthermore, by adjusting the spacing between the second doped regions in the fifth region (the spacing between the collector and emitter of the transistor, i.e., the base width of the transistor) and the implantation doses of the second doped regions and the well region, the breakdown voltage and the negative resistance can be adjusted, and ultimately the holding voltage of the bidirectional TVS device is made greater than the operating voltage, which will not cause latch-up problems, and can also make the clamping voltage lower under high current conditions, resulting in lower power consumption.

[0068] Furthermore, since the first diode is completely identical to the third diode, the second diode is completely identical to the diode, and they share a transistor, the forward and reverse breakdown voltages of the bidirectional TVS device are equal, and the forward and reverse breakdown voltages have good consistency.

[0069] In a preferred embodiment, the isolation layer is an intrinsic semiconductor layer. By arranging an intrinsic semiconductor layer between the substrate and the epitaxial layer, the substrate, the isolation layer and the epitaxial layer form a longitudinal PIN junction. Compared with the PN junction, the PIN junction can significantly reduce the carrier concentration and thus reduce the capacitance.

[0070] In a preferred embodiment, the isolation layer is an insulating layer, so that the TVS device forms a silicon on insulator (SOI) structure, and devices in different regions are separated by an isolation layer with good insulation performance, which can eliminate the opening of bulk silicon parasitic devices, reduce the parasitic capacitance and leakage current between the substrate and the epitaxial layer, and has the advantages of high integration and good radiation resistance.

[0071] In a preferred embodiment, a deep trench filling process is used to form the first doped region and / or the second doped region in the transistor and / or the diode, and the electric field is introduced from the device surface into the interior of the epitaxial layer, thereby improving the stability and surge resistance of the device.

[0072] Furthermore, the first doped region and / or the second doped region of the deep trench structure enables the transistor and / or the diode to have a larger effective area, which can significantly improve the surge resistance capability and reduce the clamping voltage.

[0073] Furthermore, the deep trench structure in the transistor and / or diode has a small lateral diffusion, and more minimum repeating units can be made under the same area, thereby increasing the current density per unit area and further improving the surge and ESD resistance of the device.

[0074] Furthermore, the ion implantation process is limited by the capacity of the implantation machine, and the maximum ion implantation dose can only be 1.0E16 cm -2The first doping region and / or the second doping region in the triode and / or the diode are formed by a deep trench filling process, which can make the doping concentration of the first doping region and the second doping region higher, improve the emission efficiency of the triode and reduce the contact resistance, thereby improving I PP capability and lower clamping voltage.

[0075] In a preferred embodiment, in the fifth region, the first doped region and the second doped region are arranged in a "U-shape", and the second doped region arranged in the "U-shape" constitutes a transistor. The current can flow through the collector of the inner circle into the emitter of the outer circle, thereby increasing the circumference-to-area ratio and improving the emission efficiency and surge resistance of the transistor current.

[0076] In a preferred embodiment, in the fifth region, the first doped region and the second doped region are arranged in a "circular ring shape", and the second doped region arranged in the "circular ring shape" constitutes a triode. The current can flow into the emitter of the outer circle through the surrounding areas of the collector of the inner circle, thereby increasing the circumference-to-area ratio, improving the emission efficiency and surge resistance of the triode current, and making the electric field distribution smoother. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0078] Figure 1 The electrical IV curves of the bidirectional TVS device in both the forward and reverse directions are shown;

[0079] FIG2 shows a schematic diagram of a circuit connection structure of a first bidirectional TVS device in the prior art;

[0080] Figure 3 A schematic diagram of a circuit connection structure of a second bidirectional TVS device in the prior art is shown;

[0081] Figure 4 A schematic diagram of a circuit connection structure of a third bidirectional TVS device in the prior art is shown;

[0082] Figure 5 A cross-sectional view of a bidirectional TVS device according to a first embodiment of the present invention is shown;

[0083] Figure 6 A top view showing the arrangement of the well region, the first doping region and the second doping region in the bidirectional TVS device of the first embodiment of the present invention is shown;

[0084] Figure 7 A schematic diagram showing the circuit connection structure of a bidirectional TVS device according to a first embodiment of the present invention is shown;

[0085] Figures 8a to 8cA schematic diagram showing the current flow direction when a high potential is applied to the first channel I / O1 and a low potential is applied to the second channel I / O2 in the bidirectional TVS device of the first embodiment of the present invention;

[0086] Figures 9a to 9i The cross-sectional views at various stages of the preparation process of the bidirectional TVS device according to the first embodiment of the present invention are shown;

[0087] Fig.10 A cross-sectional view of a bidirectional TVS device according to a second embodiment of the present invention is shown;

[0088] Fig.11 A cross-sectional view of a bidirectional TVS device according to a third embodiment of the present invention is shown;

[0089] Fig.12 A cross-sectional view of a bidirectional TVS device according to a fourth embodiment of the present invention is shown;

[0090] Figures 13a to 13k shows cross-sectional views of various stages in the process of preparing a bidirectional TVS device according to a fourth embodiment of the present invention;

[0091] Fig.14 A cross-sectional view of a bidirectional TVS device according to a fifth embodiment of the present invention is shown;

[0092] Figure 15a to Figure 15h shows cross-sectional views of various stages in the process of preparing a bidirectional TVS device according to a fifth embodiment of the present invention;

[0093] Fig.16 A cross-sectional view of a bidirectional TVS device according to a sixth embodiment of the present invention is shown;

[0094] Fig.17 FIG. 4 is a top view of a bidirectional TVS device according to a seventh embodiment of the present invention;

[0095] Fig.18 FIG. 4 is a top view of a bidirectional TVS device according to an eighth embodiment of the present invention;

[0096] Fig.19 FIG. 4 is a top view of a bidirectional TVS device according to a ninth embodiment of the present invention;

[0097] Figures 20a to 20c The diagram shows the current flow direction when a high potential is applied to the first channel I / O1 and a low potential is applied to the second channel I / O2 in the bidirectional TVS device according to the tenth embodiment of the present invention. DETAILED DESCRIPTION

[0098] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0099] The present invention may be embodied in various forms, some examples of which will be described below.

[0100] Compared with unidirectional ultra-low capacitance TVS devices, bidirectional TVS devices are basically symmetrical in both the forward and reverse directions, so in practical applications, they can protect both directions of the circuit at the same time, so their application range is wider. The structure of the prior art bidirectional TVS devices usually does not have the Snapback effect (negative resistance effect). Figure 1 The electrical IV curves of the bidirectional TVS device in both the forward and reverse directions are shown. Figure 1 In FIG. 1 , curve A shows the IV curve of a device without the Snapback characteristic, and curve B shows the IV curve of a device with the Snapback characteristic. PP Under this condition, the clamping voltage V CB The clamping voltage V is significantly lower than that of devices without snapback characteristics. CA .

[0101] There are roughly three types of bidirectional TVS devices in the prior art. FIG. 2 shows a schematic diagram of the circuit connection structure of the first bidirectional TVS device in the prior art. Figure 2a As shown in FIG. 2 , the bidirectional TVS device connects two unidirectional ultra-low capacitance TVS devices in series, and each unidirectional ultra-low capacitance TVS device connects a low capacitance first diode D1 and a traditional voltage-stabilizing TVS diode Z1 in series, and then connects another low capacitance second diode D2 in parallel. Alternatively, as shown in FIG. 2 b , the bidirectional TVS device connects low-integration unidirectional low capacitance diodes in series.

[0102] Although the capacitance of the system line of the first type of bidirectional TVS device is much lower than that of a single TVS device at the same voltage, its forward and reverse characteristics are still equivalent to that of an ordinary diode. The first type of bidirectional TVS device has the following disadvantages: two groups of chips are connected in series, which is costly; it is difficult to package two groups of chips in a small package; it does not have the Snapback effect (negative resistance effect), and the clamping voltage is high.

[0103] Figure 3 FIG. 4 shows a schematic diagram of a circuit connection structure of a second bidirectional TVS device in the prior art; Figure 3 As shown, the bidirectional TVS device connects a group of low-capacitance first diode D1 and voltage-stabilizing TVS diode Z1 in series with another group of low-capacitance second diode D2 and voltage-stabilizing TVS diode Z2 in reverse parallel.

[0104] The second type of bidirectional TVS device has a high degree of integration and low capacitance, which meets the general low-capacitance application scenarios. However, the bidirectional TVS device is composed of a voltage-stabilizing TVS diode Z1 and a voltage-stabilizing TVS diode Z2 in the forward and reverse directions respectively. This will make it difficult to achieve consistent forward and reverse withstand voltages, which is not suitable for application scenarios with high symmetry requirements. At the same time, this structure does not have a snapback effect, and the clamping voltage is relatively high.

[0105] Figure 4 FIG. 4 shows a schematic diagram of a circuit connection structure of a third bidirectional TVS device in the prior art; Figure 4 As shown, the bidirectional TVS device includes a low-capacitance first diode D1, a low-capacitance second diode D2, a low-capacitance third diode D3, a low-capacitance fourth diode D4 and a Zener diode Z1, wherein the first diode D1 and the second diode D2 are connected in parallel, the third diode D3 and the fourth diode D4 are connected in parallel, and the first diode D1 and the second diode D2 connected in parallel and the third diode D3 and the fourth diode D4 connected in parallel are respectively connected to the Zener diode Z1.

[0106] The third type of bidirectional TVS device uses the same voltage regulator Z1 for both the forward and reverse channels, and does not have the problem of poor voltage symmetry. However, the third type of bidirectional TVS device does not have the Snapback effect, and the clamping voltage is relatively high. At the same time, the use of a buried layer with a high doping concentration will lead to a large parasitic capacitance.

[0107] Figure 5 FIG. 4 shows a cross-sectional view of a bidirectional TVS device according to a first embodiment of the present invention; Figure 5 As shown, the bidirectional TVS device includes a substrate 101, an isolation layer 102, an epitaxial layer 103, an isolation structure 105, a plurality of first doped regions 107, a plurality of second doped regions 108, a dielectric layer 109 and a metal interconnection structure.

[0108] The isolation layer 102 is located on the substrate 101, and the epitaxial layer 103 is located on the isolation layer 102, wherein the substrate 101 has a first doping type, the isolation layer 102 is an intrinsic semiconductor layer, and the epitaxial layer 103 has a second doping type opposite to the first doping type. In this embodiment, the substrate 101 is, for example, a P-substrate, and the epitaxial layer 103 is, for example, an N-epitaxial layer.

[0109] The isolation structure 105 extends from the surface of the epitaxial layer 103 toward the substrate 101, and the isolation structure 105 penetrates the epitaxial layer 103 and the isolation layer 102, and extends to the inside of the substrate 101. The isolation structure 105 isolates the epitaxial layer 103 to form multiple regions. In this embodiment, the multiple regions are respectively a triode region and four diode regions. Specifically, the epitaxial layer 103 is isolated by the isolation structure 105 to form a first region 1031, a second region 1032, a third region 1033, a fourth region 1034 and a fifth region 1035, wherein the first region 1031, the second region 1032, the third region 1033 and the fourth region 1034 are diode regions, and the fifth region 1035 is a triode region.

[0110] In this embodiment, the first area 1031 , the second area 1032 , the third area 1033 and the fourth area 1034 are arranged in a matrix, and the fifth area 1035 is located in the central area of ​​the matrix, but the present invention is not limited thereto.

[0111] In this embodiment, the isolation structure 105 includes an isolation trench, a gate oxide layer (not shown) covering the sidewalls and bottom of the isolation trench, and polysilicon filling the isolation trench, that is, the gate oxide layer is located between the polysilicon and the isolation trench.

[0112] The plurality of first doping regions 107 and the plurality of second doping regions 108 extend from the surface of the epitaxial layer 103 to the interior of the epitaxial layer 103, respectively. The first doping regions 107 have a first doping type, and the second doping regions 108 have a second doping type. In this embodiment, the first doping regions 107 are, for example, P+ doping regions, and the second doping regions 108 are, for example, N+ doping regions.

[0113] Optionally, the epitaxial layer 103 further includes a well region 106, the well region 106 extends from the surface of the epitaxial layer 103 to the inside of the epitaxial layer 103, and in the first region 1031, the second region 1032, the third region 1033, and the fourth region 1034, the first doped region 107 is located in the well region 106, and in the fifth region 1035, the first doped region 107 and the second doped region 108 are both located in the well region 106. The well region 106 has a first doping type, and the well region 106 is, for example, a P-type well region.

[0114] Furthermore, the length of the well region 106 is greater than the length of the first doping region 107 and the second doping region 108 , the width of the well region 106 is greater than the width of the first doping region 107 and the second doping region 108 , and the depth of the well region 106 is greater than the depth of the first doping region 107 and the second doping region 108 .

[0115] In this embodiment, the well region 106 within the diode region (the first region 1031, the second region 1032, the third region 1033 and the fourth region 1034) can make the electric field distribution more uniform, prevent the electric field from breaking down on the device surface, and can significantly improve the forward diode's surge resistance and anti-static capabilities, making the device more stable and having better performance.

[0116] Figure 6 FIG. 4 shows a top view of the arrangement of the well region, the first doping region and the second doping region in the bidirectional TVS device of the first embodiment of the present invention; Figure 5 and Figure 6 In the first region 1031, the second region 1032, the third region 1033 and the fourth region 1034, the first doping region 107, the second doping region 108 and the well region 106 are arranged in parallel in a strip shape, wherein the first doping region 107 is located in the well region 106, the second doping region 108 is located in the epitaxial layer 103 outside the well region 106, and the first doping region 107 and the second doping region 108 are alternately distributed. In the fifth region 1035, the well region 106 is rectangular, a plurality of first doping regions 107 and a plurality of second doping regions 108 are arranged in parallel in a strip shape, and a plurality of first doping regions 107 and a plurality of second doping regions 108 are all located inside the well region 106. In a specific embodiment, the number of the first doping regions 107 is 3 to 50; the number of the second doping regions 108 is 3 to 50.

[0117] Further, in the first region 1031, the first doped region 107 in a well region 106, the adjacent second doped region 108, and the epitaxial layer 103 constitute a first diode D1, wherein the first doped region 107 in the first region 1031 is the anode of the first diode D1, and the second doped region 108 in the first region 1031 is the cathode of the first diode D1. The first region 1031 includes at least one first diode D1, and when the first region 1031 includes multiple first diodes D1, the multiple first diodes D1 are connected in parallel.

[0118] In the second region 1032, the first doped region 107 in a well region 106, the adjacent second doped region 108 and the epitaxial layer 103 constitute a second diode D2, wherein the first doped region 107 in the second region 1032 is the anode of the second diode D2, and the second doped region 108 in the second region 1032 is the cathode of the second diode D2. The second region 1032 includes at least one second diode D2, and when the first region 1031 includes multiple second diodes D2, the multiple second diodes D2 are connected in parallel.

[0119] In the third region 1033, the first doped region 107 in one well region 106, the adjacent second doped region 108 and the epitaxial layer 103 constitute a third diode D3, and in the fourth region 1034, the first doped region 107 in one well region 106, the adjacent second doped region 108 and the epitaxial layer 103 constitute a fourth diode D4. In order to maintain good symmetry, the third diode D3 is completely identical to the second diode D2 in area, structure and number; the fourth diode D4 is completely identical to the first diode D1 in area, structure and number.

[0120] In a specific embodiment, in the first region 1031, the second region 1032, the third region 1033 and the fourth region 1034, the width of the first doping region 107 and the second doping region 108 is 1.5um to 10um, the length is 30um to 200um, and the junction depth is 0.3um to 2um. The width, length and depth of the first doping region 107 in the first region 1031 and the third region 1033 are equal, and the width, length and depth of the second doping region 108 are equal; the width, length and depth of the first doping region 107 in the second region 1032 and the fourth region 1034 are equal, and the width, length and depth of the second doping region 108 are equal, so that the current capacity in the forward and reverse directions is the same.

[0121] Further, in the fifth region 1035, the well region 106 and the second doped region 108 in the well region 106 constitute an NPN transistor. Specifically, two adjacent second doped regions 108 constitute the collector and emitter of the NPN transistor, respectively, and the well region 106 between the two second doped regions 108 constitutes the base of the NPN transistor. The first doped region 107 is arranged in the middle and edge of the well region 106, and the first doped region 107 is connected to the second doped region 108 forming the emitter of the NPN transistor through a metal interconnection structure, so that the base and emitter of the NPN transistor are short-circuited. Further, the size of the trigger current can be controlled by setting the number and area of ​​the first doped region 107.

[0122] In a specific embodiment, in the fifth region 1035, the width of the first doping region 107 and the second doping region 108 is 1.5um~10um, the length is 100um~300um, and the junction depth is 0.3um~2um; the spacing between adjacent first doping regions 107 and between adjacent first doping regions 107 and second doping regions 108 is 0.5um~5um.

[0123] Furthermore, the dielectric layer 109 is located on the surface of the epitaxial layer 103 away from the substrate 101, and a plurality of contact holes 1091 are opened in the dielectric layer 109, and the contact holes 1091 penetrate the dielectric layer 109 to expose the plurality of first doped regions 107 and the plurality of second doped regions 108; the contact holes 1091 are filled with metal material (not shown in the figure), and the metal material is in contact with the exposed plurality of first doped regions 107 and the plurality of second doped regions 108 to form a metal interconnection structure of the plurality of first doped regions 107 and the plurality of second doped regions 108.

[0124] Figure 7 FIG. 1 shows a schematic diagram of a circuit connection structure of a bidirectional TVS device according to a first embodiment of the present invention; Figure 5 as well as Figure 7 , the anode of the first diode D1 (the first doping region 107 in the first region 1031) and the cathode of the second diode D2 (the second doping region 108 in the second region 1032) are connected to the first channel I / O1; the cathode of the first diode D1 (the second doping region 108 in the first region 1031), the cathode of the third diode D3 (the second doping region 108 in the third region 1033) and the collector of the NPN transistor (the second doping region 108 forming the collector of the NPN transistor in the fifth region 1035) are connected together and connected to the power supply terminal VCC. The anode of the second diode D2 (the first doping region 107 in the second region 1032), the anode of the fourth diode D4 (the first doping region 107 in the fourth region 1034), the base of the NPN transistor (the first doping region 107 in the fifth region 1035 short-circuited with the emitter of the NPN transistor) and the emitter (the second doping region 108 in the fifth region 1035 forming the emitter of the NPN transistor) are connected together and grounded GND. The anode of the third diode D3 (the first doping region 107 in the third region 1033) and the cathode of the fourth diode D4 (the second doping region 108 in the fourth region 1034) are connected to the second channel I / O2. The collector of the NPN transistor serves as the first potential of the transistor, and the emitter of the NPN transistor serves as the second potential of the transistor.

[0125] In the present embodiment, a lateral NPN transistor with a base and an emitter short-circuited constitutes the voltage regulator part of the bidirectional TVS device. Compared with the bidirectional TVS device in the prior art, the bidirectional TVS device in the present embodiment has a snapback characteristic, wherein the breakdown voltage and the negative resistance (i.e., the retrace amplitude, the difference between BVCB and BVCE) can be adjusted by adjusting the spacing between the second doped regions 108 in the fifth region 1035 (the spacing between the collector and the emitter of the NPN transistor, i.e., the base width of the NPN transistor) and the implantation dose of the second doped region 108 and the well region 106, thereby ultimately making the holding voltage (VH) of the bidirectional TVS device greater than the operating voltage, which will not cause a latch-up problem, and can also make the clamping voltage lower under high current conditions, and the power consumption will be smaller.

[0126] Furthermore, in this embodiment, since the first diode D1 is completely identical to the third diode D3, the second diode D2 is completely identical to the diode D4, and they share a common NPN transistor, the forward and reverse breakdown voltages are equal and have good consistency.

[0127] The consistency of the forward and reverse breakdown voltage of the bidirectional TVS device of this embodiment will be described below in combination with the working process of the bidirectional TVS device of this embodiment. Specifically, FIG. 8 shows a schematic diagram of the current flow direction when a high potential is applied to the first channel I / O1 and a low potential is applied to the second channel I / O2 in the bidirectional TVS device of the first embodiment of the present invention; wherein, Figure 8a is a cross-sectional view of a bidirectional TVS device according to a first embodiment of the present invention, Figure 8b FIG. 4 is a top view of the arrangement of the well region, the first doping region and the second doping region in the bidirectional TVS device of the first embodiment of the present invention, Figure 8c FIG. 1 is a schematic diagram of the circuit connection structure of a bidirectional TVS device according to the first embodiment of the present invention.

[0128] Specifically, when the first channel I / O1 is at a high potential and the second channel I / O2 is at a low potential, the current flows as follows: Figure 8aAs shown. The current flows from the anode of the first diode D1 (the first doping region 107 in the first region 1031) into the cathode of the first diode D1 (the second doping region 108 in the first region 1031), and further into the collector of the NPN transistor (the second doping region 108 constituting the collector in the fifth region 1035). At this time, the base and emitter of the NPN transistor are short-circuited, the collector region and the base region have high doping concentrations, and the depletion regions of the collector region and the base region begin to widen and avalanche breakdown occurs. Avalanche breakdown occurs and collision ionization generates electron-hole pairs. Electrons are sucked into the collector region (the second doping region 108 constituting the collector in the fifth region 1035), and holes are injected into the base region (the well region 106 in the fifth region 1035). The current flows from the base and the emitter (the fifth region 1035). When the inflow current increases, the voltage drop on the base reaches the turn-on voltage of the PN junction formed by the base region (well region 106) and the emitter region (second doped region 108), the NPN transistor will be turned on and enter the amplification region, and the breakdown voltage will drop rapidly to the turn-on voltage of the NPN transistor, and a negative resistance retracement phenomenon will occur. The current will flow out from the second doped region 108 constituting the emitter and flow into the second channel I / O2 through the fourth diode D4. In this way, under certain current conditions, the clamping voltage can be greatly reduced, such as Figure 1 As shown in the middle curve B.

[0129] In this embodiment, the lateral breakdown voltage of the second diode D2 is relatively high (usually 50V to 100V), and the breakdown voltage of the longitudinal PN junction formed by the substrate 101 and the epitaxial layer 103 is greater than 100V. At the same time, in order to make the voltage of the bidirectional TVS device appropriate, the collector-emitter (CE) breakdown voltage is relatively low by adjusting the emitter concentration, base concentration and width of the NPN transistor, generally only a few volts. Compared with the second diode D2, the breakdown voltage of the NPN transistor is much lower. When the first channel I / O1 is high potential and the second channel I / O2 is low potential, a positive voltage is applied to the anode of the first diode D1, the first diode D1 is turned on, and the NPN transistor is first broken down due to its low breakdown voltage, and the current flows from the first diode D1 into the NPN transistor; then the current flows from the emitter of the NPN transistor into the fourth diode D4, and the current flows out from the second channel I / O2 after the fourth diode D4 is forward-conducted. Therefore, the reverse breakdown voltage of the first channel I / O1 to the second channel I / O2 can be expressed as:

[0130] V BR1 =V f1 +V NPN +V f4

[0131] Among them, V f1 is the forward voltage drop of the first diode D1, VNPN is the collector-emitter (CE) breakdown voltage of the NPN transistor, V f4 is the forward voltage drop of the fourth diode D4. When the current flowing through the first diode D1 and the fourth diode D4 is 10mA, V f1 and V f4 About 0.9V, V NPN When used as ESD protection, it can reach 4V~7V, so this bidirectional TVS device is suitable for protecting 3.3V and 5V circuits.

[0132] Similarly, when the second channel I / O2 is at a high potential and the first channel I / O1 is at a low potential, the current flows into the NPN transistor from the forward direction of the third diode D3, and then flows out of the first channel I / O1 through the second diode D2. The reverse breakdown voltage of the second channel I / O2 to the first channel I / O1 can be expressed as:

[0133] V BR2 =V f3 +V NPN +V f2

[0134] Among them, V f3 is the forward voltage drop of the third diode D3, V NPN is the collector-emitter (CE) breakdown voltage of the NPN transistor, V f2 is the forward voltage drop of the second diode D2.

[0135] Since the first diode D1 is exactly the same as the third diode D3, and the second diode D2 is exactly the same as the diode D4, and they share the NPN transistor, V BR1 =V BR2 , the forward and reverse breakdown voltages have good consistency.

[0136] Furthermore, this embodiment uses a diode and a voltage-stabilizing NPN transistor to integrate into a bidirectional TVS device, which can significantly reduce the capacitance of the device. Among them, although the single transistor structure has a good current discharge capability, the larger the area of ​​the transistor area, the larger the I PP The higher the capacitance, the better the ESD resistance. While a single transistor structure has good current discharge capability, its parasitic capacitance is also large, generally from a dozen pF to several dozen pF. This embodiment uses four low-capacitance diodes and an NPN transistor to form a bidirectional TVS device, which can take into account the advantages of both diodes and NPN transistors, and has the characteristics of small capacitance, low residual voltage, and appropriate voltage.

[0137] Specifically, the first doping region 107 and the second doping region 108 are alternately arranged in the epitaxial layer 103, and the alternately arranged first doping region 107 and the second doping region 108 and the epitaxial layer 103 form the first diode D1 to the fourth diode D4. Since the doping concentration of the epitaxial layer 103 is low, the area of ​​the first diode D1 to the fourth diode D4 is small, and the capacitance of the diode is generally 0.1pF to 1pF. The low-capacitance diode and the general-capacitance transistor are integrated into a circuit. The transistor is equivalent to a wire. The circuit can be equivalent to the first diode D1 and the second diode D2 are connected in parallel, the third diode D3 and the fourth diode D4 are connected in parallel, and then the two are connected in series. Assuming that the capacitance C of the first diode D1 D1 The capacitance C of the third diode D3 D3 are equal, and C D1 =C D3 =0.4pF, the capacitance C of the second diode D2 D2 and the capacitance C of the fourth diode D4 D4 are equal, and C D2 = C D4 =0.3pF, then the capacitance C of the first channel I / O1 to the second channel I / O2 T It can be expressed as:

[0138]

[0139] It can be seen from the above formula that by integrating the first diode D1 to the fourth diode D4 and the NPN transistor into one circuit, the capacitance of the bidirectional TVS device is greatly reduced. Furthermore, the capacitance and clamping voltage of the bidirectional TVS device can be adjusted by adjusting the areas of the first diode D1 to the fourth diode D4 and the NPN transistor.

[0140] Figures 9a to 9i The cross-sectional views of various stages in the preparation process of the bidirectional TVS device of the first embodiment of the present invention are shown below. Figures 9a to 9i A method for preparing a bidirectional TVS device according to a first embodiment of the present invention is described.

[0141] like Figure 9a As shown, a substrate 101 is provided. The substrate 101 is a semiconductor layer of a first doping type. In this embodiment, the substrate 101 is, for example, a P-type silicon substrate, and the resistivity of the substrate 101 is 50Ω·cm≤ρ≤200Ω·cm. The parasitic capacitance is reduced by setting the resistivity of the substrate 101.

[0142] like Figure 9bAs shown, an isolation layer 102 and an epitaxial layer 103 are sequentially formed on the substrate 101 , wherein the isolation layer 102 is located on the substrate 101 , and the epitaxial layer 103 is located on the isolation layer 102 .

[0143] Wherein, the isolation layer 102 is an intrinsic semiconductor layer, and the epitaxial layer 103 is a semiconductor layer of the second doping type. In this embodiment, the epitaxial layer 103 is, for example, an N-type epitaxial layer. In this embodiment, the isolation layer 102 is provided between the substrate 101 and the epitaxial layer 103, so that the substrate 101, the isolation layer 102 and the epitaxial layer 103 form a longitudinal PIN junction. Compared with a PN junction without the isolation layer 102, this embodiment can significantly reduce the carrier concentration, thereby reducing the parasitic capacitance. In addition, in the subsequent triode region, the substrate 101 is a P-type substrate, and there is an isolation layer 102 between the substrate 101 and the triode region, and the longitudinal capacitance is very low.

[0144] like Fig.9c As shown, a first oxide layer 1041 having an opening 1041 a is formed on the epitaxial layer 103 .

[0145] In this step, the first oxide layer 1041 is formed on the epitaxial layer 103 by, for example, a deposition process. Further, an opening 1041a is formed in the first oxide layer 1041 by photolithography and etching. The first oxide layer 1041 is, for example, a silicon oxide (SiO2) layer.

[0146] like Figure 9d As shown, an isolation structure 105 is formed.

[0147] In this step, the epitaxial layer 103 , the isolation layer 102 and the substrate 101 are etched through the opening 1041 a to form a plurality of isolation trenches, wherein each isolation trench penetrates the epitaxial layer 103 and the isolation layer 102 and extends to the interior of the substrate 101 .

[0148] Further, a gate oxide layer is formed on the sidewall and bottom of the isolation trench by gate oxide growth, and then the isolation trench is filled with a polysilicon filling process to form an isolation structure 105. The isolation structure 105 divides the semiconductor structure into different regions. In this embodiment, the semiconductor structure is at least isolated to form a first region 1031, a second region 1032, a third region 1033, a fourth region 1034, and a fifth region 1035. Then, the first oxide layer 1041 is removed.

[0149] like Fig.9e As shown, the second oxide layer 1042 is grown by thermal oxidation.

[0150] In this embodiment, the second oxide layer 1042 is, for example, a silicon oxide (SiO 2 ) layer, the thickness of the second oxide layer 1042 is less than the thickness of the first oxide layer 1041 , and the second oxide layer 1042 serves as a masking layer for subsequent ion implantation.

[0151] like Figure 9f As shown, a first ion implantation is performed to form a plurality of well regions 106 .

[0152] In this step, the second oxide layer 1042 is used as a masking layer, and the first doping type impurities are selectively implanted by a photolithography process, and push-up is performed to form a plurality of the well regions 106. The well regions 106 extend from the surface of the epitaxial layer 103 to the inside of the epitaxial layer 103. The plurality of well regions 106 are respectively located in the epitaxial layer 103 in the first region 1031, the second region 1032, the third region 1033, the fourth region 1034, and the fifth region 1035. In the first region 1031, the second region 1032, the third region 1033, and the fourth region 1034, the top view of the well region 106 is in the shape of a long strip, and in the fifth region 1035, the top view of the well region 106 is in the shape of a rectangle.

[0153] like Figure 9g As shown, a second ion implantation is performed to form a first doped region 107 .

[0154] In this step, the second oxide layer 1042 is used as a masking layer, and a high concentration of first doping type impurities are selectively implanted by a photolithography process, and annealing is performed to form a first doping region 107. The first doping region 107 is an implantation region. The first doping region 107 extends from the surface of the well region 106 toward the inside of the well region 106. In the first region 1031, the second region 1032, the third region 1033, and the fourth region 1034, the top view of the first doping region 107 is in the shape of a long strip, and a plurality of the first doping regions 107 are located in the corresponding well region 106.

[0155] like Figure 9h As shown, a third ion implantation is performed to form a second doped region 108 .

[0156] In this step, the second oxide layer 1042 is used as a masking layer, and a high concentration of second doping type impurities are selectively implanted by a photolithography process, and annealing is performed to form a second doping region 108, which is an implantation region. The second doping region 108 extends from the surface of the epitaxial layer 103 to the inside of the epitaxial layer 103. The top view of multiple second doping regions 108 is in the shape of long strips. In the first region 1031, the second region 1032, the third region 1033 and the fourth region 1034, the second doping region 108 is located in the epitaxial layer 103 and is alternately distributed with the first doping region 107. In the fifth region 1035, multiple second doping regions 108 are arranged in parallel inside the well region 106.

[0157] In the first region 1031, the first doped region 107 in the well region 106, the second doped region 108 outside the well region 106, and the epitaxial layer 103 constitute a first diode D1; in the second region 1032, the first doped region 107 in the well region 106, the second doped region 108 outside the well region 106, and the epitaxial layer 103 constitute a second diode D2; in the third region 1033, the first doped region 107 in the well region 106, the second doped region 108 outside the well region 106, and the epitaxial layer 103 constitute a third diode D3; in the fourth region 1034, the first doped region 107 in the well region 106, the second doped region 108 outside the well region 106, and the epitaxial layer 103 constitute a fourth diode D4. The third diode D3 has the same area and structure as the second diode D2; the fourth diode D4 has the same area and structure as the first diode D1.

[0158] In the fifth region 1035, the well region 106 and the second doped region 108 in the well region 106 constitute an NPN transistor. Specifically, two adjacent second doped regions 108 and the well region between the two second doped regions 108 respectively constitute the collector, emitter and base of the NPN transistor. The first doped region 107 is arranged inside and at the edge of the well region 106.

[0159] In a specific embodiment, in the first region 1031, the second region 1032, the third region 1033 and the fourth region 1034, the width of the first doping region 107 and the second doping region 108 is 1.5um to 10um, the length is 30um to 200um, and the junction depth is 0.3um to 2um. In the fifth region 1035, the width of the first doping region 107 and the second doping region 108 is 1.5um to 10um, the length is 100um to 300um, and the junction depth is 0.3um to 2um; the spacing between adjacent first doping regions 107 and between adjacent first doping regions 107 and second doping regions 108 is 0.5um to 5um.

[0160] like Figure 9i As shown, a dielectric layer 109 is formed on the surface of the epitaxial layer 103 , and a contact hole 1091 is formed in the dielectric layer 109 .

[0161] In this step, for example, a deposition process is used to form the dielectric layer 109 on the surface of the epitaxial layer 103. The dielectric layer 109 is, for example, a silicon oxide (SiO2) layer. Further, a plurality of contact holes 1091 are formed in the dielectric layer 109 by using a photolithography process and an etching process. The contact holes 1091 penetrate the dielectric layer 109, exposing the plurality of first doped regions 107 and the plurality of second doped regions 108.

[0162] Furthermore, a metal interconnection structure is formed.

[0163] In this step, metal is deposited in the contact hole 1091 and on the surface of the dielectric layer 109, and the metal is photolithographically and etched to form a metal interconnection structure.

[0164] The metal interconnection structure is electrically connected to the exposed first doping regions 107 and the second doping regions 108 to form a metal interconnection structure of the first doping regions 107 and the second doping regions 108. Figure 5 Optionally, a double-layer metal interconnection structure can be formed as required.

[0165] Specifically, the anode of the first diode D1 (the first doping region 107 in the fifth region 1035) and the cathode of the second diode D2 (the second doping region 108 in the first region 1031) are connected to the first channel I / O1; the cathode of the first diode D1 (the second doping region 108 in the first region 1031), the cathode of the third diode D3 (the second doping region 108 in the third region 1033) and the collector of the NPN transistor are connected together and connected to the power supply terminal VCC. The anode of the second diode D2 (the first doping region 107 in the second region 1032), the anode of the fourth diode D4 (the first doping region 107 in the fifth region 1053), the base and the emitter of the NPN transistor are connected together and grounded GND. The anode of the third diode D3 (the first doping region 107 in the third region 1033) and the cathode of the fourth diode D4 (the second doping region 108 in the fourth region 1034) are connected to the second channel I / O2.

[0166] Furthermore, a passivation layer is deposited on the metal interconnect structure, and the passivation layer is photolithographically and etched to form a pressure point; the substrate is thinned to a suitable thickness to adapt to different packaging forms. The above steps are conventional techniques in the art and will not be repeated here.

[0167] Fig.10 FIG. 4 shows a cross-sectional view of a bidirectional TVS device according to a second embodiment of the present invention. Fig.10 As shown, the bidirectional TVS device includes a substrate 101, an isolation layer 102a, an epitaxial layer 103, an isolation structure 105, a plurality of well regions 106, a plurality of first doped regions 107, a plurality of second doped regions 108, a dielectric layer 109, and a metal interconnection structure.

[0168] The substrate 101 , epitaxial layer 103 , isolation structure 105 , multiple well regions 106 , multiple first doped regions 107 , multiple second doped regions 108 , dielectric layer 109 , and metal interconnect structure in this embodiment are the same as those in the first embodiment and are not described again. Different from the first embodiment, in this embodiment, the isolation layer 102a is an insulating layer, such as a silicon oxide layer, so that the bidirectional TVS device forms a silicon on insulator (SOI) structure, so that the substrate and the epitaxial layer are completely isolated, and further the devices in different regions (such as diodes or transistors) are separated by the isolation layer 102a with good insulation performance, which can prevent the first doping region (P+), the second doping region in different regions and the substrate from forming a parasitic PNPNP structure (SCR structure), thereby preventing the risk of false triggering in the circuit, reducing the parasitic capacitance and leakage current between the substrate 101 and the epitaxial layer 103, and having the advantages of high integration and good radiation resistance.

[0169] The preparation method of the bidirectional TVS device of this embodiment is the same as that of the bidirectional TVS device of the first embodiment, and will not be described in detail here.

[0170] Fig.11 FIG. 4 shows a cross-sectional view of a bidirectional TVS device according to a third embodiment of the present invention. Fig.11 As shown, the bidirectional TVS device includes a substrate 101, an isolation layer 102, an epitaxial layer 103, an isolation structure 105, a plurality of well regions 106, a plurality of first doped regions 107, a plurality of second doped regions 108, a dielectric layer 109, and a metal interconnection structure.

[0171] Different from the first embodiment, in this embodiment, the first doped region 107 is only located in the first region 1031 , the second region 1032 , the third region 1033 and the fourth region 1034 , and the well region 106 of the fifth region 1035 only has the second doped region 108 .

[0172] In this embodiment, the base and emitter of the NPN transistor are not short-circuited, and the NPN transistor is an open-base transistor. When an external voltage causes the collector and base of the NPN transistor to undergo avalanche breakdown, collision ionization generates electron-hole pairs, and electrons are sucked into the collector (the second doping region 108 in the fifth region 1035), and holes are injected into the base (well region 106). When the PN junction formed by the base (well region 106) and the emitter (the second doping region 108 in the fifth region 1035) reaches the forward turn-on voltage, the NPN transistor is turned on and enters the amplification region, and the breakdown voltage drops rapidly to the turn-on voltage of the NPN transistor, and the Snapback (negative resistance retracement) phenomenon occurs.

[0173] In the first embodiment, the base and emitter of the NPN transistor are short-circuited, and holes can flow out through the base. Therefore, the current formed by the well region 106 (the base region of the NPN transistor, i.e., the P region) and the second doped region 108 (the emitter region of the NPN transistor, i.e., the N region) is relatively large when the PN junction is turned on, generally at the mA level. In the present embodiment, the base of the NPN transistor is open, holes cannot flow out through the base, and the current formed by the well region 106 (the base region of the NPN transistor, i.e., the P region) and the second doped region 108 (the emitter region of the NPN transistor, i.e., the N region) is relatively small when the PN junction is turned on, generally at the μA level.

[0174] The preparation method of the bidirectional TVS device of this embodiment is the same as that of the bidirectional TVS device of the first embodiment, and will not be described in detail here.

[0175] Fig.12 FIG. 4 shows a cross-sectional view of a bidirectional TVS device according to a fourth embodiment of the present invention. Fig.12 As shown, the bidirectional TVS device includes a substrate 101, an isolation layer 102, an epitaxial layer 103, an isolation structure 105, a plurality of well regions 106, a plurality of first doped regions 107, a plurality of second doped regions 108, a plurality of first doped regions 107a, a plurality of second doped regions 108a, a dielectric layer 109, and a metal interconnection structure.

[0176] Different from the first embodiment, in this embodiment, a plurality of first doping regions 107a and a plurality of second doping regions 108a are formed in the fifth region 1035; the first doping regions 107a and the second doping regions 108a are deep trench structures filled with doped semiconductor materials.

[0177] Specifically, the well region 106 of the fifth region 1035 has a first deep trench and a second deep trench, the first deep trench is filled with a semiconductor material of a first doping type (e.g., a P-type semiconductor material) to form a first doping region 107a; the second deep trench is filled with a semiconductor material of a second doping type (e.g., an N-type semiconductor material) to form a second doping region 108a. In this embodiment, the first deep trench is filled with, for example, boron-doped polysilicon; the doping concentration is 1E17 to 1E20 cm-3. The second deep trench is filled with, for example, phosphorus-doped polysilicon; the doping concentration is 1E17 to 1E20 cm-3.

[0178] Furthermore, the first deep groove and the second deep groove have the same size, and the bottom curves of the first deep groove and the second deep groove are smooth, so that the electric field is evenly distributed at the bottom of the first deep groove and the second deep groove, thereby improving the stability of the product.

[0179] In a specific embodiment, the width of the top of the first deep groove and the second deep groove is, for example, 1um to 3um, and the depth is, for example, 2um to 6um. The sidewalls of the first deep groove and the second deep groove are inclined, and the inclination angle is 89.0°±0.5°.

[0180] In this embodiment, the area of ​​the NPN transistor is increased by increasing the depth of the first doping region and the second doping region forming the NPN transistor, thereby further improving the current discharge capacity of the NPN transistor; at the same time, the electric field is introduced from the device surface into the epitaxial layer, thereby improving the current discharge capacity, obtaining a lower clamping voltage, and improving the stability of the device.

[0181] Figures 13a to 13k The cross-sectional views at various stages in the preparation process of the bidirectional TVS device according to the fourth embodiment of the present invention are shown.

[0182] in, Fig.13a and Fig.13b The steps shown are similar to those in the first embodiment. Figure 9a and Figure 9b The steps shown are the same and will not be repeated here in this embodiment.

[0183] like Fig.13c As shown, a second oxide layer 1042 is formed on the epitaxial layer 103 .

[0184] In this step, the second oxide layer 1042 is formed on the epitaxial layer 103 by, for example, a deposition process. The second oxide layer 1042 is, for example, a silicon oxide (SiO2) layer, and the thickness of the second oxide layer 1042 is, for example,

[0185] like Fig.13dAs shown, a first ion implantation is performed to form a plurality of well regions 106 .

[0186] In this step, the second oxide layer 1042 is used as a mask layer, and the first doping type impurities are selectively implanted by photolithography, and push-up is performed to form a plurality of well regions 106. The well regions 106 extend from the surface of the epitaxial layer 103 toward the inside of the epitaxial layer 103.

[0187] like Fig.13e As shown, a second ion implantation is performed to form a first doped region 107 .

[0188] In this step, the second oxide layer 1042 is used as a masking layer, and a high concentration of first doping type impurities are selectively implanted by a photolithography process, and annealing is performed to form a first doping region 107. The first doping region 107 extends from the surface of the well region 106 toward the inside of the well region 106. The first doping region 107 is located in a portion of the well region 106.

[0189] like Fig.13f As shown, a third ion implantation is performed to form a second doped region 108 .

[0190] In this step, the second oxide layer 1042 is used as a masking layer, and a high concentration of second doping type impurities are selectively implanted by a photolithography process, and annealing is performed to form a second doping region 108. The second doping region 108 extends from the surface of the epitaxial layer 103 toward the inside of the epitaxial layer 103. A plurality of the second doping regions 108 are located in the epitaxial layer 103 and are alternately distributed with the first doping regions 107. Then the second oxide layer 1042 is removed.

[0191] like Figure 13g As shown, a first oxide layer 1041 having an opening 1041 a is formed on the epitaxial layer 103 .

[0192] In this step, a first oxide layer 1041 is formed on the epitaxial layer 103 by a thin film growth process, and then an opening 1041a is formed in the first oxide layer 1041 by photolithography and etching. The first oxide layer 1041 is, for example, a silicon oxide (SiO2) layer, and has a thickness of, for example, 1.2 um.

[0193] like Fig.13h As shown, an isolation structure 105 is formed.

[0194] In this step, the epitaxial layer 103 , the isolation layer 102 and the substrate 101 are etched through the opening 1041 a to form a plurality of isolation trenches, wherein each isolation trench penetrates the epitaxial layer 103 and the isolation layer 102 and extends to the interior of the substrate 101 .

[0195] Further, the isolation trench is filled with gate oxide growth and polysilicon filling processes, and the polysilicon on the surface of the first oxide layer 1041 is removed by polycrystalline etching or CMP process, leaving only the polysilicon inside the isolation trench, to form an isolation structure 105. The isolation structure 105 divides the semiconductor structure into different regions. In this embodiment, the semiconductor structure is at least isolated to form a first region 1031, a second region 1032, a third region 1033, a fourth region 1034, and a fifth region 1035.

[0196] The first doping region 107, the second doping region 108 and part of the well region 106 are located in the first region 1031, the second region 1032, the third region 1033 and the fourth region 1034. The well region 106 without the first doping region 107 is located in the fifth region 1035.

[0197] like Fig.13i As shown, a first doped region 107a is formed.

[0198] In this step, the epitaxial layer 103 in the fifth region 1035 is photolithographically and etched to form a first deep groove. Specifically, a photoresist is formed on the first oxide layer 1041, and then the photoresist is exposed and developed to form a photoresist mask, and the first oxide layer 1041 is etched through the photoresist mask to form an opening 1041b, and then the photoresist is removed. The first oxide layer 1041 is further used as a hard mask to etch the epitaxial layer 103 in the fifth region 1035 to form a first deep groove.

[0199] Furthermore, a boron-doped polysilicon filling process is adopted to fill the first deep trench with boron-doped polysilicon to form the first doped region 107a. Specifically, a certain proportion of BCl3 and SiH4 is introduced into the reaction furnace tube, the temperature is 510°C to 600°C, and the square resistance is 4ohm to 20ohm, so that the boron-doped polysilicon can fill the first deep trench, and then a polycrystalline etching or CMP process is adopted to remove the boron-doped polysilicon on the surface of the first oxide layer 1041, and only the boron-doped polysilicon in the first deep trench is retained to form the first doped region 107a.

[0200] In this embodiment, the width of the top of the first deep groove is, for example, 1um to 3um, and the depth is, for example, 2um to 6um. The sidewall of the first deep groove is inclined, and the inclination angle is 89.0°±0.5°. The bottom curve of the first deep groove is smooth, so that the electric field is evenly distributed at the bottom of the first deep groove, thereby improving the stability of the product.

[0201] like Fig.13j As shown, a second doping region 108a is formed.

[0202] In this step, the epitaxial layer 103 in the fifth region 1035 is photolithographically and etched to form a second deep groove. Specifically, a photoresist is formed on the first oxide layer 1041, and then the photoresist is exposed and developed to form a photoresist mask, and the first oxide layer 1041 is etched through the photoresist mask to form an opening 1041c, and then the photoresist is removed. The first oxide layer 1041 is further used as a hard mask to etch the epitaxial layer 103 in the fifth region 1035 to form a second deep groove.

[0203] Furthermore, a phosphorus-doped polysilicon filling process is adopted to fill the second deep trench with phosphorus-doped polysilicon to form the second doped region 108a. Specifically, a certain proportion of PH3 and SiH4 is introduced into the reaction furnace tube, the temperature is 510°C to 600°C, and the square resistance is 4ohm to 20ohm, so that the phosphorus-doped polysilicon can fill the second deep trench, and then a polycrystalline etching or CMP process is adopted to remove the boron-doped polysilicon on the surface of the first oxide layer 1041, and only the boron-doped polysilicon in the second deep trench is retained to form the second doped region 108a.

[0204] In this embodiment, the width of the top of the second deep groove is, for example, 1um to 3um, and the depth is, for example, 2um to 6um. The sidewall of the second deep groove is inclined, and the inclination angle is 89.0°±0.5°. The bottom curve of the second deep groove is smooth, so that the electric field is evenly distributed at the bottom of the second deep groove, thereby improving the stability of the product.

[0205] Further, an annealing process is used to push the junction so that the junction depth and diffusion width meet the target requirements. In the fifth region 1035, the well region 106, the first doped region 107a in the well region 106, and the second doped region 108a in the well region 106 constitute an NPN transistor. Specifically, two adjacent second doped regions 108a and the well region 106 between the two second doped regions 108a respectively constitute the collector, emitter, and base of the NPN transistor. The first doped region 107a is arranged inside and at the edge of the well region 106.

[0206] In this embodiment, the stress release of the isolation structure 105 can be performed together with the annealing of the first doping region 107 a and the second doping region 108 a , thus saving steps.

[0207] This embodiment adopts a deep trench filling process to form the NPN transistor. Compared with the first embodiment, the NPN transistor of this embodiment introduces the electric field from the device surface to the bottom of silicon, thereby improving the stability and surge resistance of the device.

[0208] Furthermore, compared with the NPN transistor of the first embodiment, the NPN transistor of the deep trench structure of the present embodiment has a larger effective area, which can significantly improve the surge resistance capability and reduce the clamping voltage.

[0209] Furthermore, compared with the NPN transistor of the first embodiment, the deep trench structure of the NPN transistor of this embodiment has a small lateral diffusion, and more minimum repeating units can be made under the same area, thereby improving the current density per unit area and further improving the surge and ESD resistance of the device.

[0210] Furthermore, in the first embodiment, the ion implantation process is limited by the capability of the implantation machine, and the maximum ion implantation dose can only be 1.0E16 cm -2 The doped polysilicon process of this embodiment can make the doping concentration of N+ and P+ higher, which can improve the emission efficiency of the transistor and reduce the contact resistance, thereby improving I PP capability and lower clamping voltage.

[0211] like Figure 13k As shown, a dielectric layer 109 is formed on the epitaxial layer 103 , and a contact hole 1091 is formed in the dielectric layer 109 .

[0212] This step is similar to that in the first embodiment. Figure 9i The steps shown are the same and will not be repeated here.

[0213] Further, a metal interconnect structure is formed to form Fig.12 The structure shown.

[0214] This step is the same as that in the first embodiment and will not be described again.

[0215] Fig.14 FIG. 4 shows a cross-sectional view of a bidirectional TVS device according to a fifth embodiment of the present invention. Fig.14 As shown, the bidirectional TVS device includes a substrate 101, an isolation layer 102, an epitaxial layer 103, an isolation structure 105, a plurality of well regions 106, a plurality of first doped regions 107a, a plurality of second doped regions 108a, a dielectric layer 109 and a metal interconnection structure.

[0216] Different from the fourth embodiment, in this embodiment, in the first region 1031, the second region 1032, the third region 1033 and the fourth region 1034, the multiple first doping regions 107a are used to replace the multiple first doping regions 107 in the fourth embodiment, and the multiple second doping regions 108a are used to replace the multiple second doping regions 108 in the fourth embodiment.

[0217] Specifically, the well region 106 of the first region 1031, the second region 1032, the third region 1033 and the fourth region 1034 has a first deep trench, and the first deep trench is filled with a semiconductor material of a first doping type (for example, a P-type semiconductor material) to form a first doping region 107a; the epitaxial layer 103 of the first region 1031, the second region 1032, the third region 1033 and the fourth region 1034 has a second deep trench, and the second deep trench is filled with a semiconductor material of a second doping type (for example, an N-type semiconductor material) to form a second doping region 108a. In this embodiment, the first deep trench is filled with, for example, boron-doped polysilicon; the doping concentration is 1E17 to 1E20 cm-3. The second deep trench is filled with, for example, phosphorus-doped polysilicon; the doping concentration is 1E17 to 1E20 cm-3.

[0218] Furthermore, the first deep groove and the second deep groove have the same size, and the bottom curves of the first deep groove and the second deep groove are smooth, so that the electric field is evenly distributed at the bottom of the first deep groove and the second deep groove, thereby improving the stability of the product.

[0219] In a specific embodiment, the width of the top of the first deep groove and the second deep groove is, for example, 1um to 3um, and the depth is, for example, 2um to 6um. The sidewalls of the first deep groove and the second deep groove are inclined, and the inclination angle is 89.0°±0.5°.

[0220] Figure 15a to Figure 15h The cross-sectional views at various stages in the preparation process of the bidirectional TVS device according to the fifth embodiment of the present invention are shown.

[0221] Figures 15a to 15d The steps shown are similar to those in the fourth embodiment. Figures 13a to 13d The steps shown are the same and will not be repeated here in this embodiment.

[0222] Furthermore, if Fig.15e As shown, a first oxide layer 1041 having an opening 1041 a is formed on the epitaxial layer 103 .

[0223] In this step, a first oxide layer 1041 is formed on the epitaxial layer 103 by a thin film growth process, and then an opening 1041a is formed in the first oxide layer 1041 by photolithography and etching. The first oxide layer 1041 is, for example, a silicon oxide (SiO2) layer, and has a thickness of, for example, 1.2 um.

[0224] like Fig.15f As shown, an isolation structure 105 is formed.

[0225] In the step, the epitaxial layer 103 , the isolation layer 102 and the substrate 101 are etched through the opening 1041 a to form a plurality of isolation trenches, wherein each isolation trench penetrates the epitaxial layer 103 and the isolation layer 102 and extends to the interior of the substrate 101 .

[0226] Further, the isolation trench is filled with gate oxide growth and polysilicon filling processes, and the polysilicon on the surface of the first oxide layer 1041 is removed by polycrystalline etching or CMP process, leaving only the polysilicon inside the isolation trench, to form an isolation structure 105. The isolation structure 105 divides the semiconductor structure into different regions. In this embodiment, the semiconductor structure is at least isolated to form a first region 1031, a second region 1032, a third region 1033, a fourth region 1034, and a fifth region 1035.

[0227] like Figure 15g As shown, a first doped region 107a is formed.

[0228] In this step, the epitaxial layer 103 in the first region 1031 to the fifth region 1035 is photolithographically and etched to form a first deep groove. Specifically, a photoresist is formed on the first oxide layer 1041, and then the photoresist is exposed and developed to form a photoresist mask, and the first oxide layer 1041 is etched through the photoresist mask to form an opening 1041b, and then the photoresist is removed. The first oxide layer 1041 is further used as a hard mask to etch the epitaxial layer 103 in the first region 1031 to the fifth region 1035 to form a first deep groove. In the first region 1031 to the fifth region 1035, the first deep groove is located in the well region 106.

[0229] Furthermore, a boron-doped polysilicon filling process is adopted to fill the first deep trench with boron-doped polysilicon to form the first doped region 107a. Specifically, a certain proportion of BCl3 and SiH4 is introduced into the reaction furnace tube, the temperature is 510°C to 600°C, and the square resistance is 4ohm to 20ohm, so that the boron-doped polysilicon can fill the first deep trench, and then a polycrystalline etching or CMP process is adopted to remove the boron-doped polysilicon on the surface of the first oxide layer 1041, and only the boron-doped polysilicon in the first deep trench is retained to form the first doped region 107a.

[0230] In this embodiment, the width of the top of the first deep groove is, for example, 1um to 3um, and the depth is, for example, 2um to 6um. The sidewall of the first deep groove is inclined, and the inclination angle is 89.0°±0.5°. The bottom curve of the first deep groove is smooth, so that the electric field is evenly distributed at the bottom of the first deep groove, thereby improving the stability of the product.

[0231] Furthermore, if Figure 15h As shown, a second doping region 108a is formed.

[0232] In this step, the epitaxial layer 103 in the first region 1031 to the fifth region 1035 is photolithographically and etched to form a second deep groove. Specifically, a photoresist is formed on the first oxide layer 1041, and then the photoresist is exposed and developed to form a photoresist mask, and the first oxide layer 1041 is etched through the photoresist mask to form an opening 1041c, and then the photoresist is removed. The first oxide layer 1041 is further used as a hard mask to etch the epitaxial layer 103 in the first region 1031 to the fifth region 1035 to form a second deep groove. Among them, in the first region 1031 to the fourth region 1034, the second deep groove is located in the epitaxial layer 103 and is alternately distributed with the first deep groove. In the fifth region 1035, the second deep groove is located in the well region 106 and is located between the first deep grooves.

[0233] Furthermore, a phosphorus-doped polysilicon filling process is adopted to fill the second deep trench with phosphorus-doped polysilicon to form the second doped region 108a. Specifically, a certain proportion of PH3 and SiH4 is introduced into the reaction furnace tube, the temperature is 510°C to 600°C, and the square resistance is 4ohm to 20ohm, so that the phosphorus-doped polysilicon can fill the second deep trench, and then a polycrystalline etching or CMP process is adopted to remove the phosphorus-doped polysilicon on the surface of the first oxide layer 1041, and only the phosphorus-doped polysilicon in the second deep trench is retained to form the second doped region 108a.

[0234] In this embodiment, the width of the top of the second deep groove is, for example, 1um to 3um, and the depth is, for example, 2um to 6um. The sidewall of the second deep groove is inclined, and the inclination angle is 89.0°±0.5°. The bottom curve of the second deep groove is smooth, so that the electric field is evenly distributed at the bottom of the second deep groove, thereby improving the stability of the product.

[0235] Furthermore, an annealing process is used to push the junction so that the junction depth and diffusion width meet the target requirements.

[0236] Furthermore, a dielectric layer 109 is formed on the epitaxial layer 103 , a contact hole 1091 is formed in the dielectric layer 109 , and a metal interconnection structure is formed.

[0237] Fig.16 FIG. 4 shows a cross-sectional view of a bidirectional TVS device according to a sixth embodiment of the present invention. Fig.16As shown, the bidirectional TVS device includes a substrate 101, an isolation layer 102, an epitaxial layer 103, an isolation structure 105, a plurality of well regions 106, a plurality of first doped regions 107, a plurality of first doped regions 107a, a plurality of second doped regions 108, a plurality of second doped regions 108a, a dielectric layer 109 and a metal interconnection structure.

[0238] Different from the first embodiment, in this embodiment, a first doping region 107 a is formed under each first doping region 107 , and a second doping region 108 a is formed under each second doping region 108 .

[0239] In the fourth and fifth embodiments, the contact hole 1091 needs to be inside the first doping region 107a and the second doping region 108a. Since the widths of the first deep trench and the second deep trench are relatively small, the process requirements for the contact hole are relatively high, and generally require 0.35um CMOS process processing. In this embodiment, the first doping region 107 and the second doping region 108 are added above the first doping region 107a and the second doping region 108a, respectively. The top widths of the first doping region 107 and the second doping region 108 are greater than the top widths of the first doping region 107a and the second doping region 108a, which reduces the process requirements for the contact hole and can reduce the contact resistance of the contact hole.

[0240] Fig.17 FIG. 4 shows a top view of a bidirectional TVS device according to a seventh embodiment of the present invention. Fig.17 As shown, different from the first embodiment, in this embodiment, in the fifth region, the top view of the first doping region 107 and the second doping region 108 are arranged in a rectangular shape, the side length of the rectangle is 2um to 20um, the spacing is 0.5um to 5um, and the junction depth is 0.3um to 2um.

[0241] Fig.18 FIG. 4 shows a top view of a bidirectional TVS device according to an eighth embodiment of the present invention. Fig.18As shown, different from the first embodiment, in this embodiment, in the fifth region, the first doping region 107 and the second doping region 108 are arranged in a "U-shaped" shape. In this embodiment, the second doping region 108 of the inner circle of the "U-shaped" shape, the well region 106, and the second doping region 108 of the outer circle of the "U-shaped" shape respectively constitute the collector, base and emitter of the NPN triode; in the NPN triode of this embodiment, the current can flow into the emitter of the outer circle through the surrounding of the collector of the inner circle, which increases the perimeter area ratio and improves the emission efficiency and surge resistance of the NPN triode current. Among them, the side length of the second doping region 108 of the inner circle of the "U-shaped" shape is 2um~10um, the width of the first doping region 107 and the second doping region 108 of the outer circle of the "U-shaped" shape is 4um~12um, and the spacing between the second doping region 108 of the inner circle and the first doping region 107 or the second doping region 108 of the outer circle is 0.5um~5um. In this embodiment, the number and size of the first doping region and the second doping region are selected according to actual needs.

[0242] In addition, the outer circle of the “U-shaped” part is the first doped region 107. The number and area of ​​the first doped region 107 can control the magnitude of the trigger current. The first doped region 107 is connected to the emitter through a metal interconnection structure to short-circuit the base and emitter of the transistor.

[0243] Fig.19 FIG. 4 shows a top view of a bidirectional TVS device according to a ninth embodiment of the present invention. Fig.19 As shown, different from the first embodiment, in this embodiment, in the fifth region, the first doping region 107 and the second doping region 108 are arranged in a "ring shape". In this embodiment, the second doping region of the inner ring of the "ring shape", the well region, and the second doping region of the outer ring of the "ring shape" respectively constitute the collector, base and emitter of the NPN triode; in the NPN triode of this embodiment, the current can flow into the emitter of the outer ring through the surrounding of the collector of the inner ring, which increases the perimeter area ratio, improves the emission efficiency and surge resistance of the NPN triode current, and makes the electric field distribution smoother. Among them, the outer diameter of the first doping region and the second doping region of the inner ring of the "ring shape" is 2um~10um, and the outer diameter of the first doping region and the second doping region of the outer ring of the "ring shape" is 4um~12um, and the distance between the first doping region and the second doping region of the inner ring and the first doping region and the second doping region of the outer ring is 0.5um~5um. In other embodiments, the number and size of the first doping region and the second doping region are selected according to actual needs.

[0244] In addition, the outer ring of the "ring-shaped" part is the first doped region 107. The number and area of ​​the first doped region 107 can control the magnitude of the trigger current. The first doped region 107 is connected to the emitter through a metal interconnection structure to short-circuit the base and emitter of the transistor.

[0245] FIG20 shows a schematic diagram of current flow when a high potential is applied to the first channel I / O1 and a low potential is applied to the second channel I / O2 in the bidirectional TVS device of the tenth embodiment of the present invention; wherein, Fig.20a FIG. 4 is a cross-sectional view showing a bidirectional TVS device according to a tenth embodiment of the present invention, Fig.20b FIG. 1 is a top view of the arrangement of the well region, the first doping region, and the second doping region in the bidirectional TVS device according to the tenth embodiment of the present invention. Fig.20c Schematic diagram of the circuit connection structure of the bidirectional TVS device of the tenth embodiment of the present invention. Different from the first embodiment, in this embodiment, the first doping type is an N-type doping type, and correspondingly, the second doping type is a P-type doping type.

[0246] Specifically, in this embodiment, the substrate 101 is, for example, an N-substrate, and the epitaxial layer 103 is, for example, a P-epitaxial layer; the first doping region 107 is an N+ doping region, and the second doping region is a P+ doping region. In the first region 1031, the second region 1032, the third region 1033, and the fourth region 1034, the well region 106 is an N-well, and the first doping region 107 is located in the well region 106; in the first region 1031, the second region 1032, the third region 1933, and the fourth region 1034, a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4 are formed respectively; in the fifth region 1035, the well region 106 is an N-well, and the first doping region 107 and the second doping region 108 are located in the well region 106; a PNP transistor is formed in the fifth region 1035.

[0247] The anode of the first diode D1 (the second doping region 108 in the first region 1031) and the cathode of the second diode D2 (the first doping region 107 in the second region 1032) are connected to the first channel I / O1; the cathode of the first diode D1 (the first doping region 107 in the first region 1031), the cathode of the third diode D3 (the first doping region 107 in the third region 1033) and the emitter of the PNP transistor (the second doping region 108 in the fifth region 1035 forming the emitter of the PNP transistor) are connected together and connected to the power supply terminal VCC. The anode of the second diode D2 (the second doping region 108 in the second region 1032), the anode of the fourth diode D4 (the second doping region 108 in the fourth region 1034), the base of the PNP transistor (the first doping region 107 in the fifth region 1035 short-circuited with the collector of the PNP transistor) and the collector (the second doping region 108 in the fifth region 1035 forming the emitter of the PNP transistor) are connected together and grounded GND. The anode of the third diode D3 (the second doping region 108 in the third region 1033) and the cathode of the fourth diode D4 (the first doping region 107 in the fourth region 1034) are connected to the second channel I / O2. The emitter of the PNP transistor serves as the first potential of the transistor, and the collector of the PNP transistor serves as the second potential of the transistor.

[0248] The bidirectional TVS device and preparation method thereof provided by the present invention integrate a diode and a voltage-stabilizing transistor into a bidirectional TVS device, integrating the advantages of the small capacitance of the diode and the Snapback effect of the short circuit between the base and the emitter of the transistor, taking into account the advantages of both the diode and the transistor, and having the characteristics of small capacitance, low residual voltage and appropriate voltage.

[0249] In a preferred embodiment, a triode with a base and an emitter short-circuited constitutes a voltage regulator part of the bidirectional TVS device, and compared with the bidirectional TVS device in the prior art, it has a snapback characteristic.

[0250] Optionally, a transistor constitutes the voltage regulator part of the bidirectional TVS device, the base of the transistor is open, holes cannot flow out through the base, and the PN junction formed by the base and emitter of the transistor has a small current when turned on, generally at the uA level.

[0251] Furthermore, by adjusting the spacing between the second doped regions in the fifth region (the spacing between the collector and emitter of the transistor, i.e., the base width of the transistor) and the implantation doses of the second doped regions and the well region, the breakdown voltage and the negative resistance can be adjusted, and ultimately the holding voltage of the bidirectional TVS device is made greater than the operating voltage, which will not cause latch-up problems, and can also make the clamping voltage lower under high current conditions, resulting in lower power consumption.

[0252] Furthermore, since the first diode is completely identical to the third diode, the second diode is completely identical to the diode, and they share a transistor, the forward and reverse breakdown voltages of the bidirectional TVS device are equal, and the forward and reverse breakdown voltages have good consistency.

[0253] In a preferred embodiment, the isolation layer is an intrinsic semiconductor layer. By arranging an intrinsic semiconductor layer between the substrate and the epitaxial layer, the substrate, the isolation layer and the epitaxial layer form a longitudinal PIN junction. Compared with the PN junction, the PIN junction can significantly reduce the carrier concentration and thus reduce the capacitance.

[0254] In a preferred embodiment, the isolation layer is an insulating layer, so that the TVS device forms a silicon on insulator (SOI) structure, and devices in different regions are separated by an isolation layer with good insulation performance, which can eliminate the opening of bulk silicon parasitic devices, reduce the parasitic capacitance and leakage current between the substrate and the epitaxial layer, and has the advantages of high integration and good radiation resistance.

[0255] In a preferred embodiment, a deep trench filling process is used to form the first doped region and / or the second doped region in the transistor and / or the diode, and the electric field is introduced from the device surface into the interior of the epitaxial layer, thereby improving the stability and surge resistance of the device.

[0256] Furthermore, the first doped region and / or the second doped region of the deep trench structure enables the transistor and / or the diode to have a larger effective area, which can significantly improve the surge resistance capability and reduce the clamping voltage.

[0257] Furthermore, the deep trench structure in the transistor and / or diode has a small lateral diffusion, and more minimum repeating units can be made under the same area, thereby increasing the current density per unit area and further improving the surge and ESD resistance of the device.

[0258] Furthermore, the ion implantation process is limited by the capacity of the implantation machine, and the maximum ion implantation dose can only be 1.0E16 cm -2The first doping region and / or the second doping region in the triode and / or the diode are formed by a deep trench filling process, which can make the doping concentration of the first doping region and the second doping region higher, improve the emission efficiency of the triode and reduce the contact resistance, thereby improving I PP capability and lower clamping voltage.

[0259] In a preferred embodiment, in the fifth region, the first doped region and the second doped region are arranged in a "U-shape", and the second doped region arranged in the "U-shape" constitutes a transistor. The current can flow through the collector of the inner circle into the emitter of the outer circle, thereby increasing the circumference-to-area ratio and improving the emission efficiency and surge resistance of the transistor current.

[0260] In a preferred embodiment, in the fifth region, the first doped region and the second doped region are arranged in a "circular ring shape", and the second doped region arranged in the "circular ring shape" constitutes a triode. The current can flow into the emitter of the outer circle through the surrounding areas of the collector of the inner circle, thereby increasing the circumference-to-area ratio, improving the emission efficiency and surge resistance of the triode current, and making the electric field distribution smoother.

[0261] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A bidirectional TVS device, comprising: a substrate of a first doping type; an epitaxial layer of a second doping type located on the substrate, wherein the second doping type is opposite to the first doping type; an isolation structure extending from the surface of the epitaxial layer into the substrate, defining a first region, a second region, a third region, a fourth region and a fifth region isolated from each other in the epitaxial layer; wherein a first diode, a second diode, a third diode and a fourth diode are formed in the first region, the second region, the third region and the fourth region respectively, and a triode is formed in the fifth region; and The metal interconnection structure connects the cathodes of the first diode and the third diode to the first potential of the triode, and connects the anodes of the second diode and the fourth diode to the second potential of the triode.

2. The bidirectional TVS device according to claim 1, wherein: The anode of the first diode and the cathode of the second diode are connected to the first channel; the cathode of the first diode, the cathode of the third diode, and the collector of the transistor are connected to the power supply terminal; the anode of the second diode, the emitter of the transistor, and the anode of the fourth diode are grounded; the anode of the third diode and the cathode of the fourth diode are connected to the second channel.

3. The bidirectional TVS device according to claim 1 or 2, wherein: Also includes: a well region, located in the epitaxial layer of the fifth region, the well region having a first doping type; A first doping region of a first doping type is located in the epitaxial layer of the first region, the second region, the third region, and the fourth region; as well as A second doping region of a second doping type is located in the epitaxial layer of the first region, the second region, the third region, the fourth region, and in the well region of the fifth region; In the first region, the second region, the third region and the fourth region, the first doped region, the second doped region and the epitaxial layer constitute a first diode, a second diode, a third diode and a fourth diode respectively; in the fifth region, the second doped region and the well region constitute a triode.

4. The bidirectional TVS device according to claim 3, wherein: The first doping region of the first doping type is also located in the well region of the fifth region. The first doping region in the fifth region is short-circuited with the second doping region forming the transistor emitter to form a transistor with a short-circuited base and emitter in the fifth region.

5. The bidirectional TVS device according to claim 3, wherein: The first region, the second region, the third region, and the fourth region further include a well region, wherein the well region is located in the epitaxial layer, the first doped region is located in the well region, and the second doped region is located outside the well region.

6. The bidirectional TVS device according to claim 1, wherein: An isolation layer is included, wherein the isolation layer is located between the substrate and the epitaxial layer, and the isolation structure penetrates the epitaxial layer and the isolation layer from the surface of the epitaxial layer and extends into the substrate.

7. The bidirectional TVS device according to claim 6, wherein: The isolation layer is an intrinsic semiconductor layer or an insulating layer.

8. The bidirectional TVS device according to claim 3, wherein: The first doped region comprises: An implanted region of a first doping type; and / or a deep trench filled with a semiconductor material of a first doping type; The second doped region comprises: implanted region of a second doping type; and / or A deep trench is filled with a semiconductor material of a second doping type.

9. The bidirectional TVS device according to claim 8, wherein: The width of the first doping region and the second doping region is 1.5um to 20um, and the junction depth is 0.3um to 2um.

10. The bidirectional TVS device according to claim 8, wherein: The width of the top of the first doping region and the second doping region is 1um to 3um, and the depth is 2um to 6um.

11. The bidirectional TVS device according to claim 3, wherein: In the first region, the second region, the third region and the fourth region, the first doping regions and the second doping regions are alternately arranged.

12. The bidirectional TVS device according to claim 3, wherein: In the fifth region, the top-view shapes of the first doping region and the second doping region are strip, rectangle, U-shape, ring, or a combination thereof.

13. The bidirectional TVS device according to claim 1, wherein: The first area, the second area, the third area and the fourth area are arranged in a matrix, and the fifth area is located in a central area of ​​the matrix.

14. The bidirectional TVS device according to claim 1, wherein: The area and structure of the third diode are completely the same as those of the second diode, and the area and structure of the fourth diode are completely the same as those of the first and second diodes.

15. A method for preparing a bidirectional TVS device, comprising: forming an epitaxial layer of a second doping type on a substrate of the first doping type, wherein the second doping type is opposite to the first doping type; forming an isolation structure, the isolation structure extending from the surface of the epitaxial layer into the substrate, defining a first region, a second region, a third region, a fourth region and a fifth region isolated from each other in the epitaxial layer; wherein a first diode, a second diode, a third diode and a fourth diode are formed in the first region, the second region, the third region and the fourth region respectively, and a triode is formed in the fifth region; and A metal interconnection structure is formed, wherein the metal interconnection structure connects the cathodes of the first diode and the third diode to the first potential of the triode, and connects the anodes of the second diode and the fourth diode to the second potential of the triode.

16. The method for preparing a bidirectional TVS device according to claim 15, wherein: The anode of the first diode and the cathode of the second diode are connected to the first channel; the cathode of the first diode, the cathode of the third diode, and the collector of the transistor are connected to the power supply terminal; the anode of the second diode, the emitter of the transistor, and the anode of the fourth diode are grounded; the anode of the third diode and the cathode of the fourth diode are connected to the second channel.

17. The method for preparing a bidirectional TVS device according to claim 15 or 16, wherein: Before or after forming the isolation structure, the method further includes: forming a well region in the epitaxial layer of the fifth region, wherein the well region has a first doping type; forming a first doping region of a first doping type in the epitaxial layers of the first region, the second region, the third region, and the fourth region; and forming a second doping region of a second doping type in the epitaxial layers of the first region, the second region, the third region, and the fourth region and in the well region of the fifth region; In the first region, the second region, the third region and the fourth region, the first doped region, the second doped region and the epitaxial layer constitute a first diode, a second diode, a third diode and a fourth diode respectively; in the fifth region, the second doped region and the well region constitute a triode.

18. The method for preparing a bidirectional TVS device according to claim 17, wherein: Before or after forming the isolation structure, it also includes: forming a first doping region of the first doping type in the fifth region, the first doping region in the fifth region is short-circuited with the second doping region forming the emitter of the transistor, so as to form a transistor with a short-circuited base and emitter in the fifth region.

19. The method for preparing a bidirectional TVS device according to claim 17, wherein: Before or after forming the isolation structure, the method further includes: forming a well region in the epitaxial layer in the first region, the second region, the third region, and the fourth region, wherein the first doped region is located in the well region and the second doped region is located outside the well region.

20. The method for preparing a bidirectional TVS device according to claim 15, wherein: Before forming the epitaxial layer, the method further includes: forming an isolation layer on the substrate, wherein the isolation structure penetrates the epitaxial layer and the isolation layer from the surface of the epitaxial layer and extends into the substrate.

21. The method for preparing a bidirectional TVS device according to claim 20, wherein: The isolation layer is an intrinsic semiconductor layer or an insulating layer.

22. The method for preparing a bidirectional TVS device according to claim 17, wherein: The first doped region comprises: An implanted region of a first doping type; and / or a deep trench filled with a semiconductor material of a first doping type; The second doped region comprises: implanted region of a second doping type; and / or A deep trench is filled with a semiconductor material of a second doping type.

23. The method for preparing a bidirectional TVS device according to claim 22, wherein: An implantation region of the first doping type or an implantation region of the second doping type is formed by ion implantation.

24. The method for preparing a bidirectional TVS device according to claim 22, wherein: The method of forming a deep trench filled with a semiconductor material of a first doping type or a semiconductor material of a second doping type comprises: forming a deep trench extending from a surface of the epitaxial layer to an interior of the epitaxial layer; and The deep trench is filled with a semiconductor material of a first doping type or a semiconductor material of a second doping type to form a first doping region or a second doping region.

25. The method for preparing a bidirectional TVS device according to claim 24, wherein: The semiconductor material of the first doping type is boron-doped polysilicon with a doping concentration of 1E17 to 1E20 cm-3; the semiconductor material of the second doping type is phosphorus-doped polysilicon with a doping concentration of 1E17 to 1E20 cm-3.

26. The method for preparing a bidirectional TVS device according to claim 22, wherein: The width of the first doping region and the second doping region is 1.5um to 20um, and the junction depth is 0.3um to 2um.

27. The method for preparing a bidirectional TVS device according to claim 22, wherein: The width of the top of the first doping region and the second doping region is 1um to 3um, and the depth is 2um to 6um.

28. The method for preparing a bidirectional TVS device according to claim 17, wherein: In the first region, the second region, the third region and the fourth region, the first doping regions and the second doping regions are alternately arranged.

29. The method for preparing a bidirectional TVS device according to claim 17, wherein: In the fifth region, the top-view shapes of the first doping region and the second doping region are strip, rectangle, U-shape, ring, or a combination thereof.

30. The method for preparing a bidirectional TVS device according to claim 15, wherein: The first area, the second area, the third area and the fourth area are arranged in a matrix, and the fifth area is located in a central area of ​​the matrix.

31. The method for preparing a bidirectional TVS device according to claim 15, wherein: The area and structure of the third diode are completely the same as those of the second diode, and the area and structure of the fourth diode are completely the same as those of the first and second diodes.

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