An IGBT chip with a compensation channel

Abstract

The present invention relates to an IGBT chip with a compensation channel. A left emitter region and a left contact hole, a right emitter region and a right contact hole are arranged in the cell. Two P+ deep well regions which are biased to the left and to the right are formed in the P-type base region. This enables, even if a certain offset occurs in each contact hole, the threshold value of the conduction channel on the main emitter region side to increase and the current to decrease, but the conduction channel under the left emitter region or the right emitter region has an increased current due to a decreased threshold value, thereby compensating for the decrease in the current within the cell and ensuring the performance and reliability of the chip.

Description

Technical Field

[0001] The present invention relates to an IGBT chip, and particularly to an IGBT chip with a compensation channel. Background Art

[0002] In an IGBT chip, there are contact holes for high-concentration P-type impurity implantation into the P+ deep well region between adjacent trench gates. As the performance of the trench-type IGBT chip is gradually optimized, its cell size is continuously reduced, which makes the distance between the contact hole and the adjacent gate also decrease.

[0003] Due to the warping of the silicon wafer or the lithography alignment accuracy, the contact hole and the P-type impurity will inevitably deviate from their design centers. When the deviation exceeds a certain range, it will significantly increase the threshold voltage of the corresponding trench, greatly weaken the conductivity of the trench, increase the turn-on voltage drop, reduce the cell current, and thus reduce the overall performance of the chip, making it unable to meet the design requirements of relevant parameters. Summary of the Invention

[0004] Aiming at the defect of the reduction of the cell current caused by the deviation of the contact hole and the P-type impurity implantation, the purpose of the present invention is to provide an IGBT chip with a compensation channel, which can effectively alleviate the reduction of the cell current caused by the deviation of the contact hole and the P-type impurity implantation.

[0005] The IGBT chip with a compensation channel of the present invention includes a chip body, which includes an N-type base region, a collector region located below the N-type base region, a collector metal located below the collector region and connected to the collector region, a P-type base region located above the N-type base region, an insulating dielectric layer located above the P-type base region, and an emitter metal located above the insulating dielectric layer. A plurality of gate trenches are provided in the chip body, polysilicon gates are provided in the gate trenches, a main emitter region, a left emitter region and a right emitter region are provided between adjacent gate trenches. The two sides of the main emitter region are respectively connected to adjacent gate trenches. One end of the left emitter region is connected to the adjacent gate trench on the left, and the other end is separated from the adjacent gate trench on the right. The right end of the right emitter region is connected to the adjacent gate trench on the right, and the other end is separated from the adjacent gate trench on the left;

[0006] A main contact hole, a left contact hole and a right contact hole with their tops all located in the insulating dielectric layer are further provided between adjacent gate trenches. The main contact hole is located in the middle of the main emitter region. The distance between the left contact hole and the adjacent gate trench on the left is less than the distance from the right adjacent gate trench. The distance between the right contact hole and the adjacent gate trench on the right is less than the distance from the left adjacent gate trench. The bottom end of the main contact hole extends to the P-type base region after passing through the main emitter region. The bottom end of the left contact hole extends to the P-type base region after passing through the left emitter region. The bottom end of the right contact hole extends to the P-type base region after passing through the right emitter region;

[0007] The emitter metal extends into the main contact hole, the left contact hole, and the right contact hole respectively. Below the main contact hole, the left contact hole, and the right contact hole, there are P+ deep well regions located in the P-type base region.

[0008] The advantages of the IGBT chip with a compensated channel are that there are a main contact hole in the middle, a left contact hole near the left gate trench, and a right contact hole near the right gate trench between adjacent gate trenches in the cell. Correspondingly, the P+ deep well regions formed after P impurity implantation by each contact hole include a P+ deep well region in the middle, a P+ deep well region near the left gate trench, and a P+ deep well region near the right gate trench. When certain deviations occur in each contact hole due to silicon wafer warping or lithography alignment deviation, not only does the P+ deep well region in the middle deviate, but also the P+ deep well regions below the left contact hole and the right contact hole deviate accordingly, thereby achieving compensation for the channel and cell current.

[0009] Furthermore, in the IGBT chip with a compensated channel of the present invention, an N-type field stop region is provided between the N-type base region and the collector region.

[0010] The above description is only an overview of the technical solution of the present invention. In order to understand the technical means of the present invention more clearly and implement it specifically according to the content of the specification, the following uses embodiments of the present invention to describe it in detail. Brief Description of the Drawings

[0011] Figure 1 is a plan view of an IGBT chip with a compensated channel;

[0012] Figure 2 is Figure 1 the cross-sectional view of the IGBT chip corresponding to the C2 dotted line in

[0013] Figure 3 is Figure 1 the cross-sectional view of the IGBT chip corresponding to the C1 dotted line in

[0014] Figure 4 is Figure 1 the cross-sectional view of the IGBT chip corresponding to the C3 dotted line in

[0015] In the figure, N-type base region 1, collector region 2, collector metal 3, P-type base region 4, insulating dielectric layer 5, emitter metal 6, gate trench 7, polysilicon gate 8, main emitter region 9, left emitter region 10, right emitter region 11, main contact hole 12, left contact hole 13, right contact hole 14, P+ deep well region 15, N-type field stop region 16. Detailed Embodiment

[0016] The specific embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The following embodiments are used to illustrate the present invention, but are not used to limit the scope of the present invention.

[0017] Referring to Figures 1 to 4 , the IGBT chip with a compensation channel in this embodiment includes a chip body. The chip body includes an N-type base region 1, a collector region 2 located below the N-type base region, a collector metal 3 located below the collector region and connected to the collector region, a P-type base region 4 located above the N-type base region, an insulating dielectric layer 5 located above the P-type base region, and an emitter metal 6 located above the insulating dielectric layer. A plurality of gate trenches 7 are provided in the chip body, and polysilicon gate electrodes 8 are provided in the gate trenches. A main emitter region 9, a left emitter region 10, and a right emitter region 11 are provided between adjacent gate trenches. Both sides of the main emitter region are connected to adjacent gate trenches. One end of the left emitter region is connected to the adjacent gate trench on the left side, and the other end is separated from the adjacent gate trench on the right side. The right end of the right emitter region is connected to the adjacent gate trench on the right side, and the other end is separated from the adjacent gate trench on the left side;

[0018] Main contact holes 12, left contact holes 13, and right contact holes 14 with their tops all located in the insulating dielectric layer are also provided between adjacent gate trenches. The main contact hole is located in the middle of the main emitter region. The distance between the left contact hole and the adjacent gate trench on the left side is less than the distance from the adjacent gate trench on the right side. The distance between the right contact hole and the adjacent gate trench on the right side is less than the distance from the adjacent gate trench on the left side. Since the main contact hole is located in the middle of the main emitter region, that is, in the middle of a single cell, this makes the left emitter region deviate to the left side of the main contact hole, and the right emitter region deviate to the right side of the main contact hole. The bottom end of the main contact hole extends to the P-type base region after passing through the main emitter region. The bottom end of the left contact hole extends to the P-type base region after passing through the left emitter region. The bottom end of the right contact hole extends to the P-type base region after passing through the right emitter region;

[0019] The emitter metal extends into the main contact hole, the left contact hole, and the right contact hole respectively. P+ deep well regions 15 located in the P-type base region are provided below the main contact hole, the left contact hole, and the right contact hole.

[0020] In the IGBT chip with a compensation channel of the present invention, there are a main contact hole located in the middle, a left contact hole close to the left gate trench, and a right contact hole close to the right gate trench between adjacent gate trenches in a cell. Correspondingly, the P+ deep well regions formed after P impurity implantation by each contact hole include a P+ deep well region located in the middle, a P+ deep well region close to the left gate trench, and a P+ deep well region close to the right gate trench. When certain deviations occur in each contact hole due to wafer warping or lithography alignment deviation, not only does the P+ deep well region located in the middle deviate, but also the P+ deep well regions below the left contact hole and the right contact hole deviate accordingly, thereby realizing the compensation for the channel and cell current.

[0021] Specifically, when each contact hole has no offset or a small offset, the conductive channel under the main emitter region operates normally. However, for the compensating conductive channels under the left and right emitter regions, due to the influence of P impurities, their threshold voltages are much greater than that of the normal conductive channel, and the current in the channels can be ignored. At this time, the IGBT chip is similar to a normal chip.

[0022] When each contact hole is offset to the right by a certain distance, at this time, the conductive channel under the right emitter region, due to its proximity to the P+ deep well region, has its threshold voltage further increased, and the current in the conductive channel can be ignored.

[0023] At this time, for the conductive channel on the right side under the main emitter region, due to its proximity to the P+ deep well region under the main contact hole, its threshold voltage increases and the current in the channel decreases. However, since the P+ deep well region under the left contact hole also shifts to the right, the distance between the conductive channel under the left emitter region and this P+ deep well region increases, thereby reducing the threshold voltage of this conductive channel and increasing the channel current in the conductive channel. The increased channel current will effectively compensate for the channel current on the right side under the main emitter region, thereby alleviating or eliminating the reduction of the cell current.

[0024] When each contact hole is offset to the left, the compensation process is similar to when it is offset to the right, and will not be elaborated here.

[0025] In specific implementation, both sides of the main emitter region are connected to adjacent gate trenches. The main contact hole is located in the middle of the cell, and it extends from the insulating dielectric layer through the main emitter region into the P-type base region, and its bottom end is located in the P+ deep well region on the surface of the P-type base region.

[0026] The left emitter region is only connected to the left gate trench. The left contact hole deviates to the left from the cell center and extends into the P-type base region through the insulating dielectric layer and the left emitter region, and its bottom end is located in the P+ deep well region on the surface of the P-type base region. The right emitter region and the right contact hole are similar and will not be elaborated here.

[0027] During fabrication, compared with the existing IGBT chips, the IGBT chip with a compensating channel only adds the corresponding process steps for the left emitter region, left contact hole, right emitter region, and right contact hole. The fabrication of the left emitter region is similar to the fabrication method of the emitter region of the existing chips, but during implantation, the implantation region is biased towards the left side of the cell. Similarly, the right emitter region is biased towards the right side of the cell, and the specific fabrication process will not be elaborated here.

[0028] Preferably, for the IGBT chip with a compensating channel in this embodiment, an N-type field stop region 16 is provided between the N-type base region and the collector region.

[0029] The above are only the preferred embodiments of the present invention, which are used to assist those skilled in the art to implement the corresponding technical solutions, rather than to limit the protection scope of the present invention. The protection scope of the present invention is defined by the appended claims. It should be noted that for those of ordinary skill in the art, based on the technical solutions of the present invention, several equivalent improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present invention. At the same time, it should be understood that although this specification is described according to the above embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions of each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. An IGBT chip with a compensation channel, comprising a chip body, the chip body includes an N-type base region (1), a collector region (2) located below the N-type base region, a collector metal (3) located below the collector region and connected to the collector region, a P-type base region (4) located above the N-type base region, an insulating dielectric layer (5) located above the P-type base region, and an emitter metal (6) located above the insulating dielectric layer. A plurality of gate trenches (7) are provided in the chip body, and polysilicon gates (8) are provided in the gate trenches. It is characterized in that: A main emitter region (9), a left emitter region (10) and a right emitter region (11) are provided between adjacent gate trenches. The two sides of the main emitter region are respectively connected to adjacent gate trenches. One end of the left emitter region is connected to the adjacent gate trench on the left side, and the other end is separated from the adjacent gate trench on the right side. The right end of the right emitter region is connected to the adjacent gate trench on the right side, and the other end is separated from the adjacent gate trench on the left side; Main contact holes (12), left contact holes (13) and right contact holes (14) with their tops all located in the insulating dielectric layer are also provided between adjacent gate trenches. The main contact hole is located in the middle of the main emitter region. The distance between the left contact hole and the adjacent gate trench on the left side is less than the distance from the adjacent gate trench on the right side. The distance between the right contact hole and the adjacent gate trench on the right side is less than the distance from the adjacent gate trench on the left side. The bottom end of the main contact hole extends to the P-type base region after passing through the main emitter region. The bottom end of the left contact hole extends to the P-type base region after passing through the left emitter region. The bottom end of the right contact hole extends to the P-type base region after passing through the right emitter region; The emitter metal extends into the main contact hole, the left contact hole and the right contact hole respectively. P+ deep well regions (15) located in the P-type base region are provided below the main contact hole, the left contact hole and the right contact hole.

2. The IGBT chip with a compensation channel according to claim 1, characterized in that: An N-type field stop region (16) is provided between the N-type base region and the collector region.

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