Memory control method, memory, and memory system

Abstract

Embodiments of the present disclosure provide a memory control method, a memory and a memory system. The memory includes a plurality of memory cells, each of which is configured to store N-bit data, where N is an integer greater than 1. The method includes: performing a read operation based on a read voltage corresponding to a target logical page to obtain a hard read value and a soft read value of the target logical page, and storing the hard read value, the soft read value and inhibition information into three latches in a page buffer, respectively; obtaining hard data of the target logical page based on the hard read value of the target logical page; and obtaining soft data of the target logical page based on the hard data and the soft read value of the target logical page.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for controlling a memory, a memory, and a memory system. Background Technology

[0002] With the continuous development of semiconductor technology, memory manufacturing technology has gradually transitioned from simple planar structures to more complex three-dimensional structures, increasing integration density by arranging memory cells three-dimensionally on a substrate. The development of this three-dimensional memory device technology is one of the mainstream international research trends.

[0003] However, reading hard and soft data from storage units takes a long time and requires a significant amount of latches. Summary of the Invention

[0004] In view of the above, this disclosure provides a method for controlling a memory, a memory, and a memory system to solve at least one problem existing in the prior art.

[0005] To achieve the above objectives, the technical solution of this disclosure embodiment is implemented as follows:

[0006] A first aspect of this disclosure provides a method for controlling a memory, the memory including a plurality of storage cells, each storage cell being configured to store N bits of data, where N is an integer greater than 1; the method includes:

[0007] A read operation is performed based on the read voltage corresponding to the target logic page to obtain the hard read value and soft read value of the target logic page, and the hard read value, the soft read value and the disable information are stored in three latches in the page buffer respectively;

[0008] Based on the hard read value of the target logical page, the hard data of the target logical page is obtained;

[0009] Based on the hard data and the soft read value of the target logical page, the soft data of the target logical page is obtained.

[0010] In some embodiments, the page buffer includes a main latch, a bias latch, and N data latches; storing the hard read value, the soft read value, and the disable information into the three latches in the page buffer includes: storing the hard read value, the soft read value, and the disable information into the bias latch, the first data latch among the N data latches, and the main latch; or, storing the hard read value, the soft read value, and the disable information into the first data latch among the N data latches, the bias latch, and the main latch.

[0011] In some embodiments, the method further includes: after obtaining the hard data, releasing the main latch; and after obtaining the soft data, storing the soft data in the main latch.

[0012] In some embodiments, the method further includes: dumping the hard data from the bias latch or the first data latch to a second data latch among the N data latches, dumping the soft data from the main latch to a third data latch among the N data latches, and releasing the bias latch, the first data latch, and the main latch.

[0013] In some embodiments, each target logical page corresponds to at least one read voltage; the step of performing a read operation based on the read voltage corresponding to the target logical page to obtain the hard read value and soft read value of the target logical page includes: after applying each read voltage to the storage cell, obtaining the hard read value and soft read value corresponding to the read voltage through a first sensing and a second sensing respectively; the sensing time of the first sensing is less than the sensing time of the second sensing.

[0014] In some embodiments, when N is 3, each of the storage cells is configured to be 2 3 One of the storage states stores 3 bits of data; the first read voltage through the seventh read voltage is used to distinguish the two... 3 Each storage state.

[0015] In some embodiments, when N is 3, the first logic page of the three logic pages corresponds to the first read voltage and the fifth read voltage; the second logic page of the three logic pages corresponds to the second read voltage, the fourth read voltage and the sixth read voltage; and the third logic page of the three logic pages corresponds to the third read voltage and the seventh read voltage; wherein the first read voltage to the seventh read voltage increases sequentially.

[0016] In some embodiments, when the target logical page is the first logical page, the step of performing a read operation based on the read voltage corresponding to the target logical page to obtain the hard read value and soft read value of the target logical page includes: applying the first read voltage to the storage unit; obtaining the first hard read value and the first soft read value through consecutive first sensing and second sensing respectively; the sensing time of the first sensing is less than the sensing time of the second sensing; applying the fifth read voltage to the storage unit; obtaining the second hard read value and the second soft read value through consecutive third sensing and fourth sensing respectively; the sensing time of the third sensing is less than the sensing time of the fourth sensing; the first hard read value and the second hard read value constitute the hard read value of the first logical page; the first soft read value and the second soft read value constitute the soft read value of the first logical page.

[0017] In some embodiments, performing a read operation based on the read voltage corresponding to the target logical page to obtain the hard read value and soft read value of the target logical page includes: applying a hard read voltage and a soft read voltage to the memory cell respectively to obtain the hard read value and soft read value of the target logical page respectively.

[0018] A second aspect of this disclosure provides a memory comprising: a memory cell array including a plurality of memory cells; each memory cell being configured to store N bits of data, wherein N is an integer greater than 1; and peripheral circuitry coupled to the memory cell array; the peripheral circuitry including a page buffer; the peripheral circuitry being configured to:

[0019] A read operation is performed based on the read voltage corresponding to the target logic page to obtain the hard read value and soft read value of the target logic page, and the hard read value, the soft read value and the disable information are stored in three latches in the page buffer respectively;

[0020] Based on the hard read value of the target logical page, the hard data of the target logical page is obtained;

[0021] Based on the hard data and the soft read value of the target logical page, the soft data of the target logical page is obtained.

[0022] In some embodiments, the page buffer includes a main latch, a bias latch, and N data latches; the peripheral circuitry is specifically configured to: store the hard read value, the soft read value, and the disable information into the bias latch, the first data latch among the N data latches, and the main latch, respectively; or, store the hard read value, the soft read value, and the disable information into the first data latch among the N data latches, the bias latch, and the main latch, respectively.

[0023] In some embodiments, the peripheral circuitry is further configured to: release the main latch after obtaining the hard data; and store the soft data in the main latch after obtaining the soft data.

[0024] In some embodiments, the peripheral circuitry is further configured to: dump the hard data from the bias latch or the first data latch to a second data latch among the N data latches, dump the soft data from the main latch to a third data latch among the N data latches, and release the bias latch, the first data latch, and the main latch.

[0025] In some embodiments, each target logic page corresponds to at least one read voltage; the peripheral circuit is specifically configured to: after applying each read voltage to the memory cell, obtain the hard read value and the soft read value corresponding to the read voltage through a first sensing and a second sensing respectively; the sensing time of the first sensing is less than the sensing time of the second sensing.

[0026] In some embodiments, when N is 3, each of the storage cells is configured to be 2 3 One of the storage states stores 3 bits of data; the first read voltage through the seventh read voltage is used to distinguish the two... 3 Each storage state.

[0027] In some embodiments, when N is 3, the first logic page of the three logic pages corresponds to the first read voltage and the fifth read voltage; the second logic page of the three logic pages corresponds to the second read voltage, the fourth read voltage and the sixth read voltage; and the third logic page of the three logic pages corresponds to the third read voltage and the seventh read voltage; wherein the first read voltage to the seventh read voltage increases sequentially.

[0028] In some embodiments, when the target logical page is the first logical page, the peripheral circuit is specifically configured to: apply the first read voltage to the memory cell; obtain a first hard read value and a first soft read value through continuous first sensing and second sensing respectively; the sensing time of the first sensing is less than the sensing time of the second sensing; apply the fifth read voltage to the memory cell; obtain a second hard read value and a second soft read value through continuous third sensing and fourth sensing respectively; the sensing time of the third sensing is less than the sensing time of the fourth sensing; the first hard read value and the second hard read value constitute the hard read value of the first logical page; the first soft read value and the second soft read value constitute the soft read value of the first logical page.

[0029] In some embodiments, the peripheral circuit is specifically configured to apply a hard read voltage and a soft read voltage to the memory cell respectively to obtain the hard read value and soft read value of the target logic page respectively.

[0030] A third aspect of this disclosure provides a memory system comprising: at least one memory as described above; and a controller coupled to the memory.

[0031] This disclosure provides a method for controlling a memory, a memory, and a memory system. The memory includes multiple storage cells, each configured to store N bits of data, where N is an integer greater than 1. The method includes: performing a read operation based on a read voltage corresponding to a target logical page to obtain a hard read value and a soft read value of the target logical page, and storing the hard read value, the soft read value, and a disable information into three latches in a page buffer, respectively; obtaining hard data of the target logical page based on the hard read value; and obtaining soft data of the target logical page based on the hard data and the soft read value. This disclosure only requires three latches to store the hard read value, soft read value, and disable information respectively during the process of obtaining hard data and soft data, thus reducing latch usage and reserving more latches for reading data from the next logical page. Attached Figure Description

[0032] Figure 1 This is a block diagram of a memory system according to an exemplary embodiment of the present disclosure;

[0033] Figure 2a This is a schematic diagram illustrating a memory card according to an exemplary embodiment of the present disclosure;

[0034] Figure 2b This is a schematic diagram illustrating a solid-state drive (SSD) according to an exemplary embodiment of the present disclosure;

[0035] Figure 3 A schematic diagram of an exemplary memory including peripheral circuitry provided for embodiments of this disclosure;

[0036] Figure 4 A schematic cross-section of an exemplary memory cell array including memory strings, provided for embodiments of this disclosure;

[0037] Figure 5 A block diagram of an exemplary memory including a memory cell array and peripheral circuitry provided for embodiments of this disclosure;

[0038] Figure 6 A schematic diagram of the discharge curve of a sensing node SO provided in an embodiment of this disclosure;

[0039] Figure 7 This is a schematic diagram illustrating a hard data reading process provided in an embodiment of the present disclosure;

[0040] Figure 8a This is a schematic diagram illustrating a soft data reading process provided in an embodiment of the present disclosure;

[0041] Figure 8b This is a schematic diagram illustrating the usage state of a latch in a page buffer during a soft data reading process provided in an embodiment of this disclosure.

[0042] Figure 9 A flowchart illustrating a memory control method provided in an embodiment of this disclosure;

[0043] Figure 10 A schematic diagram of continuous sensing provided for an embodiment of this disclosure;

[0044] Figure 11 This is a schematic flowchart illustrating a memory control method provided in an embodiment of the present disclosure;

[0045] Figure 12a A schematic diagram illustrating a process for reading low-page data of a TLC provided in this embodiment of the disclosure;

[0046] Figure 12b A schematic diagram illustrating the usage state of a latch in a page buffer during the storage process of reading low-page data in a TLC, provided in an embodiment of this disclosure;

[0047] Figure 13a A schematic diagram illustrating a process for reading low-page data of a QLC provided in this embodiment of the disclosure;

[0048] Figure 13b A schematic diagram illustrating the usage state of a latch in a page buffer during the storage process of reading low-page data of a QLC, provided in an embodiment of this disclosure;

[0049] Figure 14 A detailed flowchart illustrating another memory control method provided in this embodiment of the present disclosure;

[0050] Figure 15a This is a schematic diagram illustrating another process for reading low-page data of a TLC, provided in an embodiment of this disclosure.

[0051] Figure 15b A schematic diagram illustrating the usage state of the latch in the page buffer during another storage process for reading low-page TLC data, provided in an embodiment of this disclosure;

[0052] Figure 16a This is a schematic diagram illustrating another process for reading low-page data of a QLC, provided in an embodiment of this disclosure.

[0053] Figure 16b This is a schematic diagram illustrating the usage state of the latch in the page buffer during another storage process for reading low-page data of QLC, as provided in an embodiment of this disclosure. Detailed Implementation

[0054] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0055] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0056] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0057] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0058] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0059] refer to Figure 1 , Figure 1 This is a block diagram illustrating a memory system according to an exemplary embodiment of this disclosure. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory 104.

[0060] Memory 104 can be any memory disclosed in this disclosure. As disclosed in detail below, memory 104 (e.g., NAND flash memory (e.g., three-dimensional (3D) NAND flash memory)) can have reduced leakage current from drive transistors (e.g., string drivers) coupled to unselected word lines during erase operations, which allows for further reduction in the size of the drive transistors.

[0061] According to some embodiments, controller 106 is coupled to memory 104 and host 108 and is configured to control memory 104. Controller 106 can manage data stored in memory 104 and communicate with host 108. In some embodiments, controller 106 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. Controller 106 can be configured to control operations of memory 104, such as read, erase, and program operations. Controller 106 can also be configured to manage various functions related to data stored or to be stored in memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to memory 104. Controller 106 may also perform any other suitable functions, such as formatting memory 104. Controller 106 may communicate with external devices (e.g., host 108) according to specific communication protocols. For example, controller 106 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0062] The controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2aIn one example shown, controller 106 and a single memory 104 can be integrated into memory card 202. Memory card 202 can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. Memory card 202 can also include a connection between memory card 202 and a host (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, controller 106 and multiple memories 104 can be integrated into SSD 206. SSD 206 may also include interfaces for connecting SSD 206 to a host computer (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0063] Figure 3 A schematic circuit diagram of an exemplary memory 300, including peripheral circuitry, is shown according to some aspects of this disclosure. The memory 300 may be... Figure 1 An example of memory 104 is shown. Memory 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array, wherein memory cells 306 are provided in the form of an array of NAND memory strings 308, each extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0064] Each of the aforementioned storage units 306 has any one of a plurality of storage states. Specifically, each storage unit 306 can be configured to have 2 N One of the storage states stores N bits of data, where N is an integer greater than 1. This 2 N The storage states include erase state and 2. N-1 non-erasable state. In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible storage states (levels) and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first threshold voltage range, while a second storage state "1" may correspond to a second threshold voltage range. In some embodiments, each memory cell 306 is an xLC capable of storing more than a single bit of data in more than four storage states (levels). In one example, programming is performed by writing one of three possible nominal storage values ​​to the MLC memory cell to program the MLC memory cell from an erase state to one of three possible programming levels (e.g., 01, 10, and 11). A fourth nominal storage value may be used to indicate an erase state (e.g., 00).

[0065] like Figure 3 As shown, each NAND memory string 308 may further include a source-select-gate (SSG) transistor 310 at its source end and a drain-select-gate (DSG) transistor 312 at its drain end. The SSG transistor 310 and DSG transistor 312 may be configured to activate a selected NAND memory string 308 (column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the drain of each NAND memory string 308 is coupled to a corresponding bit line 316 from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage or deselect voltage to the gate of the corresponding DSG transistor 312 via one or more DSG lines 313 and / or by applying a select voltage or deselect voltage to the gate of the corresponding SSG transistor 310 via one or more SSG lines 315.

[0066] like Figure 3As shown, NAND flash memory strings 308 can be organized into multiple memory blocks 304, each memory block may have a common source line 314 coupled to, for example, an ACS. In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304, an erase voltage (Vers) (e.g., a high positive bias (e.g., 20V or greater)) can be used to bias the source line 314 coupled to the selected memory block 304 and unselected memory blocks 304 in the same plane as the selected memory block 304. Memory cells 306 adjacent to the NAND flash memory string 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a memory page 320 of the memory cell 306, which is the basic data unit for read and program operations. The size of a memory page 320, measured in bits, can be related to the number of NAND memory strings 308 coupled by word lines 318 in a memory block 304. Each word line 318 may include multiple control gates (gate electrodes) and gate lines coupling the control gates at each memory cell 306 in the corresponding memory page 320.

[0067] like Figure 3 As shown, the memory cell array 301 may include an array of memory cells 306 in multiple rows and columns within each memory block 304. According to some embodiments, a row of memory cells 306 corresponds to one or more memory pages 320, and a column of memory cells corresponds to a NAND memory string 308. Multiple rows of memory cells 306 may be coupled to word lines 318, and multiple columns of memory cells 306 may be coupled to bit lines 316. Peripheral circuitry 302 may be coupled to the memory cell array 301 via bit lines 316 and word lines 318.

[0068] Figure 4 A schematic cross-sectional view of an exemplary memory array 301 including NAND memory strings 308 is shown according to some aspects of the present invention. Figure 4 As shown, the NAND memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 stacked alternately in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 can determine the number of memory cells included in the memory array 401.

[0069] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0070] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0071] Return to reference Figure 3 The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0072] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory cell array 301 according to control signals from control logic unit 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a memory page 320 of memory cell array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic unit 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0073] The row decoder / word line driver 508 can be configured to be controlled by the control logic unit 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive SSG lines 315 and DSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform an erase operation on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by the control logic unit 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0074] Control logic unit 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic unit 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic unit 512 and acts as a control buffer to buffer control commands received from a host (not shown) and relay them to control logic unit 512, as well as to buffer status information received from control logic unit 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0075] During a read operation on a memory cell, the channel current varies depending on the cell's storage state (e.g., storing "1" or "0"). Therefore, the storage state of the cell can be obtained by sensing the channel current, thus revealing the data stored within. However, directly measuring the small channel current in a 3D NAND flash memory is difficult. In practical applications, within a small page buffer, the channel current is typically measured indirectly by detecting the discharge of the sensing node SO within the page buffer, thereby obtaining the cell's storage state.

[0076] Figure 6 This is a schematic diagram of the discharge curve of a sensing node SO provided in an embodiment of this disclosure. Figure 6 As shown, during a read operation, the sensing node SO is first charged to a fixed voltage. The sensing node SO is connected to the memory cell via a bit line. If the applied read voltage during the read operation is sufficient to turn on the memory cell, then after a period of time (e.g., ... Figure 6 After ΔT, the sensing node SO will discharge due to the conduction of the memory cell; if the read voltage applied during the read operation cannot turn on the memory cell or can only weakly turn it on, then after a period of time (e.g., ΔT), the reading will continue. Figure 6 After ΔT), the sensing node SO hardly discharges. Based on this, the channel current can be indirectly measured by the voltage change ΔVc of the sensing node SO, thereby obtaining the storage state of the memory cell.

[0077] Typically, data indicating the storage state of a memory cell is called hard data. Hard data is the read value of the bits stored in the memory cell, which can be distinguished by voltages (e.g., ...) used to differentiate the different storage states of the memory cell. Figure 7 V in R1The hard data is obtained by performing a read operation; while the data that indicates the position of the threshold voltage of the memory cell in the threshold voltage distribution corresponding to the memory state of the memory cell is called soft data. Soft data can provide additional reliability information for the hard data. Soft data is based on the additional voltage between the read voltages corresponding to the hard data (e.g., ...). Figure 8a V in R1 -△V and V R1 The soft data value generated at +△V) represents how close the threshold voltage of the storage cell is to the read voltage corresponding to the hard data mentioned above.

[0078] The following combination Figure 7 and Figure 8a The process of reading hard data and soft data is explained. Figure 7 This is a schematic diagram illustrating a hard data reading process provided in an embodiment of this disclosure. Figure 7 As shown, taking a three-level cell (TLC) as an example, each cell can be configured to store 3 bits of data in one of eight storage states (e.g., P0-P7 states). In a TLC, each physical page corresponds to three logical pages: low page (LP), middle page (MP), and high page (UP). For example, when performing a read operation on a cell to read the hard data of the low page, a read voltage V must first be applied to the word line containing that cell. R1 Read voltage V R1 Used to distinguish between the P0 state and the P1-P7 states. V is obtained by detecting the discharge of the sensing node SO. R1 The corresponding hard read value. In some embodiments, the threshold voltage is less than the read voltage V. R1 The hard read value of the memory cell is 1, and the threshold voltage is greater than the read voltage V. R1 The hard read value of the storage unit is 0.

[0079] In other embodiments, the threshold voltage is less than the read voltage V. R1 The hard read value of the memory cell is 0, and the threshold voltage is greater than the read voltage V. R1 The hard read value of the storage cell is 1. This disclosure does not limit this.

[0080] Then apply a read voltage V to the word line where the memory cell is located. R5 Among them, the voltage V is read. R5 Used to distinguish between P0-P4 states and P5-P7 states. V is obtained by detecting the discharge of the sensing node SO. R5 The corresponding hard read value. In some embodiments, the threshold voltage is less than the read voltage V. R5 The hard read value of the memory cell is 1, and the threshold voltage is greater than the read voltage V.R5 The hard read value of the memory cell is 0. Finally, the read voltage V... R5 The corresponding hard read value is inverted and then compared with the read voltage V. R1 The corresponding hard read value is ORed to obtain the hard data corresponding to the lower page.

[0081] Figure 8a This is a schematic diagram illustrating a soft data reading process provided in an embodiment of this disclosure. Figure 8a As shown, taking reading soft data from a lower page in a TLC as an example, the first step is to apply a read voltage V to the word line containing the memory cell to be read. R1 -ΔV, to obtain the reading voltage V R1 -ΔV corresponds to the soft read value. The value of ΔV can be determined based on the threshold voltage distribution of each memory state in the TLC. The threshold voltage of the memory cell is less than the read voltage V. R1 When -△V, V R1 The soft read value corresponding to -ΔV is 1, meaning the threshold voltage of the memory cell is greater than the read voltage V. R1 When -△V, V R1 The soft read value corresponding to -△V is 0. Then, a read voltage V is applied to the word line containing the memory cell. R1 +△V, to obtain the reading voltage V R1 +△V corresponds to the soft read value. The threshold voltage of the memory cell is less than the read voltage V. R1 When +△V, V R1 The soft read value corresponding to +△V is 1, meaning the threshold voltage of the memory cell is greater than the read voltage V. R1 When +△V, V R1 The soft read value corresponding to +△V is 0. Read the voltage V. R1 -ΔV corresponds to the soft read value and the read voltage V R1 The soft read value corresponding to +△V is XORed to obtain V. R1 The corresponding soft read value. Among them, the threshold voltage of the memory cell is greater than V. R1 -△V and less than V R1 When +△V, V R1 The corresponding soft read value is 1, and the threshold voltage of the memory cell is greater than V. R1 +△V or less than V R1 When -△V, V R1 The corresponding soft read value is 0.

[0082] Then, a read voltage V is applied to the word line containing the memory cell to be read. R5 -ΔV and reading voltage V R5 +△V, to obtain V R5 The corresponding soft read value. It should be understood that obtaining V... R5The corresponding soft read value is the same as the V obtained above. R1 The corresponding method for reading soft values ​​is similar, so it will not be described in detail here. Finally, V R1 The corresponding soft read value and V R5 The corresponding soft read values ​​are ORed to obtain the soft data for the lower page. Here, the above method of reading soft data is called softdata single bit read (SDSBR).

[0083] As mentioned above, two read operations are required to obtain the hard data of the TLC low page, while four read operations are required to obtain the soft data of the TLC low page. Since the word line and bit line of the memory cell to be read need to be set accordingly each time a read operation is performed, the required read time is relatively long.

[0084] Figure 8b This diagram illustrates the usage state of a latch in a page buffer during a soft data read process provided in an embodiment of this disclosure. Figure 8b As shown, the TLC page buffer includes a main latch DS, a bias latch DL, and three data latches. Figure 8b (D1, D2, and DC in the diagram). When reading voltage V R1 -△V After completing the read operation, V R1 The soft read value data1 corresponding to -△V is stored in the data latch DL. At this time, the data will be read based on the voltage V. R1 The V obtained after the read operation performed by -△V R5 The prohibition information corresponding to -△V is stored in the bias latch DL. Where V R5 The prohibition information corresponding to -△V is used to indicate: During the read operation corresponding to P5 state (to read voltage V) R5 When performing a read operation (ΔV), the threshold voltage on the same word line as the memory cell to be read is less than the read voltage V. R1 -A read-inhibit voltage is applied to the bit line of the memory cell of ΔV.

[0085] When the reading voltage V R1 After +△V completes the read operation, it stores the data data2 into the data latch DC. Here, data2 is V R1 -△V corresponds to the soft read value and V R1 The result of an XOR operation on the soft read value corresponding to +△V. At this point, the reading voltage V will be used as the basis for the result. R1 The V obtained after the read operation performed by +△V R5 The prohibition information corresponding to +△V is stored in data latch D1. Where V R5The +△V corresponding prohibition information is used to indicate: When reading voltage V... R5 When performing a read operation, the threshold voltage for the memory cell to be read that is located on the same word line is less than the read voltage V. R1 A read-inhibit voltage is applied to the bit line of the memory cell with +△V. However, the bias latch DL still stores V. R5 -△V corresponds to the prohibition information.

[0086] When the reading voltage V R5 When -△V performs a read operation, V R5 - The prohibition information corresponding to △V is dumped from the bias latch DL to the main latch DS, and based on V R5 -△V corresponds to the prohibition information, where the threshold voltage on the same word line as the memory cell to be read is less than the read voltage V. R1 A read disable voltage is applied to the bit line of the memory cell with a read voltage of -ΔV. R5 -△V After completing the read operation, V R5 -The soft read value data3 corresponding to ΔV is stored in data latch D2. At this time, bias latch DL, data latch D1, and data latch DC still store V respectively. R5 -△V corresponds to the prohibition information, V R5 The prohibition information and data corresponding to +△V are in data2.

[0087] When the reading voltage V R5 When +△V performs a read operation, V R5 The prohibition information corresponding to +△V is dumped from data latch D1 to main latch DS, and based on V R5 The +△V corresponding prohibition information indicates that the threshold voltage on the same word line as the memory cell to be read is less than the read voltage V. R1 A read disable voltage is applied to the bit line of the memory cell with a read voltage of +ΔV. R5 After +△V completes the read operation, it stores the soft data data4 into the data latch DC. Here, soft data data4 is the data from V... R5 +△V corresponds to the soft read value and V R5 The result of an XOR operation on the soft read value data3 corresponding to -△V, followed by an OR operation on the data data2, is then used. At this point, the bias latch DL and the data latch D1 still store V respectively. R5 -△V corresponds to the prohibition information and V R5 +△V corresponds to the prohibited information.

[0088] Retrieving soft data from lower pages requires at least five latches. Furthermore, since hard and soft data need to be retrieved separately through different read operations, it cannot simultaneously cache both hard and soft data.

[0089] Therefore, this disclosure provides a method for controlling a memory. Figure 9 This is a flowchart illustrating a memory control method provided in an embodiment of the present disclosure. The memory includes multiple storage cells, each configured to store N bits of data, where N is an integer greater than 1. Figure 9 As shown, in step 901, a read operation is performed based on the read voltage corresponding to the target logic page to obtain the hard read value and soft read value of the target logic page, and the hard read value, soft read value and disable information are stored in three latches in the page buffer respectively.

[0090] The target logical page is the logical page from which the read operation will be performed. For example, when N is 3, that is, in TLC, one physical page corresponds to three logical pages: low page (LP), middle page (MP), and high page (UP). The target logical page can be any one of these three pages. When N is 4, that is, in a Quad-Level Cell (QLC), one physical page corresponds to four logical pages: low page (LP), middle page (MP), high page (UP), and extra page (XP). The target logical page can be any one of these three pages.

[0091] Each target logical page corresponds to at least one read voltage. For example, when N is 3, each memory cell is configured to store 3 bits of data in one of eight memory states, and the first to seventh read voltages are used to distinguish these eight memory states. The first to seventh read voltages increase sequentially. When N is 3, one physical page corresponds to three logical pages. The first logical page corresponds to the first and fifth read voltages. The second logical page corresponds to the second, fourth, and sixth read voltages, and the third logical page corresponds to the third and seventh read voltages. Here, the first logical page can be a low page of the TLC, the second logical page can be a middle page of the TLC, and the third logical page can be a high page of the TLC.

[0092] In some embodiments, a hard read voltage and a soft read voltage are applied to the memory cell to obtain the hard read value and soft read value of the target logical page, respectively. The low page of a TLC is used as an example for illustration. A first hard read voltage (e.g., a first read voltage V) is applied to the memory cell. R1To obtain a first hard read value, a first soft read voltage is applied to the memory cell to obtain a first soft read value. The first soft read voltage can be a voltage larger than the first hard read voltage (e.g., V). R1 +△V); apply a second hard read voltage (e.g., a fifth read voltage V) to the memory cell. R5 To obtain a second hard read value, a second soft read voltage is then applied to the memory cell to obtain a second soft read value. The second soft read voltage can be a voltage larger than the second hard read voltage by a preset value (e.g., V). R5 +△V).

[0093] In other embodiments, performing a read operation based on the read voltage corresponding to the low page (a first read voltage and a fifth read voltage) includes two consecutive sensing operations. For example, a read operation based on the first read voltage corresponding to the low page includes a first sensing and a second sensing. By setting the sensing time of the first sensing to be shorter than the sensing time of the second sensing, the threshold voltage is made such that in the first sensing, the threshold voltage is less than a voltage greater than the first read voltage by a preset value (e.g., V). R1 The read value of the storage cell (+ΔV) is 1, and the threshold voltage is greater than a preset value greater than the first read voltage (e.g., V). R1 The read value of the storage cell (+ΔV) is 0; thus, in the second sensing, the threshold voltage is less than the first read voltage (e.g., V). R1 The read value of the memory cell is 1, and the threshold voltage is greater than the first read voltage (e.g., V). R1 The read value of the storage cell is 0. Thus, by applying a read voltage, a read operation consisting of two consecutive sensing operations can be performed to obtain two different read values ​​corresponding to the voltage (e.g., a first hard read value and a first soft read value).

[0094] The read operation performed in step 901 based on the read voltage corresponding to the target logic page includes two consecutive sensing operations. Figure 10 This is a schematic diagram of continuous sensing provided in an embodiment of this disclosure. For example... Figure 10 As shown, the horizontal axis represents time, and the vertical axis represents voltage. Figure 10 The curves in the diagram represent the voltage change at sensing node SO. T1-T2 represents the first sensing in two consecutive sensing operations, and T2-T3 represents the process of obtaining a hard readout value through the discharge of sensing node SO in the first sensing operation. T3-T4 represents the second sensing in two consecutive sensing operations, and T4-T5 represents the process of obtaining a soft readout value through the discharge of sensing node SO in the second sensing operation. The sensing time of the first sensing operation is shorter than the sensing time of the second sensing operation, i.e., (T2-T1) < (T4-T3).

[0095] The page buffer includes a main latch DS, a bias latch DL, and N data latches. In some embodiments, hard read values, soft read values, and disable information are stored in the bias latch DL, a first data latch among the N data latches, and the main latch DS, respectively. The first data latch is any one of the N data latches. In other embodiments, the hard read value, soft read value, and disable information are stored in the first data latch, the bias latch DL, and the main latch DS, respectively. For example, taking reading low-page data of a TLC as an example, in some embodiments, a read operation is performed based on a first hard read voltage and a first soft read voltage to obtain a first hard read value and a first soft read value. Simultaneously, performing a read operation based on the first soft read voltage can also obtain disable information corresponding to a second hard read voltage. The disable information corresponding to the second hard read voltage indicates that, when a subsequent read operation is performed with the second hard read voltage, a read disable voltage is applied to the bit lines of memory cells located on the same word line as the memory cell to be read, whose threshold voltage is less than the first soft read voltage. Then, the prohibition information corresponding to the first hard read value, the first soft read value, and the second hard read voltage is stored in the bias latch DL, the first latch of the three data latches, and the main latch DS, respectively.

[0096] In other embodiments, a read operation is performed based on a first read voltage to obtain a first hard read value and a first soft read value. Simultaneously, performing a read operation based on the first read voltage can also obtain first prohibition information. This first prohibition information indicates that, in a subsequent read operation performed with a fifth read voltage, a read prohibition voltage should be applied to the bit lines of memory cells located on the same word line as the memory cell to be read, where the threshold voltage is less than the first read voltage. Then, the first hard read value, the first soft read value, and the first prohibition information are stored in the bias latch DL, the first latch of the three data latches, and the main latch DS, respectively.

[0097] In step 902, the hard data of the target logical page is obtained based on the hard read value of the target logical page.

[0098] For example, taking the reading of hard data from the lower page of a TLC as an example, after performing read operations based on a first hard read voltage, a first soft read voltage, a second hard read voltage, and a second soft read voltage to obtain a first hard read value, a first soft read value, a second hard read value, and a second soft read value, respectively; or, after performing a read operation based on the first read voltage to obtain the first hard read value and the first soft read value, and performing a read operation based on a fifth read voltage to obtain the second hard read value and the second soft read value, the result of inverting the second hard read value and performing a bitwise OR operation with the first hard read value is used as the hard data of the lower page. For example, the first hard read value is A, the second hard read value is B, and the hard data...

[0099] In some embodiments, after obtaining hard data, the main latch DS is released. Thus, after obtaining soft data, the main latch DS can store the soft data.

[0100] In step 903, the soft data of the target logical page is obtained based on the hard data and soft read value of the target logical page.

[0101] For example, taking the reading of soft data from the lower page of a TLC as an example, the result of an OR operation between the inverted second soft read value and the first soft read value is then XORed with the aforementioned hard data from the lower page to obtain the soft data from the lower page. For example, if the first soft read value is C, the second soft read value is D, and the hard data is HD, then the soft data...

[0102] In some embodiments, after obtaining the soft data, the soft data is stored in the master latch DS.

[0103] Compared to related technologies, which require separate read operations to obtain hard read values ​​and soft read values, this disclosure obtains both hard read values ​​and soft read values ​​in a single read operation. Furthermore, it uses these hard read values ​​and soft read values ​​obtained in each read operation to obtain hard data and soft data. This avoids the long word line and bit line setup times caused by numerous read operations, thus reducing read time. Moreover, this disclosure only requires three latches to store the hard read value, soft read value, and disable information during the process of obtaining hard data and soft data, allowing more latches to be reserved for reading data from the next logical page.

[0104] In some embodiments, after soft data is stored in the main latch DS, hard data is dumped from the bias latch DL or the first data latch to the second data latch among N data latches, and soft data is dumped from the main latch DS to the third data latch among N data latches. Then, the bias latch DL, the first data latch, and the main latch DS are released. The first data latch, the second data latch, and the third data latch are different data latches among the N data latches. Alternatively, before the read operation of the next logical page data, the hard data can be dumped from the bias latch DL to the second data latch among N data latches, and the soft data can be dumped from the main latch DS to the third data latch among N data latches, and then the bias latch DL, the first data latch, and the main latch DS can be released.

[0105] This disclosure allows for the reading of the next logical page by dumping hard data from the bias latch DL to the second data latch among N data latches, dumping soft data from the main latch DS to the third data latch among N data latches, and releasing the bias latch DL, the first data latch, and the main latch DS.

[0106] Figure 11 This is a schematic flowchart illustrating a memory control method provided in an embodiment of this disclosure. Figure 11 As shown, in step 1101, a prepulse operation is performed. In some embodiments, before performing a read operation, a pass voltage can be applied to the selected word line (i.e., the word line containing the memory cell to be read) and the non-selected word line to turn on the selected word line and the non-selected word line, and turn off the bottom select transistor and top select transistor of the selected memory string (i.e., the memory string containing the memory cell to be read) and / or the non-selected memory string, so as to establish a substantially uniform charge distribution in the channel of the memory cell in each memory string through charge sharing, thereby reducing the degree of read interference and preventing hot carrier injection (HCI) crosstalk between memory strings.

[0107] In step 1102, word lines and bit lines are selected. The row driver can operate in response to a row address signal from the control circuitry to generate word line signals to select the word lines for the read operation. The column driver can operate in response to a column address signal from the control circuitry to generate bit line signals to select the bit lines for the read operation. Thus, a target memory cell can be selected via the selected word lines and bit lines. During the read operation, a read voltage can be applied to the target memory cell via the selected word lines, and a current signal can be sensed from the target memory cell via the selected bit lines to read data from the target memory cell. For example, when reading data from the low page of a TLC, a first read voltage or a fifth read voltage can be applied to the selected word lines, and a pass voltage can be applied to the unselected word lines, while based on inhibit information (e.g., ...). Figure 15b The first prohibition information in the memory cell is used to apply a read prohibition voltage to the bit line where the memory cell is located, and then the data of the target memory cell can be read by detecting the sensing current of the bit line where the target memory cell is located.

[0108] In step 1103, a read operation including one sensing is performed, for example, a read operation is performed based on a first hard read voltage to obtain a first hard read value.

[0109] In step 1104, data latching is performed. The hard read value, soft read value, and disable information are stored in the bias latch DL, the first data latch among the N data latches, and the main latch DS, respectively.

[0110] In step 1105, it is determined whether all read voltages corresponding to the target logic page have been read. For example, taking the reading of data from the low page of TLC as an example, if the first hard read voltage, the first soft read voltage, the second hard read voltage, and the second soft read voltage have all been read, then step 1106 is executed; if there is a read voltage among the first hard read voltage, the first soft read voltage, the second hard read voltage, and the second soft read voltage that has not been read, then steps 1102-1104 are executed based on the read voltage that has not been read to obtain its corresponding hard read value and soft read value.

[0111] In step 1106, logical operations are performed to obtain soft data. For example, taking the reading of data from the low page of a TLC as an example, the result of the OR operation between the inverted second hard read value and the first hard read value is used as the hard data of the low page. For example, if the first hard read value is A and the second hard read value is B, then the hard data... The second soft read value is inverted and then ORed with the first soft read value. The result of this OR operation is then XORed with the aforementioned hard data from the lower page to obtain the soft data from the lower page. For example, if the first soft read value is C and the second soft read value is D, then the soft data SD = the hard data.

[0112] In step 1107, a recovery operation is performed. In some embodiments, the voltage of the selected or unselected word line, selected or unselected positioning line is restored to the initial voltage, which may be 0V.

[0113] Figure 12a This is a schematic diagram illustrating a process for reading low-page data of a TLC, provided as an embodiment of this disclosure. Figure 12a As shown, a first hard read voltage is first applied to the selected word line, wherein the first hard read voltage can be... Figure 12a The V shown R1 .like Figure 12a As shown, the threshold voltage of the memory cell is less than the first hard read voltage V. R1 At that time, the first hard read value is 1, and the threshold voltage of the memory cell is greater than the first hard read voltage V. R1 At that time, the first hard read value of the memory cell is 0. Then, a first soft read voltage is applied to the selected word line, wherein the first soft read voltage can be... Figure 12a The V shown R1 +ΔV, where ΔV can be determined based on the threshold voltage distribution of each memory state in the TLC. The threshold voltage of the memory cell is less than the first soft read voltage V. R1When the value is +ΔV, the first soft read value is 1, and the threshold voltage of the memory cell is greater than the first soft read voltage V. R1 When the value is +ΔV, the first soft read value is 0. In other embodiments, the threshold voltage of the memory cell is less than the first hard read voltage V. R1 At that time, the first hard read value is 0, and the threshold voltage of the memory cell is greater than the first hard read voltage V. R1 At that time, the first hard read value is 1; the threshold voltage of the memory cell is less than the first soft read voltage V. R1 When the threshold voltage of the memory cell is greater than ΔV, the first soft read value is 0, and the threshold voltage of the memory cell is greater than the first soft read voltage V. R1 When +△V, the first soft read value is 1, and this disclosure does not impose any restrictions on this.

[0114] Apply a second hard read voltage to the selected word line (e.g., Figure 12a V in R5 This is used to obtain the second hard read value. The threshold voltage of the memory cell is less than the second hard read voltage V. R5 At that time, the second hard read value is 1, and the threshold voltage of the memory cell is greater than the second hard read voltage V. R5 At that time, the second hard read value is 0. A second soft read voltage is applied to the selected word line (e.g., Figure 12a V in R5 +ΔV) to obtain the second soft read value. The threshold voltage of the memory cell is less than the second soft read voltage V. R5 When the threshold voltage of the memory cell is greater than V, the second soft read value is 1, and the threshold voltage of the memory cell is greater than the second soft read voltage V. R5 When +△V, the second soft read value is 0.

[0115] The result of inverting the second hard read value and performing a bitwise OR operation with the first hard read value is used as the hard data of the lower page. For example, if the first hard read value is A and the second hard read value is B, then the hard data... The result of a bitwise OR operation between the inverted second soft read value and the first soft read value is used as the soft calculated value. For example, if the first soft read value is C, the second soft read value is D, and the soft calculated value is E... The soft-computed value is then XORed with the aforementioned hard data from the lower page to obtain the soft data from the lower page. That is, the soft data... The first hard read value and the second hard read value constitute the hard read value of the TLC low page, and the first soft read value and the second soft read value constitute the soft read value of the TLC low page.

[0116] Figure 12b This diagram illustrates the usage state of a latch in the page buffer during a storage process for reading low-page TLC data, as provided in an embodiment of this disclosure. Figure 12b As shown, the TLC page buffer includes a main latch DS, a bias latch DL, and three data latches. Figure 12b (D1, D2, and DC in the diagram). When the first hard read voltage V R1 After performing the read operation, the first hard read value is stored in the bias latch DL. At this time, the first hard read voltage V is applied. R1 The disable information corresponding to the first soft read voltage obtained from the read operation is stored in the main latch DS. The disable information corresponding to the first soft read voltage indicates that when performing a read operation with the first soft read voltage, the threshold voltage on the selected word line is less than the first hard read voltage V. R1 A read-inhibit voltage is applied to the memory cell.

[0117] When the first soft read voltage V R1 When +△V performs a read operation, based on the disable information corresponding to the first soft read voltage stored in the main latch DS, the threshold voltage on the selected word line is less than the first hard read voltage V. R1 A read-inhibit voltage is applied to the memory cell; when the first soft read voltage V is applied... R1 After the +△V read operation is completed, the first soft read value is stored in the first data latch D1. Here, the bias latch DL still stores the first hard read value. At this time, the disable information corresponding to the second hard read voltage obtained by performing the read operation with the first soft read voltage is stored in the main latch DS. The disable information corresponding to the second hard read voltage indicates that when performing the read operation with the second hard read voltage, the threshold voltage on the selected word line is less than V. R1 A read-inhibit voltage is applied to the +△V memory cell.

[0118] When the second hard read voltage V R5 During a read operation, based on the disable information corresponding to the second hard read voltage stored in the main latch DS, the threshold voltage on the selected word line is less than V. R1 A read-inhibit voltage is applied to the memory cell with a voltage of +△V; when a second hard read voltage V is applied... R5 After the read operation is completed, the hard data is stored in the bias latch DL. Here, the first data latch D1 still stores the first soft read value. At this time, the second hard read voltage V is applied. R5 The disable information corresponding to the second soft read voltage obtained from the read operation is stored in the main latch DS. The disable information corresponding to the second soft read voltage indicates that when performing a read operation with the second soft read voltage, the threshold voltage on the selected word line is less than V. R5 A read-inhibit voltage is applied to the memory cell.

[0119] When the second soft read voltage V R5 When +△V performs a read operation, based on the disable information corresponding to the second soft read voltage stored in the main latch DS, the threshold voltage on the selected word line is less than V.R5 A read-inhibit voltage is applied to the memory cell. When a second soft read voltage V is applied... R5 After the +△V read operation is completed, the soft-computed value is stored in the first data latch D1, and the main latch DS is released. The hard data and the soft-computed value are then XORed to obtain the soft data, which is then stored in the main latch DS. In some embodiments, after storing the soft data in the main latch DS, the hard data is transferred from the bias latch DL to the second data latch D2, and the soft data is transferred from the main latch DS to the third data latch DC. The bias latch DL, the first data latch D1, and the main latch DS are then released so that they can be used for reading the next logical page of data. Alternatively, before the read operation of the next logical page of data, the hard data can be transferred from the bias latch DL to the second data latch D2, the soft data from the main latch DS to the third data latch DC, and the bias latch DL, the first data latch D1, and the main latch DS can be released.

[0120] As described above, compared to related technologies, obtaining the hard data of the TLC low page requires two separate read operations, while obtaining the soft data requires four separate read operations. However, when using the memory control method provided in this disclosure to read the hard and soft data of the TLC low page, only four read operations are needed. Because the number of read operations is reduced, the word line and bit line setup time required for the read operations can be reduced, thereby reducing the read time. Furthermore, this disclosure only requires three latches (e.g., ...) when reading the hard and soft data of the TLC low page. Figure 12b The main latch DS, bias latch DL, and first data latch D1 are included, thus allowing more latches to be reserved for reading data from the next logical page.

[0121] Figure 13a This is a schematic diagram illustrating a process for reading low-page data in a QLC (Quick Memory Library) according to an embodiment of this disclosure. In the QLC, each memory cell is configured to store 4 bits of data in any of 16 memory states (e.g., P0-P15 states). The read voltage V increases sequentially. R1 '-V R15 'Used to distinguish 16 memory states. Among them, the low page corresponds to the read voltage V' R2 '、V R8 'and V R14 Read voltage V R2 Used to distinguish between storage states P0-P1 and P2-P15, and to read voltage V. R8 Used to distinguish storage states P0-P7 and P8-P15, and read voltage V. R14'Used to distinguish between storage states P0-P13 and P14-P15. It should be noted that...' Figure 13a Only the threshold voltage distributions corresponding to storage states P1, P2, P7, P8, P13, and P14 are shown. For example... Figure 13a As shown, a read voltage V is applied to the selected word line respectively. R2 '、V R2 '+△V、V R8 '、V R8 '+△V、V R14 'and V R14 '+△V, to obtain V R2 'Corresponding hard read value and soft read value, V R8 'Corresponding hard read value and soft read value and V R14 'Corresponding hard read value and soft read value.

[0122] Among them, the threshold voltage of the storage cell is less than the read voltage V. R2 At that time, V R2 The corresponding hard read value is 1, and the threshold voltage of the memory cell is greater than the read voltage V. R2 At that time, V R2 The corresponding hard read value is 0; the threshold voltage of the memory cell is less than the read voltage V. R2 When '+△V, V R2 The corresponding soft read value is 1, meaning the threshold voltage of the storage cell is greater than the read voltage V. R2 When '+△V, V R2 The corresponding soft read value is 0; the threshold voltage of the storage cell is less than the read voltage V. R8 At that time, V R8 The corresponding hard read value is 1, and the threshold voltage of the memory cell is greater than the read voltage V. R8 At that time, V R8 The corresponding hard read value is 0; the threshold voltage of the memory cell is less than the read voltage V. R8 When '+△V, V R8 The corresponding soft read value is 1, meaning the threshold voltage of the storage cell is greater than the read voltage V. R8 When '+△V, V R8 The corresponding soft read value is 0; the threshold voltage of the storage cell is less than the read voltage V. R14 At that time, V R14 The corresponding hard read value is 1, and the threshold voltage of the memory cell is greater than the read voltage V. R14 At that time, V R14 The corresponding hard read value is 0; the threshold voltage of the memory cell is less than the read voltage V. R14 When '+△V, V R14 The corresponding soft read value is 1, meaning the threshold voltage of the storage cell is greater than the read voltage V.R14 When '+△V, V R14 The corresponding soft read value is 0. The above V R2 'Corresponding hard read value, V R8 'Corresponding hard read value and V R14 The corresponding hard read value constitutes the hard read value of the low page of the QLC, as mentioned above V R2 'Corresponding soft read value, V R8 'Corresponding soft read value and V R14 The corresponding soft read values ​​constitute the soft read values ​​of the low page of the QLC.

[0123] V R8 The corresponding hard read value is inverted and then compared with V. R2 Perform an OR operation on the corresponding hard-read value, and then combine the above result with V. R14 The corresponding hard read value is ANDed to obtain the hard data. For example, V R2 The corresponding hard read values ​​are A and V. R8 The corresponding hard read value is B, V R14 The corresponding hard read value is C, then the hard data

[0124] V R8 The corresponding soft read value is inverted and then compared with V. R2 Perform an OR operation on the corresponding soft read value, and then combine the above result with V. R14 The corresponding soft read value is ANDed to obtain the soft computed value. For example, V R2 The corresponding soft read values ​​are D and V. R8 The corresponding soft read values ​​are E and V. R14 When the corresponding soft read value is F and the soft compute value is G, the soft compute value is...

[0125] The result of XORing the hard data and the soft computed value is used as the soft data of the lower page of the QLC. That is, soft data SD = hard data HD XOR soft computed value G.

[0126] Figure 13b This diagram illustrates the usage state of the latch in the page buffer during a storage process for reading low-page data in a QLC, as provided in an embodiment of this disclosure. Figure 13b As shown, the page buffer of the QLC includes one main latch DS, one bias latch DL, and four data latches. Figure 13b (D1, D2, D3, and DC in the text). When V R2 After completing the read operation, V R2 The corresponding hard read value is stored in the bias latch DL. At this point, V will be... R2 The V obtained after performing the read operationR2 The prohibition information corresponding to '+△V' is stored in the main latch DS. Where V... R2 The prohibition information corresponding to '+△V' is used to indicate: when V R2 When performing a read operation, the threshold voltage on the selected word line is less than the read voltage V. R2 A read-inhibit voltage is applied to the memory cell.

[0127] When V R2 When '+△V' performs a read operation, it is based on V in the master latch DS. R2 The "+△V" message indicates that the threshold voltage on the selected word line is less than the read voltage V. R2 A read-inhibit voltage is applied to the memory cell. When V R2 After '+△V completes the read operation, V will...' R2 The corresponding soft read value is stored in the first data latch D1. Here, the bias latch DL still stores V. R2 The corresponding hard read value. At this point, it will be represented by V. R2 The V obtained by performing the read operation on '+△V' R8 The corresponding prohibition information is stored in the main latch DS. Among them, V R8 The corresponding prohibition information is used to indicate: when using V R8 'When performing a read operation, the threshold voltage on the selected word line is less than the read voltage V.' R2 A read-inhibit voltage is applied to the memory cell with '+△V'.

[0128] When V R8 When performing a read operation, based on V in the master latch DS R8 The corresponding prohibition information indicates that the threshold voltage on the selected word line is less than the read voltage V. R2 A read-inhibit voltage is applied to the memory cell with a voltage of '+△V'. When V R8 After the read operation is completed, the data Data1 is stored in the bias latch DL. Here, data Data1 is V. R8 'The corresponding hard read value is inverted and summed with V R2 The result of the OR operation on the corresponding hard-read value, for example, V R2 The corresponding hard read values ​​are A and V. R8 The corresponding hard read value is B, then Here, the first data latch D1 still stores V. R2 'Corresponding soft read value. At this time, it will be in V R8 'V obtained by performing a read operation R8 The prohibition information corresponding to '+△V' is stored in the main latch DS. Where V... R8 The prohibition information corresponding to '+△V' is used to indicate: when VR8 When performing a read operation, the threshold voltage on the selected word line is less than the read voltage V. R8 A read-inhibit voltage is applied to the memory cell.

[0129] When V R8 When '+△V' performs a read operation, it is based on V in the master latch DS. R8 The "+△V" message indicates that the threshold voltage on the selected word line is less than the read voltage V. R8 A read-inhibit voltage is applied to the memory cell. When V R8 After the read operation is completed (+△V), the data Data2' is stored in the data latch D1. Here, data Data2' is V. R8 The corresponding soft read value is inverted and summed with V. R2 The result of the OR operation on the corresponding soft read value, for example, V R2 The corresponding soft read values ​​are D and V. R8 The corresponding soft read value is F, then Here, the bias latch DL still stores the data Data1'. At this time, it will be V R8 The V obtained by performing the read operation on '+△V' R14 The corresponding prohibition information is stored in the main latch DS. Among them, V R14 The corresponding prohibition information is used to indicate: when using V R14 'When performing a read operation, the threshold voltage on the selected word line is less than the read voltage V.' R8 A read-inhibit voltage is applied to the memory cell with '+△V'.

[0130] When V R14 When performing a read operation, based on V stored in the master latch DS R14 The corresponding prohibition information applies when the threshold voltage on the selected word line is less than the read voltage V. R8 A read-inhibit voltage is applied to the memory cell with a voltage of '+△V'. When V R14 After the read operation is completed, the hard data is stored in the bias latch DL. The hard data consists of the aforementioned Data1 and V. R14 The result of performing a bitwise AND operation on the corresponding hard-read value, for example, V. R14 When the corresponding hard read value is C, the hard data HD = Data1' & C. Here, the data latch D1 still stores the data Data2'. At this time, V... R14 'V obtained by performing a read operation R14 The prohibition information corresponding to '+△V' is stored in the main latch DS. Where V... R14 The prohibition information corresponding to '+△V' is used to indicate: when V R14When performing a read operation, the threshold voltage on the selected word line is less than the read voltage V. R14 A read-inhibit voltage is applied to the memory cell.

[0131] When V R14 When '+△V' performs a read operation, it is based on V stored in the main latch DS. R14 The "+△V" message indicates that the threshold voltage on the selected word line is less than the read voltage V. R14 A read-inhibit voltage is applied to the memory cell. When V R14 After the read operation is completed, the soft-calculated value is stored in the data latch D1. The soft-calculated value is the aforementioned data Data2' and V. R14 The result of performing a bitwise AND operation on the corresponding soft read value, for example, V R14 When the corresponding soft read value is F and the soft calculation value is G, G = Data2' & F. At this time, the main latch DS still stores V. R14 The prohibited information corresponding to '+△V'.

[0132] Then, release the main latch DS, perform an XOR operation between the hard data and the soft computed value to obtain the soft data. For example, if the soft computed value is G, then the soft data SD = HD XOR G, and store the soft data in the main latch DS.

[0133] In some embodiments, after soft data is stored in the main latch DS, hard data is dumped from the bias latch DL to the data latch D3, soft data is dumped from the main latch DS to the data latch DC, and the bias latch DL, data latch D1, and main latch DS are released so that they can be used for reading the next page of data. Alternatively, the hard data can be dumped from the bias latch DL to the data latch D3, the soft data from the main latch DS to the data latch DC, and the bias latch DL, data latch D1, and main latch DS can be released before the read operation of the next logical page of data.

[0134] As described above, compared to related technologies, obtaining the hard data corresponding to the QLC requires three separate read operations, and obtaining the soft data of the lower page of the QLC requires six separate read operations. However, when using the memory control method provided in this embodiment to read the hard and soft data of the lower page of the QLC, only six read operations are needed. Because the number of read operations is reduced, the word line and bit line setup time required for the read operations can be reduced, thereby reducing the read time. Furthermore, this disclosure does not require more latches when reading the hard and soft data of the lower page of the QLC; only three latches are needed (e.g., ...). Figure 13bThe main latch (DS), bias latch (DL), and data latch (D1) are located in the main latch, thus allowing more latches to be reserved for reading data from the next logical page.

[0135] Figure 14 This is a schematic flowchart illustrating another memory control method provided in an embodiment of this disclosure. It should be understood that... Figure 14 Steps 1401-1402 in the above are the same as those mentioned above. Figure 11 Steps 1101-1102 are similar and can be referred to the descriptions corresponding to steps 1101-1102 above, which will not be repeated here. In step 1403, a read operation including two consecutive sensing operations is performed. In some embodiments, by performing as follows Figure 10 The diagram shows two consecutive sensing operations to obtain the hard read value and soft read value corresponding to the read voltage.

[0136] In step 1404, data latching is performed. The hard read value, soft read value, and disable information are stored in the bias latch DL, the first data latch among the N data latches, and the main latch DS, respectively.

[0137] In step 1405, it is determined whether all read voltages corresponding to the target logic page have undergone read operations. For example, taking the reading of data from the low page of the TLC as an example, if both the first read voltage and the fifth read voltage have undergone read operations, then step 1406 is executed; if there is a read voltage among the first and fifth read voltages that has not undergone read operations, then steps 1402-1404 are executed based on the read voltage that has not undergone read operations to obtain its corresponding hard read value and soft read value. Steps 1406-1407 are the same as described above. Figure 11 Steps 1106-1107 are similar and can be referred to the descriptions of steps 1106-1107 above, which will not be repeated here.

[0138] Figure 15a This is a schematic diagram illustrating another process for reading low-page data of a TLC, provided as an embodiment of this disclosure. For example... Figure 15a As shown, a first read voltage is first applied to the selected word line, and a first hard read value and a first soft read value are obtained through consecutive first and second sensing, respectively. The sensing time of the first sensing is shorter than the sensing time of the second sensing. The method for obtaining the first hard read value and the first soft read value through consecutive first and second sensing is as described above. Figure 10 As described above, it will not be repeated here. The first reading voltage can be... Figure 15a The reading voltage V shown R1 or V R1 +ΔV, where ΔV can be determined based on the threshold voltage distribution of each storage state in the TLC. For example... Figure 15aAs shown, the threshold voltage of the memory cell is less than the read voltage V. R1 At that time, the first hard read value is 1, and the threshold voltage of the memory cell is greater than the read voltage V. R1 At that time, the first hard read value of the memory cell is 0; the threshold voltage of the memory cell is less than the read voltage V. R1 When the value is +ΔV, the first soft read value is 1, and the threshold voltage of the memory cell is greater than the read voltage V. R1 When the value is +ΔV, the first soft read value is 0. In other embodiments, the threshold voltage of the memory cell is less than the read voltage V. R1 At that time, the first hard read value is 0, and the threshold voltage of the memory cell is greater than the read voltage V. R1 At that time, the first hard read value is 1; the threshold voltage of the memory cell is less than the read voltage V. R1 When the value is +ΔV, the first soft read value is 0, and the threshold voltage of the memory cell is greater than the read voltage V. R1 When +△V is applied, the first soft read value is 1. This disclosure does not impose any limitations on the comparison.

[0139] Then, a fifth read voltage is applied to the selected word line, and the second hard read value and the second soft read value are obtained through consecutive third and fourth sensing, respectively. The sensing time of the third sensing is shorter than the sensing time of the fourth sensing. The threshold voltage of the memory cell is less than the read voltage V. R5 At that time, the second hard read value is 1, and the threshold voltage of the memory cell is greater than the read voltage V. R5 At that time, the second hard read value is 0; the threshold voltage of the memory cell is less than the read voltage V. R5 When the value is +ΔV, the second soft read value is 1, and the threshold voltage of the memory cell is greater than the read voltage V. R5 When +△V, the second soft read value is 0.

[0140] The result of inverting the second hard read value and performing a bitwise OR operation with the first hard read value is used as the hard data of the lower page. For example, if the first hard read value is A and the second hard read value is B, then the hard data... The result of a bitwise OR operation between the inverted second soft read value and the first soft read value is used as the soft calculated value. For example, if the first soft read value is C, the second soft read value is D, and the soft calculated value is E... The soft-computed value is then XORed with the aforementioned hard data from the lower page to obtain the soft data from the lower page. That is, the soft data... The first hard read value and the second hard read value constitute the hard read value of the TLC low page, and the first soft read value and the second soft read value constitute the soft read value of the TLC low page.

[0141] Figure 15bThis diagram illustrates the usage state of latches in the page buffer during another storage process for reading low-page TLC data, as provided in an embodiment of this disclosure. After the first read operation is performed, i.e., after performing the read operation with the first read voltage, the first hard read value is stored in the bias latch DL, and the first soft read value is stored in the first data latch D1. At this time, the first inhibit information obtained based on the first read operation is stored in the main latch DS. Wherein, when the first read voltage is V... R1 At this time, the first prohibition message is used to indicate that when performing the second read operation, that is, when performing the read operation with the fifth read voltage, the threshold voltage on the selected word line is less than the read voltage V. R1 A read-inhibit voltage is applied to the memory cell; when the first read voltage is V R1 When +ΔV is applied, the first prohibition message indicates that during the second read operation, the threshold voltage on the selected word line is less than the read voltage V. R1 A read-inhibit voltage is applied to the +△V memory cell.

[0142] When performing the second read operation, that is, when performing the read operation with the fifth read voltage, the main latch DS still stores the first prohibition information, and based on the first prohibition information stored in the main latch DS, the threshold voltage on the selected word line is less than the read voltage V. R1 or V R1 A read-inhibit voltage is applied to the +△V storage cell. After the second read operation is completed, the hard data is stored in the bias latch DL, the soft-calculated value is stored in the first data latch D1, and the main latch DS is released. The hard data and the soft-calculated value are XORed to obtain the soft data, which is then stored in the main latch DS.

[0143] In some embodiments, after soft data is stored in the main latch DS, hard data is dumped from the bias latch DL to the second data latch D2, soft data is dumped from the main latch DS to the third data latch DC, and the bias latch DL, the first data latch D1, and the main latch DS are released so that they can be used for reading the next logical page of data. Alternatively, the hard data can be dumped from the bias latch DL to the second data latch D2, the soft data can be dumped from the main latch DS to the third data latch DC, and the bias latch DL, the first data latch D1, and the main latch DS can be released before the read operation of the next logical page of data.

[0144] When reading TLC low-page data using the memory control method provided in this disclosure, only two read operations are needed to simultaneously obtain hard data and soft data, further reducing the number of read operations. This reduces the word line and bit line setup time required for the read operations. Although this disclosure adds one sensing operation compared to related technologies, the time required for one sensing operation is negligible compared to the word line and bit line setup time. Therefore, this disclosure reduces the read time. Furthermore, when reading hard and soft data from the TLC low page, this disclosure only requires three latches (e.g., Figure 15b The main latch DS, bias latch DL, and first data latch D1 are included, thus allowing more latches to be reserved for reading data from the next logical page.

[0145] Figure 16a This diagram illustrates another process for reading low-page data from a QLC, as provided in an embodiment of this disclosure. In the QLC, each memory cell is configured to store 4 bits of data in any of 16 memory states (e.g., P0-P15 states). The read voltage V increases sequentially. R1 '-V R15 'Used to distinguish 16 memory states. Among them, the low page corresponds to the read voltage V' R2 '、V R8 "and V R14 Read voltage V R2 Used to distinguish between storage states P0-P1 and P2-P15, and to read voltage V. R8 Used to distinguish storage states P0-P7 and P8-P15, and read voltage V. R14 'Used to distinguish between storage states P0-P13 and P14-P15. It should be noted that...' Figure 16a Only the threshold voltage distributions corresponding to storage states P1, P2, P7, P8, P13, and P14 are shown. For example... Figure 16a As shown, firstly, a read voltage V is applied to the selected word line. R2 ', V is obtained through consecutive fifth and sixth sensing respectively. R2 The corresponding hard read value and soft read value. The sensing time of the fifth sensor is shorter than the sensing time of the sixth sensor. In some other embodiments, a read voltage V is applied to a selected word line. R2 +△V, V is obtained through the fifth and sixth consecutive senses respectively. R2 The corresponding hard read value and soft read value, where the value of ΔV can be determined based on the threshold voltage distribution of each storage state in the QLC. V is obtained through consecutive fifth and sixth sensing. R2 The corresponding hard read value and soft read value are similar to the method described above for obtaining the first hard read value and the first soft read value through continuous first sensing and second sensing, respectively, and will not be repeated here.

[0146] like Figure 16a As shown, the threshold voltage of the memory cell is less than the read voltage V. R2 At that time, V R2 The corresponding hard read value is 1, and the threshold voltage of the memory cell is greater than the read voltage V. R2 At that time, V R2 The corresponding hard read value is 0; the threshold voltage of the memory cell is less than the read voltage V. R2 When '+△V, V R2 The corresponding soft read value is 1, meaning the threshold voltage of the storage cell is greater than the read voltage V. R2 When '+△V, V R2 The corresponding soft read value is 0. In other embodiments, the threshold voltage of the memory cell is less than the read voltage V. R2 At that time, V R2 The corresponding hard read value is 0, and the threshold voltage of the memory cell is greater than the read voltage V. R2 At that time, V R2 The corresponding hard read value is 1; the threshold voltage of the memory cell is less than the read voltage V. R2 When '+△V, V R2 The corresponding soft read value is 0, and the threshold voltage of the storage cell is greater than the read voltage V. R2 When '+△V, V R2 The corresponding soft read value is 1. This disclosure does not impose any restrictions on this.

[0147] Then apply the read voltage V to the selected word line. R8 ', V is obtained through the seventh and eighth consecutive sensing respectively. R8 The corresponding hard read value and soft read value. The sensing time of the seventh sensor is shorter than that of the eighth sensor. The threshold voltage of the memory cell is less than the read voltage V. R8 At that time, V R8 The corresponding hard read value is 1, and the threshold voltage of the memory cell is greater than the read voltage V. R8 At that time, V R8 The corresponding hard read value is 0; the threshold voltage of the memory cell is less than the read voltage V. R8 When '+△V, V R8 The corresponding soft read value is 1, meaning the threshold voltage of the storage cell is greater than the read voltage V. R8 When '+△V, V R8 The corresponding soft read value is 0.

[0148] Next, a read voltage V is applied to the selected word line. R14 ', V is obtained through consecutive ninth and tenth sensing respectively. R14The corresponding hard read value and soft read value. The sensing time of the ninth sensor is shorter than that of the tenth sensor. The threshold voltage of the memory cell is less than the read voltage V. R14 At that time, V R14 The corresponding hard read value is 1, and the threshold voltage of the memory cell is greater than the read voltage V. R14 At that time, V R14 The corresponding hard read value is 0; the threshold voltage of the memory cell is less than the read voltage V. R14 When '+△V, V R14 The corresponding soft read value is 1, meaning the threshold voltage of the storage cell is greater than the read voltage V. R14 When '+△V, V R14 The corresponding soft read value is 0. The above V R2 'Corresponding hard read value, V R8 'Corresponding hard read value and V R14 The corresponding hard read value constitutes the hard read value of the low page of the QLC, as mentioned above V R2 'Corresponding soft read value, V R8 'Corresponding soft read value and V R14 The corresponding soft read values ​​constitute the soft read values ​​of the low page of the QLC.

[0149] V R8 The corresponding hard read value is inverted and then compared with V. R2 Perform an OR operation on the corresponding hard-read value, and then combine the above result with V. R14 The corresponding hard read value is ANDed to obtain the hard data. For example, V R2 The corresponding hard read values ​​are A and V. R8 The corresponding hard read value is B, V R14 The corresponding hard read value is C, then the hard data

[0150] V R8 The corresponding soft read value is inverted and then compared with V. R2 Perform an OR operation on the corresponding soft read value, and then combine the above result with V. R14 The corresponding soft read value is ANDed to obtain the soft computed value. For example, V R2 The corresponding soft read values ​​are D and V. R8 The corresponding soft read values ​​are E and V. R14 When the corresponding soft read value is F and the soft compute value is G, the soft compute value is...

[0151] The result of XORing the hard data and the soft computed value is used as the soft data of the lower page of the QLC. That is, soft data SD = hard data HD XOR soft computed value G.

[0152] Figure 16b This diagram illustrates the usage state of the latch in the page buffer during another storage process for reading low-page data of the QLC, as provided in an embodiment of this disclosure. Figure 16b As shown, the page buffer of the QLC includes one main latch DS, one bias latch DL, and four data latches. Figure 16b (D1, D2, D3, and DC in the text). When V R2 After completing the read operation, V R2 The corresponding hard read value is stored in the bias latch DL, and V is... R2 The corresponding soft read value is stored in the first data latch D1. At this time, V... R2 The V obtained after performing the read operation R8 The corresponding prohibition information is stored in the main latch DS. Among them, V R8 The corresponding prohibition information is used to indicate: when using V R8 'When performing a read operation, the threshold voltage on the selected word line is less than the read voltage V.' R2 A read-inhibit voltage is applied to the memory cell.

[0153] When V R8 When performing a read operation, based on V stored in the master latch DS R8 The corresponding prohibition information applies when the threshold voltage on the selected word line is less than the read voltage V. R2 A read-inhibit voltage is applied to the memory cell. When V R8 After the read operation is completed, data Data1' is stored in the bias latch DL, and data Data2' is stored in the data latch D1. Data Data1' is V. R8 'The corresponding hard read value is inverted and summed with V R2 The result of the OR operation on the corresponding hard-read value, for example, V R2 The corresponding hard read values ​​are A and V. R8 The corresponding hard read value is B, then Data2' is V R8 The corresponding soft read value is inverted and summed with V. R2 The result of the OR operation on the corresponding soft read value, for example, V R2 The corresponding soft read values ​​are D and V. R8 The corresponding soft read value is F, then At the same time, it will be based on V R8 The V obtained after performing the read operation R14 The corresponding prohibition information is stored in the main latch DS. Among them, V R14 The corresponding prohibition information is used to indicate: when using V R14'When performing a read operation, the threshold voltage on the selected word line is less than the read voltage V.' R8 A read-inhibit voltage is applied to the memory cell.

[0154] When V R14 When performing a read operation, based on V stored in the master latch DS R14 The corresponding prohibition information applies when the threshold voltage on the selected word line is less than the read voltage V. R8 A read-inhibit voltage is applied to the memory cell. When V R14 After the read operation is completed, the hard data is stored in the bias latch DL, and the soft-computed value is stored in the data latch D1. The hard data consists of the aforementioned data Data1 and V. R14 The result of performing a bitwise AND operation on the corresponding hard-read value, for example, V. R14 When the corresponding hard read value is C, the hard data HD = Data1' & C; the soft calculation value is the aforementioned data Data2' and V. R14 The result of performing a bitwise AND operation on the corresponding soft read value, for example, V R14 When the corresponding soft read value is F and the soft calculation value is G, G = Data2' & F. At this time, the main latch DS still stores V. R14 'Corresponding prohibited information'.

[0155] Then, release the main latch DS, perform an XOR operation between the hard data and the soft computed value to obtain the soft data. For example, if the soft computed value is G, then the soft data SD = HD XOR G, and store the soft data in the main latch DS.

[0156] In some embodiments, after soft data is stored in the main latch DS, hard data is dumped from the bias latch DL to the data latch D3, soft data is dumped from the main latch DS to the data latch DC, and the bias latch DL, data latch D1, and main latch DS are released so that they can be used for reading the next page of data. Alternatively, the hard data can be dumped from the bias latch DL to the data latch D3, the soft data from the main latch DS to the data latch DC, and the bias latch DL, data latch D1, and main latch DS can be released before the read operation of the next logical page of data.

[0157] As described above, when reading QLC low-page data using the memory control method provided in this embodiment, only three read operations are needed to simultaneously obtain hard data and soft data, further reducing the number of read operations. This reduces the word line and bit line setup time required for the read operations, thereby reducing the read time. Furthermore, this disclosure does not require more latches when reading hard and soft data from the QLC low page; only three latches are needed (e.g., ...). Figure 16b The main latch (DS), bias latch (DL), and data latch (D1) are located in the main latch, thus allowing more latches to be reserved for reading data from the next logical page.

[0158] This disclosure also provides a memory, such as... Figure 3 As shown, the memory 300 includes a memory cell array 301 and peripheral circuitry 302. The memory cell array 301 includes multiple memory cells, each configured to store N bits of data, where N is an integer greater than 1. The peripheral circuitry 302 is coupled to the memory cell array 301 and includes a page buffer.

[0159] The peripheral circuit 302 is configured to perform a read operation based on the read voltage corresponding to the target logic page, obtain the hard read value and soft read value of the target logic page, and store the hard read value, soft read value and disable information into three latches in the page buffer respectively; obtain the hard data of the target logic page based on the hard read value of the target logic page; and obtain the soft data of the target logic page based on the hard data and soft read value of the target logic page.

[0160] In some embodiments, the page buffer includes a main latch, a bias latch, and N data latches. The peripheral circuitry is specifically configured to: store a hard read value, a soft read value, and a disable information into the bias latch, a first data latch among the N data latches, and the main latch, respectively; or, store the hard read value, the soft read value, and the disable information into the first data latch among the N data latches, the bias latch, and the main latch, respectively.

[0161] In some embodiments, the peripheral circuitry is further configured to: release the main latch after obtaining hard data; and store soft data in the main latch after obtaining soft data.

[0162] In some embodiments, the peripheral circuitry is further configured to: dump hard data from the bias latch or the first data latch to the second data latch among N data latches, dump soft data from the main latch to the third data latch among N data latches, and release the bias latch, the first data latch, and the main latch.

[0163] In some embodiments, each target logic page corresponds to at least one read voltage; the peripheral circuit is specifically configured to: after applying each read voltage to the memory cell, obtain the hard read value and soft read value corresponding to the read voltage through a first sensing and a second sensing respectively; the sensing time of the first sensing is less than the sensing time of the second sensing.

[0164] In some embodiments, when N is 3, each storage unit is configured to be 2 3One of the storage states stores 3 bits of data; the first to seventh read voltages are used to distinguish between 2. 3 Each storage state.

[0165] In some embodiments, when N is 3, the first logic page of the three logic pages corresponds to the first read voltage and the fifth read voltage; the second logic page of the three logic pages corresponds to the second read voltage, the fourth read voltage and the sixth read voltage; and the third logic page of the three logic pages corresponds to the third read voltage and the seventh read voltage; wherein the first read voltage to the seventh read voltage increases sequentially.

[0166] In some embodiments, when the target logic page is a first logic page, the peripheral circuit is specifically configured to: apply a first read voltage to the memory cell; obtain a first hard read value and a first soft read value through consecutive first sensing and second sensing, respectively; the sensing time of the first sensing is less than the sensing time of the second sensing; apply a fifth read voltage to the memory cell; obtain a second hard read value and a second soft read value through consecutive third sensing and fourth sensing, respectively; the sensing time of the third sensing is less than the sensing time of the fourth sensing; the first hard read value and the second hard read value constitute the hard read value of the first logic page; the first soft read value and the second soft read value constitute the soft read value of the first logic page.

[0167] In some embodiments, the peripheral circuitry is specifically configured to apply hard read voltage and soft read voltage to the memory cell respectively, so as to obtain the hard read value and soft read value of the target logic page respectively.

[0168] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0169] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0170] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A control method of a memory, characterized by, The memory includes a plurality of memory cells, each of which is configured to store N-bit data, where N is an integer greater than 1; the method comprises: performing a read operation based on a read voltage corresponding to a target logical page to obtain a hard read value and a soft read value of the target logical page, and storing the hard read value, the soft read value and the forbidden information into three latches in a page buffer respectively; obtaining hard data of the target logical page based on the hard read value of the target logical page; obtaining soft data of the target logical page based on the hard data and the soft read value of the target logical page.

2. The control method of memory according to claim 1, wherein, The page buffer includes a main latch, a bias latch and N data latches; the storing of the hard read value, the soft read value and the forbidden information into three latches in the page buffer respectively comprises: storing the hard read value, the soft read value and the forbidden information into the bias latch, a first data latch of the N data latches and the main latch respectively; or, storing the hard read value, the soft read value and the forbidden information into a first data latch of the N data latches, the bias latch and the main latch respectively.

3. The control method of memory according to claim 2, wherein, The method further comprises: after obtaining the hard data, releasing the main latch; after obtaining the soft data, storing the soft data into the main latch.

4. The control method of memory according to claim 3, wherein, The method further comprises: dumping the hard data from the bias latch or the first data latch into a second data latch of the N data latches, dumping the soft data from the main latch into a third data latch of the N data latches, and releasing the bias latch, the first data latch and the main latch.

5. The control method of memory according to claim 1, wherein, Each of the target logical pages corresponds to at least one of the read voltages; the performing of the read operation based on a read voltage corresponding to a target logical page to obtain a hard read value and a soft read value of the target logical page comprises: after applying each of the read voltages to the memory cell, obtaining the hard read value and the soft read value corresponding to the read voltage through continuous first sensing and second sensing respectively; the sensing time of the first sensing is less than that of the second sensing.

6. The control method of memory according to claim 1, wherein, N is 3, each of the memory cells is configured to store 3 bits of data in one of 2 3 memory states; and first to seventh read voltages are used to distinguish the 2 3 memory states.

7. The control method of memory according to claim 6, wherein, When N is 3, a first logical page of the three logical pages corresponds to a first read voltage and a fifth read voltage; a second logical page of the three logical pages corresponds to a second read voltage, a fourth read voltage and a sixth read voltage; a third logical page of the three logical pages corresponds to a third read voltage and a seventh read voltage; wherein the first read voltage to the seventh read voltage increases in turn.

8. The control method of memory according to claim 7, wherein, When the target logical page is the first logical page, the performing of the read operation based on a read voltage corresponding to a target logical page to obtain a hard read value and a soft read value of the target logical page comprises: applying the first read voltage to the memory cell; obtaining a first hard read value and a first soft read value through continuous first sensing and second sensing respectively; the sensing time of the first sensing is less than that of the second sensing; applying the fifth read voltage to the memory cell; The second hard read value and the second soft read value are obtained through continuous third sensing and fourth sensing respectively; a sensing time of the third sensing is less than a sensing time of the fourth sensing; The first hard read value and the second hard read value constitute the hard read value of the first logical page; and the first soft read value and the second soft read value constitute the soft read value of the first logical page.

9. The control method of memory according to claim 1, wherein, The reading operation based on the read voltage corresponding to the target logical page comprises: The hard read value and the soft read value of the target logical page are obtained by respectively applying a hard read voltage and a soft read voltage to the memory cell.

10. A memory, comprising: The memory comprises: An array of memory cells, the array of memory cells comprising a plurality of memory cells; each memory cell is configured to store N-bit data, where N is an integer greater than 1; A peripheral circuit coupled to the array of memory cells; the peripheral circuit comprises a page buffer; the peripheral circuit is configured to: Perform a reading operation based on a read voltage corresponding to a target logical page to obtain a hard read value and a soft read value of the target logical page, and store the hard read value, the soft read value and the forbidden information into three latches in the page buffer respectively; Obtain hard data of the target logical page based on the hard read value of the target logical page; Obtain soft data of the target logical page based on the hard data and the soft read value of the target logical page.

11. The memory of claim 10, wherein, The page buffer comprises a main latch, a bias latch and N data latches; the peripheral circuit is specifically configured to: Store the hard read value, the soft read value and the forbidden information into the bias latch, a first data latch of the N data latches and the main latch respectively; Or, store the hard read value, the soft read value and the forbidden information into a first data latch of the N data latches, the bias latch and the main latch respectively.

12. The memory of claim 11, wherein, The peripheral circuit is further configured to: Release the main latch after obtaining the hard data; After obtaining the soft data, store the soft data into the main latch.

13. The memory of claim 12, wherein, The peripheral circuit is further configured to: Dump the hard data from the bias latch or the first data latch to a second data latch of the N data latches, dump the soft data from the main latch to a third data latch of the N data latches, and release the bias latch, the first data latch and the main latch.

14. The memory of claim 10, wherein, Each target logical page corresponds to at least one read voltage; The peripheral circuit is specifically configured to: After applying each read voltage to the memory cell, the hard read value and the soft read value corresponding to the read voltage are obtained through continuous first sensing and second sensing respectively; The sensing time of the first sensing is less than the sensing time of the second sensing.

15. The memory of claim 10, wherein, N is 3, each of the memory cells is configured to store 3 bits of data in one of 2 3 memory states; and first to seventh read voltages are used to distinguish the 2 3 memory states.

16. The memory of claim 15, wherein, When N is 3, a first logical page of the three logical pages corresponds to a first read voltage and a fifth read voltage; a second logical page of the three logical pages corresponds to a second read voltage, a fourth read voltage and a sixth read voltage; and a third logical page of the three logical pages corresponds to a third read voltage and a seventh read voltage; wherein the first read voltage to the seventh read voltage increase sequentially.

17. The memory of claim 16, wherein, When the target logical page is the first logical page, the peripheral circuit is specifically configured to: apply the first read voltage to the storage unit; obtain a first hard read value and a first soft read value through continuous first sensing and second sensing respectively; a sensing time of the first sensing is less than a sensing time of the second sensing; apply the fifth read voltage to the storage unit; obtain a second hard read value and a second soft read value through continuous third sensing and fourth sensing respectively; a sensing time of the third sensing is less than a sensing time of the fourth sensing; the first hard read value and the second hard read value constitute the hard read value of the first logical page; the first soft read value and the second soft read value constitute the soft read value of the first logical page.

18. The memory of claim 10, wherein, The peripheral circuit is specifically configured to: apply a hard read voltage and a soft read voltage to the storage unit respectively to obtain a hard read value and a soft read value of the target logical page.

19. A memory system, comprising: The memory system comprises: at least one memory as claimed in any one of claims 10 to 18; and a controller coupled to the memory. at least one memory as claimed in any one of claims 10 to 18; and a controller coupled to the memory.

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