Apparatus and system for programming data in a non-volatile memory device

Abstract

This application relates to apparatuses and systems for programming data in a non-volatile memory device. A memory device includes a controller that performs a program verify after applying a first program pulse to at least one non-volatile memory cell. The first program pulse is applied during a data program operation and the data program operation includes applying a plurality of program pulses to program multi-bit data into the at least one non-volatile memory cell. The controller also determines a program mode for the at least one non-volatile memory cell based on a result of the program verify and changes at least one of a level of a first control voltage based on the program mode. The first control voltage is applied to a drain select line coupled to the at least one non-volatile memory cell.

Description

TECHNICAL FIELD

[0001] One or more embodiments described herein relate to an apparatus and method for storing or programming data in a non-volatile memory device. BACKGROUND

[0002] Recently, the paradigm for computing environments has shifted to ubiquitous computing, which enables computer systems to be accessed almost anytime and anywhere. Accordingly, the use of portable electronic devices (e.g., mobile phones, digital cameras, notebook computers, etc.) is rapidly increasing. Each of these devices can use or include a memory system having at least one memory device. The memory system can be a data storage device, for example, which can be used as a main storage device or an auxiliary storage device.

[0003] Such a data storage device can include one or more non-volatile semiconductor memories that exhibit improved stability and durability without mechanical driving parts (e.g., a mechanical arm) and thus provide a high data access speed and a relatively low power consumption. Examples of these types of data storage devices include, but are not limited to, universal serial bus (USB) memory devices, memory cards having various interfaces, and solid state drives (SSDs). SUMMARY

[0004] Embodiments described herein also provide an apparatus and method for improving a data input / output speed of a memory device included in a data processing system. Further, according to one embodiment, the data input / output speed can be improved in a process of programming a data item into a non-volatile memory device.

[0005] In one embodiment, a memory device can include a memory structure including at least one non-volatile memory cell configured to store multi-bit data, and a controller configured to perform a program verify after applying a first program pulse to the at least one non-volatile memory cell during a data programming operation, the data programming operation including applying a plurality of program pulses to program the multi-bit data into the at least one non-volatile memory cell and the first program pulse being one of the plurality of program pulses, determine a program mode for the at least one non-volatile memory cell based on a result of the program verify, and change at least one of a level of a first control voltage.

[0006] The memory structure can include a first transistor coupled between the at least one memory cell and a bit line, the first transistor configured to operate in response to a first control voltage applied to a drain select line (DSL); and a second transistor coupled between the at least one memory cell and a source line, the second transistor configured to operate in response to a second control voltage applied to a string select line (SSL). The at least one memory cell is coupled between the first transistor and the second transistor and is configured to store multi-bit data through a plurality of program pulses.

[0007] The at least one memory cell can include N transistors connected in series with each other between the first transistor and the second transistor. The control device can program the multi-bit data into the at least one memory cell in an order of a transistor connected to the first transistor to another transistor connected to the second transistor among the N transistors.

[0008] The control device can be configured to determine a level of the first control voltage in response to a temperature of the memory device, and determine whether to change or adjust the level of the first control voltage in response to a number of program pulses applied to the at least one non-volatile memory cell during a data programming operation.

[0009] The control device can apply a program pulse and perform a program verify corresponding to the program pulse after determining the level of the first control voltage.

[0010] The control device can be configured to compare the number of program pulses applied to the at least one non-volatile memory cell during the data programming operation with a predetermined number of changes or adjustments of the level of the first control voltage, and determine whether to apply an overvoltage drive in response to a comparison result.

[0011] The control device can lower the level of the first control voltage by a predetermined level corresponding to the number of program pulses applied to the at least one non-volatile memory cell during the data programming operation.

[0012] The control device can avoid lowering the level of the first control voltage below a minimum level for operating the transistor connected to the drain select line (DSL).

[0013] The programming mode corresponding to the second programming pulse can be determined to be one selected from among the first mode, the second mode, and the third mode. The first mode is used to apply the second programming pulse to change or adjust the threshold voltage of the at least one nonvolatile memory cell by a first level equal to or greater than the level caused by the first programming pulse. The second mode is used to apply the second programming pulse to change or adjust the threshold voltage of the at least one nonvolatile memory cell by a second level less than the level caused by the first programming pulse. The third mode is used to apply the second programming pulse to the at least one nonvolatile memory cell for which the threshold voltage is prohibited from being changed.

[0014] When the programming mode is the second mode, the control device can change the level of the first control voltage.

[0015] The control device can increase the level of the pass voltage applied to the memory structure, the level of the first control voltage applied to the drain select line (DSL), or the level of the second control voltage applied to the string select line (SSL).

[0016] In one embodiment, a memory system can include a memory device including a plurality of nonvolatile memory cells, and a controller configured to receive a write command and write data from a host, determine a storage location of the write data in the memory device, and transfer the write data to the memory device. During a data programming operation in which a plurality of programming pulses are applied to program the write data to the plurality of nonvolatile memory cells, the memory device can be configured to determine a programming mode that causes a threshold voltage of the plurality of nonvolatile memory cells to change, and to change at least one of a level of a first control voltage.

[0017] The memory device can be configured to determine the level of the first control voltage in response to a temperature of the memory device, and to determine whether to change or adjust the level of the first control voltage in response to a number of programming pulses applied to the at least one nonvolatile memory cell during the data programming operation.

[0018] The memory device can be configured to compare the number of programming pulses applied to the at least one nonvolatile memory cell during the data programming operation with a predetermined number of changes or adjustments of the level of the first control voltage, and to determine whether to apply an overvoltage drive in response to a comparison result.

[0019] A program mode corresponding to the second program pulse is determined to be one selected from among a first mode, a second mode, and a third mode: the first mode is for applying the second program pulse to change or adjust a threshold voltage of the at least one non-volatile memory cell by a first level, the first level being equal to or greater than a level caused by the first program pulse; the second mode is for applying the second program pulse to change or adjust a threshold voltage of the at least one non-volatile memory cell by a second level, the second level being less than the level caused by the first program pulse; and the third mode is for applying the second program pulse to the at least one non-volatile memory cell that is inhibited from changing the threshold voltage. The memory device can be configured to change a potential of a bit line coupled to the plurality of non-volatile memory cells.

[0020] The memory device is configured to change a potential of a bit line coupled to the plurality of non-volatile memory cells.

[0021] The memory device can avoid a level of the first control voltage being lower than a minimum level for operating a transistor connected to a drain select line (DSL).

[0022] The memory device can be configured to increase a level of a pass voltage applied to the memory structure, a level of a first control voltage applied to a drain select line (DSL), or a level of a second control voltage applied to a string select line (SSL).

[0023] In another embodiment, a memory system can include a memory device including a string arranged between a bit line and a common source line and coupled to a voltage supply circuit through a drain select line and at least one word line, the string including a drain select transistor and at least one memory cell in series, the drain select transistor being coupled to the drain select line, the memory cell being coupled to the word line; and a controller coupled to the memory device and configured to control the memory device to perform a program operation on the memory cell, the program operation including a plurality of program loops. The voltage supply circuit can increase a level of a set control voltage to be applied to the drain select line in one or more initial periods among the plurality of program loops.

[0024] The level of the set control voltage can be determined in response to a temperature of the memory device or a number of the plurality of program loops. BRIEF DESCRIPTION OF DRAWINGS

[0025] The description herein makes reference to the accompanying drawings, which hold throughout the several embodiments. Like reference numerals return to like parts throughout the several views of the drawings.

[0026] Figure 1 Embodiments of a memory device are illustrated.

[0027] Figure 2 Embodiments of a data processing system are illustrated.

[0028] Figure 3A and Figure 3B Embodiments of incremental step pulse programming (ISPP) operations are illustrated.

[0029] Figure 4 Embodiments of methods for storing multi-bit data in non-volatile memory cells are illustrated.

[0030] Figure 5 Embodiments of programming operations and verify operations of incremental step pulse programming (ISPP) operations are illustrated.

[0031] Figure 6 Embodiments of programming operations are illustrated.

[0032] Figure 7 Examples of discharge of strings and bit lines during programming operations are illustrated.

[0033] Figure 8 Examples of programming operations that can vary depending on the discharge of strings and bit lines are illustrated.

[0034] Figure 9 Embodiments of methods for controlling the discharge of strings and bit lines are illustrated.

[0035] Figure 10 Embodiments of control methods for drain select lines (DSLs) are illustrated.

[0036] Figure 11 Embodiments of control methods for drain select lines (DSLs) are illustrated.

[0037] Figure 12 Examples of tables for controlling drain select lines (DSLs) are illustrated.

[0038] Figure 13 Embodiments of programming operations are illustrated.

[0039] Figure 14 Embodiments of programming operations are illustrated. DETAILED DESCRIPTION

[0040] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, elements and features of the present disclosure can be configured or arranged differently to form other embodiments, which can be variations of any of the disclosed embodiments.

[0041] In the present disclosure, reference to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “an example embodiment,” “an embodiment,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “alternative embodiments,” and the like is intended to represent that such features are included in one or more embodiments of the present disclosure, but can or can not necessarily be combined in the same embodiment.

[0042] In the present disclosure, the terms “comprise,” “comprising,” “include,” “including,” “contain,” and “containing,” are open-ended. As used in the appended claims, these terms specify the presence of the stated elements but do not preclude the presence or addition of one or more other elements. The terms in the claims do not preclude the device from including additional components (e.g., interface units, circuitry, etc.).

[0043] In the present disclosure, various units, circuits, or other components can be described or claimed as “configured to” perform a task or tasks. In this context, “configured to” means that the block / unit / circuit / component is equipped with a structure (e.g., circuitry) that performs the task(s) during operation. As such, the task(s) can be performed using the structure, irrespective of whether the block / unit / circuit / component is currently operational (e.g., on, activated, etc.). Useful structures for performing the task(s) include, for example, hardware, software, and / or firmware. Where a structure includes software and / or firmware, the structure is configured to perform the task(s) even when the software and / or firmware is not currently executing (e.g., see the discussion below regarding FIG. 6). In one embodiment, a structure includes hardware and / or circuitry that is configured to adapt the structure itself to perform the task(s) during operation. Accordingly, the term “configured to” does not alway imply that the structure is modified to perform the task(s), although this can be the case.

[0044] As used in this disclosure, the term “circuitry” or “logic” refers to all of: (a) hardware-only circuitry implementations (such as implementations in only analog and / or digital circuitry) and (b) combinations of circuits and software (and / or firmware), such as (as applicable): (i) a combination of processor(s) or (ii) portions of processor(s) / software, including digital signal processors, software, and memory that together allow a device, such as a mobile phone or server, to implement various functionalities described herein. This definition of “circuitry” or “logic” applies to all uses of this term in this application, including in any claims. As a further example, as used in this application, the term “circuitry” or “logic” also covers an implementation that includes both a processor (or multiple processors) and memory that work together to implement various functionalities described herein. This definition of “circuitry” or “logic” applies to all uses of this term in this application, including in any claims. As another example, as used in this application, the term “circuitry” or “logic” also encompasses at least one integrated circuit or a portion thereof, for example, an integrated circuit or a portion thereof that is used to implement at least a portion of a data storage device.

[0045] As used herein, the terms “first,” “second,” “third,” etc. are used as labels for nouns that they follow and do not necessarily describe a temporal or chronological order. The terms “first” and “second” are not necessarily used to denote a first value written before a second value. Additionally, although these terms can be used herein to identify various elements, these elements are not limited by these terms. The terms are used to distinguish one element from another. For example, a first circuit can be distinguished from a second circuit.

[0046] Additionally, the term “based on” is used to describe one or more factors to which determination of some element is based. This term is not exclusive, meaning that additional factors can influence the determination. That is, the determination can be based on those factors alone, or based on those factors at least in part. Consider the phrase “determine A based on B.” While B is a factor that affects the determination of A in this case, such a phrase does not exclude determinations of A based on C. In other cases, A can be determined based on B alone.

[0047] Here, an item of data, data item, data entry, or entry of data can be a sequence of bits. For example, a data item can include the contents of a file, a portion of a file, a page in memory, an object in object-oriented programming, a digital message, a digitally scanned image, a portion of a video or audio signal, metadata, or any other entity that can be represented by a sequence of bits. According to an implementation, a data item can include a discrete object. According to another implementation, a data item can include a unit of information within a transmission packet between two different components.

[0048] Embodiments will now be described, by way of example, with reference to the accompanying drawings, in which like reference numerals refer to like elements throughout.

[0049] Embodiments described herein provide a memory system, a data processing system, and methods for operating the memory system and the data processing system. The data processing system can include components and resources such as the memory system and a host, and can dynamically allocate a plurality of data paths for data communication between the components based on usage of the components and resources.

[0050] Figure 1 Embodiments of a memory device 150 including memory cell array circuitry formed in a memory die are illustrated.

[0051] Referring to Figure 1 The memory device 150 can include at least one memory bank 330 having a plurality of cell strings 340. Each cell string 340 can include a plurality of non-volatile memory cells MC0 to MCn-1 connected to a respective one of a plurality of bit lines BL0 to BLm-1. The cell strings 340 are disposed in respective columns of the memory bank 330, and each cell string 340 can include at least one drain select transistor DST and at least one string select transistor (or source select transistor) SST. The non-volatile memory cells MC0 to MCn-1 of each cell string 340 can be connected in series between the drain select transistor DST and the string select transistor SST. Each of the non-volatile memory cells MC0 to MCn-1 can be configured as a multi-level cell (MLC) that stores a data item having a plurality of bits per cell. The cell strings 340 can be electrically connected to respective ones of the bit lines BL0 to BLm-1.

[0052] In one embodiment, the memory bank 330 can include NAND-type flash memory cells MC0 to MCn-1. In another embodiment, the memory bank 330 can be implemented as NOR-type flash memory, hybrid flash memory in which at least two different types of memory cells are mixed or combined, or single-die NAND flash in which a controller is embedded in a single memory chip. In one embodiment, the memory bank 330 can include flash memory cells including a charge-trapping flash (CTF) layer including a conductive floating gate or an insulating layer.

[0053] Figure 2Embodiments of a memory system 110 that can include a memory device 150 are shown. In the present embodiments, a memory group 330 in the memory device 150 can include one or more memory blocks 152, 154, 156. According to embodiments, the memory device 150 can have a two-dimensional (2D) or three-dimensional (3D) structure. For example, each of the memory blocks 152, 154, 156 in the memory device 150 can be implemented as a 3D structure (or a vertical structure). Each of the memory blocks 152, 154, 156 can have a three-dimensional structure extending along first to third directions (e.g., x-axis, y-axis, and z-axis directions).

[0054] The memory group 330 including the plurality of memory blocks 152, 154, 156 can be coupled to a plurality of bit lines BL, a plurality of string selection lines SSL and a plurality of drain selection lines DSL, a plurality of word lines WL, a plurality of dummy word lines DWL (not shown), and a plurality of common source lines CSL. In one embodiment, the memory group 330 can include a plurality of NAND strings NS (e.g., which can correspond to the cell strings 340, respectively). Each NAND string NS can include a plurality of memory cells MC and can be connected to a respective one of the bit lines BL. In addition, a string selection transistor SST of each NAND string NS can be connected to the common source line CSL, and a drain selection transistor DST of each NAND string NS can be connected to the respective bit line BL. In each NAND string NS, the memory cells MC can be arranged between the string selection transistor SST and the drain selection transistor DST.

[0055] Referring to Figure 1 and Figure 2 , the memory device 150 can include a voltage supply circuit 170 that can supply a word line voltage (e.g., one or more predetermined voltages such as a program voltage, a read voltage, and a pass voltage) to a respective one of the word lines according to an operation mode or supply a voltage to a block body (e.g., a well region) in which each memory block including the memory cells MC is formed. In this case, the voltage generation operation of the voltage supply circuit 170 can be performed under the control of the control circuit 180. In addition, the voltage supply circuit 170 can generate a plurality of variable read voltages to distinguish a plurality of data items from each other.

[0056] In response to the control of the control circuit, one of the memory blocks (or sectors) of the memory cell array can be selected, and one of the word lines of the selected memory block can be selected. A word line voltage can be individually supplied to the selected word line and the unselected word line. The voltage supply circuit 170 can include a voltage generation circuit for generating a target voltage having various levels (e.g., refer to Figures 4 to 8 ).

[0057] In one embodiment, the voltage supply circuit 170 can be coupled to a first pin or pad that receives a first supply voltage VCC applied from the outside (e.g., an external device) and a second pin or pad that receives a second supply voltage VPP applied from the external device. The second supply voltage VPP can have a voltage level higher (e.g., twice or more) than that of the first supply voltage VCC. For example, the first supply voltage VCC can have a voltage level of 2.0 V to 5.5 V, and the second supply voltage can have a voltage level of 9 V to 13 V.

[0058] According to an embodiment, the voltage supply circuit 170 can include a voltage generation circuit for generating various levels of target voltages used in the memory bank 330 more quickly. The voltage generation circuit can use the second supply voltage VPP to generate a target voltage that can have a voltage level higher than that of the second supply voltage VPP.

[0059] The memory device 150 can further include a read / write circuit 320 controlled by the control circuit 180. The read / write circuit 320 can operate as a sense amplifier or a write driver according to the operation mode. For example, in a verify operation and a read operation, the read / write circuit 320 can operate as a sense amplifier that reads a data item from the memory cell array. In a program operation, the read / write circuit 320 can operate as a write driver that controls a potential of a bit line according to a data item to be stored in the memory cell array. The read / write circuit 320 can receive a data item to be programmed to the cell array from a page buffer during the program operation. The read / write circuit 320 can drive a bit line based on the input data item. To this end, the read / write circuit 320 can include a plurality of page buffers (PBs) 322, 324, 326, each of which corresponds to each column (or each bit line) or each column pair (or each bit line pair). According to an embodiment, a plurality of latches can be included in each of the page buffers 322, 324, 326.

[0060] The page buffers 322, 324, 326 can be coupled to a data input / output device (e.g., a serialization circuit or a serializer) through a plurality of buses BUS. When each of the page buffers 322, 324, 326 is coupled to the data input / output device through a different bus, a delay that can occur in data transmission from the page buffers 322, 324, 326 can be reduced. For example, each page buffer 322, 324, 326 can perform data transmission without latency.

[0061] According to an embodiment, the memory device 150 can receive a write command, write data, and information (e.g., a physical address) about a location where the write data is to be stored. The control circuit 180 causes the voltage supply circuit 170 to generate a program pulse, a pass voltage, etc. used in a program operation performed in response to the write command, and to generate one or more voltages used in a verify operation performed after the program operation.

[0062] When programming multi-bit data items in the non-volatile memory cells included in the memory bank 330, the error rate can be higher than when storing one-bit data items in the non-volatile memory cells. For example, errors in the non-volatile memory cells can be caused by cell-to-cell interference (CCI). To reduce errors in the non-volatile memory cells, the width (dispersion) of the threshold voltage distribution (corresponding to the data items stored between the non-volatile memory cells) should be reduced.

[0063] To this end, the memory device 150 can perform an incremental step pulse programming (ISPP) operation to effectively narrow the threshold voltage distribution of the non-volatile memory cells. In one embodiment, the memory device 150 can use the ISPP operation for a multi-step program operation. For example, the memory device 150 can divide the program operation into a least significant bit (LSB) program operation and a most significant bit (MSB) operation according to a predetermined order between the non-volatile memory cells or pages.

[0064] According to an embodiment, a device and method can be provided that can reduce a time for discharging a bit line or a channel between application of program pulses in a data programming operation completed by applying a plurality of program pulses to memory cells in a memory device. When the discharging time can be reduced, the speed of a program operation of the memory device can be increased. For example, to discharge a bit line or a channel in the memory device, the memory device can control or adjust a voltage level of a bit line select line or a drain select line (DSL) to avoid a transistor being in a floating state when controlled through the bit line select line or the drain select line (DSL). Because the transistor can be in the floating state, the bit line or the channel can not be properly discharged.

[0065] In an embodiment, the memory device can adjust and change a setup time for adjusting a bit line potential after applying a program pulse to a non-volatile memory cell in the memory device during a unit program operation of the program pulse applied to the memory cell. As a result, a device and method capable of increasing the speed of a program operation and / or improving the efficiency of a program operation can be provided.

[0066] For example, during an operation to apply a plurality of program pulses to a non-volatile memory cell in a memory device (to program the non-volatile memory cell with multi-bit data), the memory device can perform a unit program operation in one of various modes in which a second program pulse is applied after a first program pulse has been applied.

[0067] The modes of the unit program operation can include a first program mode, a second program mode, and a third program mode. In the first program mode, a degree to which data is programmed in response to a second program pulse (e.g., a change or shift in a threshold voltage in the non-volatile memory cell when the second program pulse is applied) can be similar to or greater than a degree to which the data is programmed in response to a first program pulse. In the second program mode, the degree to which the data is programmed in response to the second program pulse is less than the degree to which the data is programmed in response to the first program pulse. In the third program mode, the degree to which the data is programmed in response to the second program pulse is absent (e.g., there is no change or shift in the threshold voltage in the non-volatile memory cell even when the second program pulse is applied). The mode can be implemented based on a potential of a bit line coupled to a target memory cell when a program pulse is applied. If a discharge time can be reduced, the memory device can improve efficiency or speed of a data programming operation by adjusting and varying a setup time for changing or discharging the potential of the bit line.

[0068] According to an embodiment, the memory device can change or adjust a control voltage applied through a bit line select line or a drain select line (DSL) in response to a programming operation environment (e.g., temperature) and regarding a number of applications or a level (or magnitude) of a program pulse applied to a non-volatile memory cell during a data programming operation. Accordingly, the memory device can reduce an operation margin corresponding to each program pulse during a data programming operation by applying a plurality of program pulses to a non-volatile memory cell. This can reduce a time taken to perform a data programming operation.

[0069] Referring again to Figure 2 , the memory device 150 is shown to be included in a data processing system 100. According to an embodiment, the data processing system 100 can include a host 102 interfaced or coupled with a memory system such as the memory system 110. For example, the host 102 and the memory system 110 can be coupled with each other via a data bus, a host cable, etc. to perform data communication.

[0070] The memory system 110 can include a memory device 150 and a controller 130. The memory device 150 and the controller 130 in the memory system 110 can be considered as components or elements physically separated from each other. The memory device 150 and the controller 130 can be connected via at least one data path. For example, the data path can include a channel and / or a lane.

[0071] According to an embodiment, the memory device 150 and the controller 130 can be functionally divided components or elements. Also, according to an embodiment, the memory device 150 and the controller 130 can be implemented in a single chip or in a plurality of chips. The controller 130 can perform a data input / output operation in response to a request input from an external device. For example, when the controller 130 performs a read operation in response to a read request input from an external device, data stored in a plurality of non-volatile memory cells included in the memory device 150 is transferred to the controller 130.

[0072] In Figure 2 , the memory device 150 can include one or more memory blocks 152, 154, 156. The memory blocks 152, 154, 156 can be understood as a group of non-volatile memory cells that remove data together by a single erase operation. The memory blocks 152, 154, 156 can include at least one page, for example, a group of non-volatile memory cells that store data together during a single programming operation and / or output data together during a single read operation. For example, one memory block can include a plurality of pages.

[0073] In an embodiment, the memory device 150 can include a plurality of memory planes or one or more memory dies. According to an embodiment, the memory plane can be considered as a logical or physical partition including at least one memory block, a driving circuit capable of controlling an array of a plurality of non-volatile memory cells, and a buffer that can temporarily store data input to or output from the non-volatile memory cells.

[0074] According to an embodiment, each memory die can include at least one memory plane, and can be understood as a collection of components implemented on a physically distinguishable substrate. Each memory die can be connected to the controller 130 through a data path, and can include an interface that exchanges items and signals of data with the controller 130.

[0075] According to an embodiment, the memory device 150 can include at least one memory block 152, 154, 156, at least one memory plane, or at least one memory die. The internal configuration (for example, as shown) of the memory device 150 can differ according to the performance of the memory system 110. Embodiments of the disclosure are not limited to Figure 1 the above-described configuration.Figure 2 the internal configuration.

[0076] In Figure 2 In one embodiment, the memory device 150 includes a voltage supply circuit 170 that can supply one or more voltages to the memory blocks 152, 154, 156. The voltage supply circuit 170 can include voltage generation circuits to generate target voltages for the memory blocks 152, 154, 156, for example, as described with reference to Figures 4 to 8

[0077] In one embodiment, the voltage supply circuit 170 can supply a read voltage Vrd, a program voltage Vprog, a pass voltage Vpass, or an erase voltage Vers to the non-volatile memory cells included in the memory blocks. For example, during a read operation to read data stored in the non-volatile memory cells in the memory blocks 152, 154, 156, the voltage supply circuit 170 can supply a read voltage Vrd to the selected non-volatile memory cells. During a program operation to store data in the non-volatile memory cells in the memory blocks 152, 154, 156, the voltage supply circuit 170 can supply a program voltage Vprog to the selected non-volatile memory cells. During a read operation or a program operation performed on the selected non-volatile memory cells, the voltage supply circuit 170 can supply a pass voltage Vpass to the unselected non-volatile memory cells. During an erase operation to erase data stored in the non-volatile memory cells in the memory blocks 152, 154, 156, the voltage supply circuit 170 can supply an erase voltage Vers to the memory blocks.

[0078] The memory device 150 can store information regarding the various voltages supplied to the memory blocks 152, 154, 156 based on which operation is performed. For example, when the non-volatile memory cells in the memory blocks 152, 154, 156 can store multi-bit data, a read voltage Vrd can be used that identifies or reads multiple levels of the multi-bit data item. The memory device 150 can include a table having information indicating the read voltage Vrd for the multiple levels corresponding to the multi-bit data item. For example, the table can include bias values stored in a register, each bias value corresponding to a particular level of the read voltage Vrd. The number of bias values for the read voltage Vrd for a read operation can be limited to a predetermined range. Further, in one embodiment, the bias values can be quantized.

[0079] ​The host 102 can include a portable electronic device (e.g., a mobile phone, an MP3 player, a notebook computer, etc.) or a non-portable electronic device (e.g., a desktop computer, a game player, a television, a projector, etc.). According to an embodiment, the host 102 can include a central processing unit (CPU) included in the portable electronic device and the non-portable electronic device.

[0080] The host 102 can include at least one operating system (OS) capable of controlling functions and operations performed in the host 102. The OS can provide interoperability between the host 102 and a user intending to store data in the memory system 110 operatively interfaced with the memory system 110. The OS can support functions and operations corresponding to a request of the user. By way of example, without limitation, the OS can be classified into a general-purpose operating system and a mobile operating system according to mobility of the host 102. The general-purpose operating system can be classified into a personal operating system and an enterprise operating system according to system requirements or a user environment. The enterprise operating system can be specialized to secure and support high-performance computing, as compared with the personal operating system.

[0081] The mobile operating system can undergo services or functions supporting mobility (e.g., a power saving function). The host 102 can include a plurality of operating systems. The host 102 can execute a plurality of operating systems interlocked with the memory system 110 corresponding to a request of the user. The host 102 can transmit a plurality of commands corresponding to the request of the user to the memory system 110, thereby performing operations corresponding to the plurality of commands within the memory system 110.

[0082] The controller 130 can control the memory device 150 in response to a request or a command from the host 102. For example, the controller 130 can perform a read operation to provide data read from the memory device 150 to the host 102 and can perform a write operation (or a program operation) to store data input from the host 102 in the memory device 150. To perform data input / output (I / O) operations, the controller 130 can control and manage internal operations of reading data, programming data, erasing data, etc.

[0083] According to an embodiment, the controller 130 can include a host interface (I / F) 132, a processor 134, an error correction circuit (ECC) 138, a power management unit (PMU) 140, a memory interface (I / F) 142, and a memory 144. As Figure 2 Components in the controller 130 as shown can vary according to structures, functions, operational performance, etc. of the memory system 110.

[0084] For example, the memory system 110 can be implemented with any of various types of storage devices (electrically coupled with the host 102) depending on the protocol of the host interface. Non-limiting examples of suitable storage devices include a solid state drive (SSD), a multimedia card (MMC), an embedded MMC (eMMC), a reduced size MMC (RS-MMC), a micro- MMC, a secure digital (SD) card, a mini-SD, a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a compact flash (CF) card, a smart media (SM) card, a memory stick, and the like. Depending on the implementation of the memory system 110, components can be added to or omitted from the controller 130.

[0085] Each of the host 102 and the memory system 110 can include a controller or an interface for transmitting and receiving signals, data, and the like according to one or more predetermined protocols. For example, the host interface 132 in the memory system 110 can include a device capable of transmitting and receiving signals, data, and the like to and from the host 102.

[0086] The host interface 132 can receive signals, commands (or requests), and / or data input from the host 102. For example, the host 102 and the memory system 110 can transmit and receive data between them using a predetermined protocol. Examples of communication standards, protocols, or interfaces supported by the host 102 and the memory system 110 for transmitting and receiving data include universal serial bus (USB), multimedia card (MMC), parallel advanced technology attachment (PATA), small computer system interface (SCSI), enhanced small disk interface (ESDI), integrated drive electronics (IDE), peripheral component interconnect express (PCIe or PCI-e), serial attached SCSI (SAS), serial advanced technology attachment (SATA), mobile industry processor interface (MIPI), and the like. According to embodiments, the host interface 132 is one layer for exchanging data with the host 102, and is implemented or driven by firmware called a host interface layer (HIL).

[0087] Integrated drive electronics (IDE) or advanced technology attachment (ATA) can be used as one of the interfaces for transmitting and receiving data, and can support data transmission and reception between the host 102 and the memory system 110 using, for example, a cable including 40 wirings connected in parallel. When a plurality of memory systems 110 are connected to a single host 102, the plurality of memory systems 110 can be divided into master and slave using a location or a dip switch to which the plurality of memory systems 110 are connected. The memory system 110 set as master can be used as a master memory device. The IDE (ATA) can include, for example, fast-ATA, ATAPI, or enhanced IDE (EIDE).

[0088] Serial Advanced Technology Attachment (SATA) interface is a serial data communication interface compatible with various ATA standards used with Integrated Drive Electronics (IDE) devices. The 40 wirings in the IDE interface can be reduced to 6 wirings in the SATA interface. For example, the 40 parallel signals of the IDE can be converted into 6 serial signals of the SATA interface. The SATA interface is widely used in the host 102 for data transmission and reception due to its faster data transmission and reception rate and its less resource consumption. The SATA interface can connect up to 30 external devices to a single transceiver included in the host 102. In addition, the SATA interface can support hot plug, which allows an external device to be attached to or detached from the host 102 while data communication between the host 102 and another device is being performed. Thus, the memory system 110 can be connected or disconnected as an additional device (e.g., a Universal Serial Bus (USB) supported device) even while the host 102 is powered on. For example, in the host 102 having an eSATA port, the memory system 110 can be freely attached to or detached from the host 102 like an external hard disk.

[0089] Small Computer System Interface (SCSI) is a serial data communication interface for connecting a computer or a server with other peripheral devices. Compared with other interfaces such as IDE and SATA, SCSI can provide a high transmission speed. In SCSI, the host 102 and at least one peripheral device (e.g., the memory system 110) are connected in series, but data transmission and reception between the host 102 and each peripheral device can be performed through parallel data communication. In SCSI, it is easy to connect or disconnect a device such as the memory system 110 to or from the host 102. SCSI can support connection of 15 other devices to a single transceiver included in the host 102.

[0090] Serial Attached SCSI (SAS) can be understood as a serial data communication version of SCSI. In SAS, the host 102 and a plurality of peripheral devices are connected in series, and data transmission and reception between the host 102 and each peripheral device can be performed in a serial data communication scheme. In addition, SAS can support connection between the host 102 and the peripheral devices through a serial cable instead of a parallel cable to easily manage equipment using SAS and to enhance or improve operation reliability and communication performance. In addition, SAS can support connection of eight external devices to a single transceiver included in the host 102.

[0091] A fast non-volatile memory (NVMe) is an interface based at least on a peripheral component interconnect express (PCIe) that is designed to increase performance and design flexibility of a host 102, server, computing device, etc. equipped with a non-volatile memory system 110. The PCIe can use a slot or a specific cable to connect a computing device (e.g., the host 102) and a peripheral device (e.g., the memory system 110). For example, the PCIe can use a number of pins (e.g., 18 pins, 32 pins, 49 pins, or 82 pins) and at least one lane (e.g., xl, x4, x8, or x16) to achieve high speed data communication of more than hundreds of MB (e.g., 250 MB / s, 500 MB / s, 984.6250 MB / s, or 1969 MB / s) per second. According to an embodiment, the PCIe scheme can achieve a bandwidth of tens to hundreds of gigabits per second. The NVMe can support an operating speed of a non-volatile memory system 110 (such as an SSD) that is faster than a hard disk.

[0092] According to an embodiment, the host 102 and the memory system 110 can be connected through a universal serial bus (USB). The universal serial bus (USB) is an extensible, hot-pluggable, plug-and-play serial interface that can improve a cost-effective standard connection between the host 102 and a peripheral device (e.g., a keyboard, a mouse, a joystick, a printer, a scanner, a storage device, a modem, a video camera, etc.). A plurality of peripheral devices such as the memory system 110 can be coupled to a single transceiver included in the host 102.

[0093] The error correction circuit 138 can correct error bits of data read from the memory device 150 and can include an error correction code (ECC) encoder and an ECC decoder. The ECC encoder can perform error correction encoding on data to be programmed in the memory device 150 in order to generate encoded data to which parity bits are added. The encoded data can be stored in the memory device 150. When the controller 130 reads the data stored in the memory device 150, the ECC decoder can detect and correct error bits contained in the data read from the memory device 150. For example, after performing error correction decoding on the data read from the memory device 150, the error correction circuit 138 determines whether the error correction decoding has been successful and outputs an indication signal (e.g., a correction success signal or a correction failure signal) based on the result of the error correction decoding. The error correction circuit 138 can use parity bits (generated during ECC encoding for data stored in the memory device 150) in order to correct error bits of read data. When the number of error bits is greater than or equal to the number of correctable error bits, the error correction circuit 138 can not correct the error bits but instead can output a correction failure signal indicating that the error bit correction has failed.

[0094] According to embodiments, the error correction circuit 138 can perform error correction operations based on coding modulation. Examples include low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis coded modulation (TCM), block coded modulation (BCM), etc. The error correction circuit 138 can include all circuits, modules, systems, and / or apparatuses for performing error correction operations based on at least one of the above codes. In embodiments, the error correction circuit 138 can include Figure 2 at least some of the components in the controller 130 shown.

[0095] The ECC decoder can perform hard decision decoding or soft decision decoding on data sent from the memory device 150. Hard decision decoding can be understood as one of two methods broadly classified for error correction. Hard decision decoding can include operations to correct erroneous bits, for example, by reading digital data “0” or “1” from a non-volatile memory cell in the memory device 150. Because hard decision decoding deals with binary logic signals, the circuit / algorithm design or configuration can be simpler and the processing speed can be faster compared to soft decision decoding.

[0096] Soft decision decoding can quantize a threshold voltage of a non-volatile memory cell in the memory device 150 by two or more quantized values (e.g., multi-bit data, approximations, analog values, etc.) in order to correct erroneous bits based on the two or more quantized values. The controller 130 can receive two or more letters or quantized values from a plurality of non-volatile memory cells in the memory device 150, and then perform decoding based on information generated by characterizing the quantized values as a combination of information such as conditional probabilities or likelihoods.

[0097] According to embodiments, the ECC decoder can use a low-density parity-check and generator matrix (LDPC-GM) code among methods designed for soft decision decoding. A low-density parity-check (LDPC) code uses an algorithm that can read data values from the memory device 150 in several bits according to reliability, rather than reading simple 1 or 0 as in hard decision decoding, and iteratively repeats the algorithm through message passing to improve the reliability of the values. Then, the values are finally determined as data of 1 or 0. For example, a decoding algorithm using an LDPC code can be understood as a probabilistic decoding. Hard decision decoding, in which values output from a non-volatile memory cell, are decoded as 0 or 1.

[0098] Compared to hard decision decoding, soft decision decoding can determine a value stored in a non-volatile memory unit based on random information. With respect to bit flips, which can be considered as errors that can occur in the memory device 150, soft decision decoding can provide an improved probability of correcting errors and recovering data, as well as providing reliability and stability of the corrected data. LDPC-GM codes can have a scheme in which an inner low-density generator matrix (LDGM) code can be concatenated in series with a high-speed LDPC code.

[0099] According to an embodiment, the ECC decoder can use, for example, a low-density parity-check convolutional code (LDPC-CC) for soft decision decoding. The LDPC-CC can correspond to a scheme using linear-time encoding and pipelined decoding based on variable block length and shift registers.

[0100] According to an embodiment, the ECC decoder can use, for example, a log-likelihood ratio Turbo code (LLR-TC) for soft decision decoding. A log-likelihood ratio (LLR) can be calculated as a non-linear function of a distance between a sampled value and an ideal value. In addition, a Turbo code (TC) can include a simple code (e.g., a Hamming code) in two or three dimensions, and decoding is repeated in a row direction and a column direction to improve reliability of a value.

[0101] A power management unit (PMU) 140 can control power supplied to the controller 130. The PMU 140 can monitor power supplied to the memory system 110 (e.g., a voltage supplied to the controller 130) and supply power to components included in the controller 130. The PMU 140 can not only detect power-on or power-off, but also generate a trigger signal to enable the memory system 110 to back up a current state in an emergency when power supplied to the memory system 110 is unstable. According to an embodiment, the PMU 140 can include a device or component capable of accumulating power that can be used in an emergency.

[0102] The memory interface 142 can serve as an interface for handling commands and data transferred between the controller 130 and the memory device 150, in order to allow the controller 130 to control the memory device 150 in response to a command or request input from the host 102. When the memory device 150 is a flash memory, the memory interface 142 can generate a control signal for the memory device 150 and can process data input to or output from the memory device 150 under the control of the processor 134.

[0103] For example, when the memory device 150 includes a NAND flash memory, the memory interface 142 includes a NAND flash controller (NFC). The memory interface 142 can provide an interface for handling commands and data between the controller 130 and the memory device 150. According to an embodiment, the memory interface 142 can be implemented or driven by firmware called a flash interface layer (FIL) for exchanging data with the memory device 150.

[0104] According to an embodiment, the memory interface 142 can support an open NAND flash interface (ONFi), a toggle mode, etc. for data input / output with the memory device 150. For example, the ONFi can use a data path (e.g., a channel, a lane, etc.) including at least one signal line capable of supporting bidirectional transmission and reception in units of 8-bit or 16-bit data. Data communication between the controller 130 and the memory device 150 can be implemented through at least one interface regarding an asynchronous single data rate (SDR), a synchronous double data rate (DDR), a toggle double data rate (DDR), etc.

[0105] The memory 144 can be used as a working memory of the memory system 110 or the controller 130 while temporarily storing transaction data of operations performed in the memory system 110 and the controller 130. For example, the memory 144 can temporarily store read data output from the memory device 150 in response to a read request from the host 102 before the read data is output to the host 102.

[0106] In addition, the controller 130 can temporarily store write data input from the host 102 in the memory 144 before programming the write data into the memory device 150. When the controller 130 controls operations of the memory device 150 such as a data read operation, a data write or programming operation, a data erase operation, etc., data transmitted between the controller 130 of the memory system 110 and the memory device 150 can be temporarily stored in the memory 144.

[0107] In addition to reading data or writing data, the memory 144 can store information for inputting or outputting data between the host 102 and the memory device 150 (e.g., mapping data, read requests, program requests, etc.). According to an embodiment, the memory 144 can include one or more of a command queue, a program memory, a data memory, a write buffer / cache, a read buffer / cache, a data buffer / cache, a mapping buffer / cache, etc. The controller 130 can allocate some storage space in the memory 144 for components established to perform data input / output operations. For example, a write buffer established in the memory 144 can be used to temporarily store target data undergoing a program operation.

[0108] In an embodiment, the memory 144 can be implemented with volatile memory. For example, the memory 144 can be implemented with static random access memory (SRAM), dynamic random access memory (DRAM), or both. Although Figure 2 Although the memory 144 is exemplified as being disposed within the controller 130, embodiments are not limited thereto. The memory 144 can be located internal or external to the controller 130. For example, the memory 144 can be embodied by external volatile memory having a memory interface that transfers data and / or signals between the memory 144 and the controller 130.

[0109] The processor 134 can control overall operations of the memory system 110. For example, the processor 134 can control a program operation or a read operation of the memory device 150 in response to a write request or a read request entered from the host 102. According to an embodiment, the processor 134 can execute firmware to control the program operation or the read operation in the memory system 110. The firmware can be, for example, a flash translation layer (FTL). According to an embodiment, the processor 134 can be implemented with a microprocessor, a central processing unit (CPU), or another processing device.

[0110] According to an embodiment, the memory system 110 can be implemented with at least one multi-core processor. A multi-core processor is a circuit or chip in which two or more cores, which are considered as distinguished processing regions, are integrated. For example, when a plurality of cores in the multi-core processor independently drive or execute a plurality of flash translation layers (FTLs), a data input / output speed (or performance) of the memory system 110 can be improved. According to an embodiment, data input / output (I / O) operations in the memory system 110 can be independently performed by different cores in the multi-core processor.

[0111] The processor 134 in the controller 130 can perform operations corresponding to requests or commands input from the host 102. Also, the memory system 110 can perform operations independently of commands or requests input from the host 102. In one case, operations performed by the controller 130 in response to requests or commands input from the host 102 can be considered foreground operations, and operations performed by the controller 130 independently of requests or commands input from the host 102 can be considered background operations. The controller 130 can perform foreground or background operations for reading, writing, or erasing data in the memory device 150. In addition, parameter setting operations corresponding to set parameter commands or set feature commands that are set commands sent from the host 102 can be considered foreground operations. As an example of background operations that can be performed without commands sent from the host 102, the controller 130 can perform garbage collection (GC), wear leveling (WL), bad block management for identifying and handling bad blocks, etc.

[0112] According to embodiments, substantially similar operations can be performed as both foreground operations and background operations. For example, when the memory system 110 performs garbage collection in response to requests or commands input from the host 102 (e.g., manual GC), the garbage collection can be considered a foreground operation. When the memory system 110 performs garbage collection independently of the host 102 (e.g., automatic GC), the garbage collection can be considered a background operation.

[0113] When the memory device 150 includes a plurality of dies (or a plurality of chips) each including a plurality of non-volatile memory cells, the controller 130 can perform parallel processing with respect to a plurality of requests or commands input from the host 102 in order to improve performance of the memory system 110. For example, the sent requests or commands can be divided into a plurality of groups including at least some of a plurality of planes, a plurality of dies, or a plurality of chips included in the memory device 150, and the requests or commands of the plurality of groups are processed individually or in parallel in each plane, each die, or each chip.

[0114] The memory interface 142 in the controller 130 can be connected to a plurality of dies or chips in the memory device 150 through at least one channel and at least one lane. When the controller 130 distributes and stores data in a plurality of dies through each channel or each lane in response to a request or command associated with a plurality of pages including non-volatile memory cells, a plurality of operations corresponding to the request or command can be performed simultaneously or in parallel in the plurality of dies or planes. Such a processing method or scheme can be considered an interleaving method. Because the data input / output speed of the memory system 110 is increased by operating in the interleaving method, the data I / O performance of the memory system 110 can be improved.

[0115] By way of example and not limitation, the controller 130 can identify a status of a plurality of channels (or lanes) associated with a plurality of dies included in the memory device 150. The controller 130 can determine a status of each channel or each lane as one of a busy status, a ready status, an active status, an idle status, a normal status, and an abnormal status. The determination by the controller 130 of which channel or lane to deliver instructions (and / or data) through can be associated with a physical block address. The controller 130 can refer to descriptors delivered from the memory device 150. The descriptors can include blocks or pages that describe parameters about certain things with respect to the memory device 150. The descriptors can have a predetermined format or structure. For example, the descriptors can include a device descriptor, a configuration descriptor, a cell descriptor, and the like. The controller 130 can refer to or use the descriptors to determine which channel or lane to exchange instructions or data with.

[0116] As described above, the memory device 150 in the memory system 110 can include one or more memory blocks 152, 154, 156. Each of the memory blocks 152, 154, 156 includes a plurality of non-volatile memory cells. According to an embodiment, the memory blocks 152, 154, 156 can be a group of non-volatile memory cells that are erased together. The memory blocks 152, 154, 156 can include a plurality of pages that are a group of non-volatile memory cells that are read or programmed together.

[0117] In one embodiment, each of the memory blocks 152, 154, 156 can have a high integration three-dimensional stacked structure. Further, the memory device 150 can include a plurality of dies, each of which includes a plurality of planes, each of which includes the memory blocks 152, 154, 156. The configuration of the memory device 150 can vary depending on the performance of the memory system 110.

[0118] In Figure 2 the memory device 150 includes the memory blocks 152, 154, and 156, which can be any memory block of a single-level cell (SLC) memory block, a multi-level cell (MLC) memory block, and the like, based on the number of bits that can be stored in one memory cell. The SLC memory block includes a plurality of pages implemented by memory cells that store one bit of data per memory cell. The SLC memory block can have a higher data I / O operation performance and a higher endurance than the MLC memory block. The MLC memory block includes a plurality of pages implemented by memory cells that store a plurality of bits of data (e.g., two or more bits of data) per memory cell. The MLC memory block can have a greater storage capacity for the same space compared to the SLC memory block. The MLC memory block can be highly integrated from a storage capacity perspective.

[0119] In an embodiment, the memory device 150 can be implemented with MLC memory blocks such as double level cell (DLC) memory blocks, triple level cell (TLC) memory blocks, quad level cell (QLC) memory blocks, and combinations thereof. A DLC memory block can include a plurality of pages implemented by memory cells capable of storing 2 bits of data per memory cell. A TLC memory block can include a plurality of pages implemented by memory cells capable of storing 3 bits of data per memory cell. A QLC memory block can include a plurality of pages implemented by memory cells capable of storing 4 bits of data per memory cell. In another embodiment, the memory device 150 can be implemented with blocks including a plurality of pages implemented by memory cells capable of storing five or more bits of data per memory cell.

[0120] According to an embodiment, the controller 130 can use a MLC memory block included in the memory device 150 as an SLC memory block storing one bit of data in one memory cell. A data input / output speed of a multi-level cell (MLC) memory block can be slower than a data input / output speed of an SLC memory block. For example, when a MLC memory block is used as an SLC memory block, a margin of a read operation or a program operation can be reduced. For example, when a MLC memory block is used as an SLC memory block, the controller 130 can perform a data input / output operation at a higher speed. Accordingly, the controller 130 can use a MLC memory block as an SLC buffer to temporarily store data, as a buffer can require a high data input / output speed to improve performance of the memory system 110.

[0121] According to an embodiment, the controller 130 can program data in a MLC multiple times without performing an erase operation on a particular MLC memory block included in the memory device 150. Generally, a non-volatile memory cell does not support data overwriting. However, the controller 130 can take advantage of a feature of a MLC capable of storing multiple bits of data to program 1 bit of data in a MLC. For a MLC overwriting operation, when 1 bit of data is programmed in a MLC, the controller 130 can store a number of programming times as separate operation information. According to an embodiment, an operation to uniformly level a threshold voltage of a MLC can be performed before another 1 bit of data is programmed in the same MLC which has already stored 1 bit of data.

[0122] In an embodiment, the memory device 150 is implemented as a non-volatile memory such as a flash memory (e.g., a NAND flash memory, a NOR flash memory, etc.). In another embodiment, the memory device 150 can be implemented by at least one of a phase change random access memory (PCRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), and a spin transfer torque magnetic random access memory (STT-MRAM), etc.

[0123] Figure 3A and Figure 3B Embodiments of incremental step pulse programming (ISPP) operations are illustrated.

[0124] Referring to Figure 3A , data can be programmed in non-volatile memory cells in an erased state. When a program pulse is supplied to a word line coupled to the non-volatile memory cells, a threshold voltage distribution of the non-volatile memory cells can be shifted right (e.g., a direction in which threshold voltages increase) from the erased state. If the program pulse is continuously supplied to the non-volatile memory cells, the threshold voltage distribution of the non-volatile memory cells can be continuously shifted right. The program pulse can be supplied until a majority of the plurality of non-volatile memory cells in the threshold voltage distribution have a threshold voltage higher than a target voltage V TARG .

[0125] In Figure 3B , when a program operation starts (operation 212), the memory device 150 can apply a program pulse to a plurality of non-volatile memory cells to which data is to be programmed (operation 214). After applying the program pulse, the memory device 150 can verify whether a majority of the plurality of non-volatile memory cells have a threshold voltage V TARG higher than a target voltage V TH (operation 216). When it is determined according to a verification result FAIL that a majority of the plurality of non-volatile memory cells do not have a threshold voltage V TARG higher than the target voltage V TH , the memory device 150 applies another program pulse to the corresponding non-volatile memory cells (operation 214). When it is determined according to another verification result PASS that a majority of the plurality of non-volatile memory cells have a threshold voltage V TARG higher than the target voltage V TH , the memory device 150 can end the program operation (operation 218).

[0126] To narrow the threshold voltage distribution of the plurality of non-volatile memory cells, it is advantageous to slightly shift the threshold voltage distribution of the plurality of non-volatile memory cells right (e.g., a first amount) when a single program pulse is applied, rather than greatly shift them right (e.g., a second amount greater than the first amount). On the other hand, when the threshold voltage distribution of the plurality of non-volatile memory cells is slightly shifted right, the number of times of applying the program pulse can increase.

[0127] According to an embodiment, as the number of times of applying a program pulse, it can be three times or more of the number of data bits storable in the nonvolatile memory cell. For example, when 2-bit data can be stored in the nonvolatile memory cell, the nonvolatile memory cell can have four program states corresponding to 2-bit data (e.g., "00", "01", "10", and "11"). In order to form a tighter threshold voltage distribution (e.g., a narrower distribution), the extent to which the threshold voltage distribution of the plurality of nonvolatile memory cells is shifted to the right in response to a single program pulse can be less than the difference between two adjacent program states. For example, when two or more program pulses are applied, it can be designed to move by the difference between two adjacent program states. In this case, the number of times of applying a program pulse can be 8 times or more, which is more than 4 times the number of data bits.

[0128] According to an embodiment, the extent to which the threshold voltage distribution of the plurality of nonvolatile memory cells moves when a single program pulse is applied can be understood as a target level. The target level is determined based on the number of times of applying a program pulse. Figure 6 Embodiments of the target level are described in more detail with reference to

[0129] Figure 4 Embodiments of a method for storing multi-bit data in a nonvolatile memory cell are illustrated. Figure 4 The method of can include a program operation performed in a memory device 150 including nonvolatile memory cells each capable of storing 3-bit data.

[0130] Data stored in a nonvolatile memory cell can be distinguished based on the level of the threshold voltage V TH of the corresponding memory cell. The threshold voltage V TH of the memory cell can vary depending on the number of electrons or charges injected into the floating gate of the corresponding memory cell. A single-level cell SLC can be divided into two ranges of threshold voltage V TH to store 1-bit data of "0" or "1". On the other hand, a triple-level cell TLC in the memory device 150 can have eight threshold voltage ranges.

[0131] Reference is made to Figure 4, in order to reduce the number of times of applying a program pulse in an incremental step pulse programming (ISPP) operation, the application of a program pulse applied to a triple-level cell (TLC) in response to data bits stored in the TLC can be controlled differently. The data stored in the TLC can be classified into LSB data, CSB data, and MSB data. The number of times of applying a program pulse can be the smallest in programming the LSB data, and the number of times of applying a program pulse can be greater than the number of times of programming the LSB data in programming the CSB data. The number of times of applying a program pulse can be the greatest in programming the MSB data.

[0132] In a memory device including a triple-level cell (TLC), each physical page can be divided into three logical pages, i.e., an LSB page, a CSB page, and an MSB page. A program pulse applied to each page can be different. For example, different shifts of a positive threshold voltage (V TH ) distribution can be induced in programming the LSB data, the CSB data, and the MSB data. In an embodiment, the threshold voltage V TH of the plurality of nonvolatile memory cells can move the most in programming the LSB page, and the threshold voltage V TH of the plurality of nonvolatile memory cells can move the least in programming the MSB page. According to an embodiment, when the number of times of applying a program pulse is the least in programming the LSB page, a latency time can be the shortest and power consumption can also be the least. On the other hand, in programming the MSB page, the number of times of applying a program pulse can increase, so that the latency time and the power consumption can increase.

[0133] Figure 5 Embodiments of a program voltage application operation and a verify operation of an ISPP operation are illustrated.

[0134] Referring to Figure 5 , after performing a program voltage application operation Pgm during an ISPP operation, the memory device 150 performs a verify operation Ver corresponding to the program voltage application operation Pgm. Each program voltage application operation Pgm can increase the threshold voltage V TH of the nonvolatile memory cell. For example, each program voltage application operation Pgm increases the threshold voltage V TH of the nonvolatile memory cell by a first potential difference ΔV.

[0135] After performing the program voltage application operation Pgm, the threshold voltage V TH of the nonvolatile memory cell can be compared with a verify voltage in the verify operation. When the threshold voltage V THWhen the threshold voltage Vth of the non-volatile memory cell is increased by the programming voltage application operation Pgm, the threshold voltage Vth of the non-volatile memory cell can reach a target voltage (e.g., a verify voltage). When the threshold voltage Vth of the non-volatile memory cell reaches the target voltage, the verify operation Ver can be performed again to determine whether the threshold voltage Vth of the non-volatile memory cell reaches the target voltage. When the threshold voltage Vth of the non-volatile memory cell does not reach the target voltage, the programming voltage application operation Pgm can be performed again to add more electrons to the floating gate of the non-volatile memory cell. Thereafter, the verify operation Ver can be performed in response to the corresponding programming voltage application operation Pgm. The repeated programming voltage application operation Pgm can be performed until the threshold voltage Vth of the non-volatile memory cell reaches the target voltage TH .

[0136] According to embodiments, the number of repetitions of the programming voltage application operation Pgm and the verify operation Ver can vary depending on standby time or latency time, power consumption, accuracy, etc. When the threshold voltage Vth of the non-volatile memory cell is finely increased by the programming voltage application operation Pgm, the accuracy of the programming voltage application operation can be increased. However, as the programming voltage application operation can be performed more times, the latency time and the power consumption can be longer and greater. On the other hand, when the threshold voltage Vth of the non-volatile memory cell is coarsely increased by the programming voltage application operation Pgm, the power consumption of the programming voltage application operation Pgm can be reduced but the operation time can be increased. TH TH The power consumption of the programming voltage application operation Pgm can be increased but the operation time can be shortened as each programming voltage application operation Pgm is greatly increased. The operation time At of the programming voltage application operation Pgm and the verify operation Ver can vary depending on the target (e.g., the change of the threshold voltage Vth) of each programming voltage application operation Pgm. TH

[0137] Referring to Figure 4 and Figure 5 , in a memory device including a triple-level non-volatile memory cell TLC, the programming voltage application operation Pgm and the verify operation Ver can be differently performed based on the purpose and the procedure of programming data in the least significant bit LSB, the center significant bit CSB, and the most significant bit MSB of the memory cell. In Figure 4 , the memory device including the triple-level non-volatile memory cell TLC has been described as an example, but the above-described programming operation can also be applied to a memory device including a quad-level non-volatile memory cell (QLC) for storing 4-bit data, or a non-volatile memory cell capable of storing 5-bit or more data.

[0138] ​​According to embodiments, for each program loop during the ISPP operation, the voltage level of the program pulse applied to the non-volatile memory cell in the program voltage application operation Pgm can be gradually increased by a preset voltage AV. However, the voltage level of the verify pulse applied to the non-volatile memory cell in the verify operation Ver corresponding to the program voltage application operation Pgm can be substantially the same (e.g., not changed). In the verify operation Ver for each program loop, the substantially same verify pulse is applied to the non-volatile memory cell, but the time At for applying the verify pulse can be changed. When the verify operation is performed by reflecting noise generated according to the operating characteristics of the memory device 150, the memory device 150 can change or adjust the voltage level of the verify pulse.

[0139] Figure 6 Embodiments of a program operation in the memory device 150 are illustrated. In Figure 6 , the non-volatile memory cell of the memory device 150 can store a single bit (1-bit) of data, and the memory device 150 can be controlled such that the threshold voltage of the non-volatile memory cell becomes one of an erase state E or a program state P. When the incremental step pulse programming (ISPP) operation is performed as described with reference to Figure 4 and Figure 5 , the threshold voltage of the non-volatile memory cell can be changed from the erase state E to the program state P. In addition, it is noted that, in Figure 5 , the verify operation can be performed after the program pulse is applied.

[0140] With reference to Figure 6 , the verify operation can use two verify voltages Vvfp, Vvfym. For example, a data program operation supporting a double verify program (DPGM) operation can perform the verify operation with two different levels of verify voltage during the verify operation. By using the verify operation with two different verify voltage levels, the degree to which the non-volatile memory cell is programmed in response to the next program pulse can be adjusted. For example, the memory device 150 can determine the amount of change in the threshold voltage that can be caused by the subsequent program pulse.

[0141] According to embodiments, the verify voltage can include a pre-verify voltage Vvfyp and a main verify voltage Vvfym. The main verify voltage Vvfym can be a verify voltage corresponding to a target state of a data program operation. The pre-verify voltage Vvfyp can have a lower level than the main verify voltage Vvfym. In a verify operation, the pre-verify voltage Vvfyp can be used to check the extent to which a data program operation is performed on a non-volatile memory cell. When it is checked through the verify operation (using the main verify voltage Vvfym) that the threshold voltage of the non-volatile memory cell is changed to have the program state P, the non-volatile memory cell does not need to be further programmed through a subsequent program pulse. In addition, when the threshold voltage of the non-volatile memory cell is lower than the pre-verify voltage Vvfyp, the non-volatile memory cell can be programmed through a subsequent program pulse.

[0142] If the threshold voltage of the non-volatile memory cell is in a range between the pre-verify voltage Vvfyp and the main verify voltage Vvfym, the non-volatile memory cell can be programmed too much when normally programmed through a subsequent program pulse (e.g., the threshold voltage of the non-volatile memory cell can be shifted too much to the right, for example, over-programming can occur in this case). Accordingly, the memory device 150 can reduce the amount of change in the threshold voltage. In this case, the memory device 150 can control or adjust the extent to which the non-volatile memory cell is programmed (e.g., the amount of change in the threshold voltage) while a subsequent program pulse is applied.

[0143] In addition, in Figure 6 When a plurality of non-volatile memory cells are programmed through a program pulse and then a verify operation is performed using the pre-verify voltage Vvfyp and the main verify voltage Vvfym, the plurality of non-volatile memory cells can be in three different states MC1, MC2, MC3. For a non-volatile memory cell having a first state MC1 lower than the pre-verify voltage Vvfyp, the memory device 150 can apply a next program pulse to change the threshold voltage of the corresponding memory cell by an amount corresponding to the corresponding program pulse or shift. Such a general program mode (PGM mode) can be referred to as a first program mode.

[0144] On the other hand, if the non-volatile memory cell has a third state MC3 higher than the main verify voltage Vvfym, the memory device 150 can avoid or prohibit further programming of the corresponding memory cell through a subsequent program pulse because the threshold voltage of the non-volatile memory cell has already reached the program state P. In one embodiment, prohibiting the non-volatile memory cell from being additionally programmed can be referred to as a program inhibit mode.

[0145] When the non-volatile memory cell is in the second state MC2, the threshold voltage of the non-volatile memory cell can shift too much when the corresponding non-volatile memory cell is programmed in a first programming mode (PGM mode). Thus, in a second programming mode (DPGM mode) when a subsequent programming pulse is applied, the amount of change in the threshold voltage can be less than that induced in the first programming mode (PGM mode).

[0146] The extent to which the non-volatile memory cell is programmed (e.g., the amount of change in the threshold voltage) can be determined based on the time at which the programming pulse is applied, the number of times the programming pulse is applied, and / or the potential difference between the programming pulses. Although the programming pulses applied to the plurality of non-volatile memory cells connected to a single word line can be the same in some embodiments, the memory device 150 can vary or adjust the amount of change in the threshold voltage for each non-volatile memory cell. To increase the threshold voltage of the plurality of non-volatile memory cells by different amounts, the memory device 150 can vary or adjust the potential of the bit lines connected to the plurality of non-volatile memory cells.

[0147] For example, during the period in which the programming pulse is applied to the word line, a reference (e.g., ground) voltage can be applied to the bit line connected to the first memory cell having a threshold voltage in the first state MC1, but the potential of another bit line connected to the second memory cell having a threshold voltage in the second state MC2 can be higher than the reference (e.g., ground) voltage. Because the potential difference between the word line and the bit line connected to the non-volatile memory cell is smaller, the amount of change in the threshold voltage induced by the programming pulse can be smaller.

[0148] When the potential difference between the word line and the bit line is below a preset level, the non-volatile memory cell will not be programmed. Because the potential difference of the second memory cell having the second state MC2 is less than the potential difference of the first memory cell having the first state MC1, the extent to which the second memory cell is programmed by the subsequent programming pulse can be less than the extent to which the first memory cell is programmed by the subsequent programming pulse.

[0149] Furthermore, even when a subsequent programming pulse is applied to the third memory cell having the third state MC3, a program inhibit voltage can be applied to the bit line coupled to the third memory cell. Because the potential difference between the programming pulse and the program inhibit voltage applied to the third memory cell having the third state MC3 is below a preset level, the third memory cell having the third state MC3 can not be further programmed by the subsequent programming pulse.

[0150] A program mode can be determined according to a verify result corresponding to a program operation performed on a non-volatile memory cell. The program mode can include a first program mode (PGM mode), a second program mode (DPGM mode), and a third program mode (PGM inhibit mode). For example, a verify pass can indicate that the non-volatile memory cell is read as a cut-off cell in response to a verify voltage. A verify fail can indicate that the non-volatile memory cell is read as a pass-through cell in response to the verify voltage. For example, if a threshold voltage of the non-volatile memory cell is lower than the verify voltage (on the left side), the non-volatile memory cell can be read as a pass-through cell. However, if the threshold voltage is equal to or higher than the verify voltage (on the right side), the non-volatile memory cell can be read as a cut-off cell.

[0151] Referring to Figure 6 A non-volatile memory cell whose program mode is the first program mode (PGM mode) can be read as a pass-through cell by both the pre-verify voltage Vvfyp and the main verify voltage Vvfym. Another non-volatile memory cell whose program mode is the second program mode (DPGM mode) can be read as a cut-off cell by the pre-verify voltage Vvfyp and as a pass-through cell by the main verify voltage Vvfym. Another non-volatile memory cell whose program mode is the third program mode (PGM inhibit mode) can be read as a cut-off cell by both the pre-verify voltage Vvfyp and the main verify voltage Vvfym. Also, because the level of the pre-verify voltage Vvfyp is less than the level of the main verify voltage Vvfym, it is not possible for a non-volatile memory cell to be read as a pass-through cell by the pre-verify voltage Vvfyp and as a cut-off cell by the main verify voltage Vvfym.

[0152] Figure 7 Embodiments for discharging strings and bit lines during program operations are illustrated.

[0153] Referring to Figure 7 The memory device 150 can include a string 340 having a plurality of non-volatile memory cells. The string 340 can have a first transistor and a second transistor. The first transistor can be connected to a bit line BL and operate in response to a first control voltage applied through a drain select line DSL. The second transistor can be connected to a source line SL and operate in response to a second control voltage applied through a string select line SSL, and at least one non-volatile memory cell is connected between the first transistor and the second transistor. The at least one non-volatile memory cell can be programmed by a program pulse applied through a word line. Figure 7 The source line SL shown can correspond to Referring to Figure 1The described common source line CSL, the first transistor can correspond to a drain select transistor DST, and the second transistor can correspond to a string select transistor SST. According to an embodiment, the first transistor and / or the second transistor can be implemented as a plurality of transistors connected in series to each other individually.

[0154] As the storage space of the memory device 150 increases, the number of nonvolatile memory cells connected in series between the first transistor and the second transistor can increase. Referring to Figure 7 , multi-bit data can be programmed in a preset order (PGM order) from a nonvolatile memory cell connected to the first transistor to another nonvolatile memory cell connected to the second transistor in sequence.

[0155] The plurality of nonvolatile memory cells in the string 340 can be divided into a programmed nonvolatile memory cell (programmed cell: PGMed Cell) 342 having a programmed state (e.g., P) in Figure 6 and an erased nonvolatile memory cell (erased cell: ERS Cell) 344 in which data is erased to maintain an erased state (e.g., E) in Figure 6 When a next programming operation is performed, a program pulse can be applied to a selected word line Sel_WL connected to a nonvolatile memory cell located next to the programmed nonvolatile memory cell 342.

[0156] A program pulse can be applied to the selected word line Sel_WL to selectively program data into a nonvolatile memory cell connected to the selected word line Sel_WL. After the program pulse is applied, the remaining charge in the string 340 can be removed to perform a verify operation corresponding to the program pulse or a next programming operation corresponding to a subsequent program pulse. To discharge the remaining charge in the bit line BL connected to the string 340, the first transistor can be turned on by a first control voltage applied through the drain select line DSL. When a program pulse is applied to the selected word line Sel_WL, a pass voltage Vpass can be applied to a word line connected to the programmed nonvolatile memory cell 342 to reduce resistance. When the resistance of the channel (DSL channel, MWL channel) is reduced, discharge can occur rapidly in the channel (DSL channel, MWL channel) of the string 340.

[0157] While the programming operation is repeatedly performed, the threshold voltage of the first transistor (operated by the first control voltage applied via the drain selection line DSL) can continue to increase. In this case, the first control voltage applied via the drain selection line DSL can be changed to be higher than a preset voltage in order to turn on the first transistor but lower the resistance of the first transistor so that the charge can be discharged faster. When the first control voltage for discharging applied through the drain selection line DSL is over-voltage driving (OVD), the memory device 150 can perform the programming operation faster than when the first control voltage is not over-driven. The first control voltage for discharging applied through the drain selection line DSL can be a voltage higher than a voltage of the first control voltage for programming applied through the drain selection line DSL. The first control voltage for discharging applied through the drain selection line DSL can be a voltage higher than a voltage of the first control voltage for erasing applied through the drain selection line DSL. Figure 6 The first programming mode, the second programming mode, or the third programming mode corresponding to the programming pulse described in the above can be performed. Through this process, the programming operation speed of the memory device 150 can be improved.

[0158] In Figure 7 In the above, in response to the operation of the first transistor by the first control voltage applied via the drain selection line DSL during the data programming operation, there are three cases: a first state (1) in which the charge is accumulated in the channel of the string 340; a second state (2) in which the charge that is not discharged remains in the channel of the string 340; and a third state (3) in which the charge cannot be discharged when the channel of the string 340 is floating. The three states will be described in more detail with reference to Figure 8 how the three states occur during the data programming operation.

[0159] Figure 8 Embodiments of the programming operation that can be changed according to the discharge of the string and the bit line are exemplified. For example, Figure 8 The discharge of the channel of the string 340 through the first transistor operated by the first control voltage applied via the drain selection line DSL before or at the same time as the programming pulse is applied during the data programming operation is exemplified.

[0160] Referring to Figure 8 When the programming pulse is applied to the selected word line Sel_WL, a pass voltage can be applied to the unselected word line Unsel_WL. Before the programming pulse is applied, the first control voltage and the second control voltage can be separately applied to the drain selection line DSL and the string selection line SSL. Thereafter, when the page buffer control signal PBSENSE is activated, the potential of each bit line BL can be differently maintained.

[0161] As described with reference to Figure 6As described, the page buffer control signal PBSENSE can be activated in response to one of three programming modes. For example, when the programming mode with respect to the nonvolatile memory cell is the first programming mode (PGM mode, general PGM mode, MPGM), the bit line connected to the nonvolatile memory cell is held at a reference (e.g., ground) voltage. When the programming mode is the third mode (PGM inhibit mode), the potential of the bit line can increase by a program inhibit voltage. When the programming mode of the nonvolatile memory cell is the second mode (DPGM), the potential of the bit line can increase over time difference. To reduce the degree of programming data in the nonvolatile memory cell, the potential of the bit line is changed while a program pulse is applied. After the program pulse is applied, the second control voltage applied through the string select line SSL can be deactivated.

[0162] When a data programming operation is performed on the plurality of nonvolatile memory cells 342 included in the string 340, the threshold voltage of the first transistor (operated by the first control voltage applied through the drain select line DSL) can increase. When the level of the pass voltage applied to the unselected word line Unsel_WL after the program pulse is applied exceeds a certain potential (e.g., 4V), the remaining charge in the channel in the string 340 can be discharged.

[0163] Because the discharge does not occur until the level of the pass voltage exceeds the certain potential, the potential of the channel (DPGM operation channel, MPGM operation channel) in the string 340 can continue to increase. To clearly distinguish the degree of programming (e.g., the amount of change in the threshold voltage by the first programming mode and the second programming mode) of the first programming mode and the second programming mode from each other, the discharge of the potential of the channel (DPGM operation channel, MPGM operation channel) in the string 340 can be performed. However, because the discharge does not occur until the potential of the pass voltage exceeds the certain potential. In addition, it can be difficult to discharge the potential of the channel (DPGM operation channel, MPGM operation channel) in the string 340 as the threshold voltage of the first transistor increases, so that the time for discharging the potential can be insufficient.

[0164] Various cases (α, β, γ, δ, ε) according to the discharge rate of the channel potential (DPGM operation channel, MPGM operation channel) in the string 340 will be described as an example. In a first case (α), when the nonvolatile memory cell is programmed in the first programming mode, the potential of the channel (MPGM operation channel) in the string 340 including the corresponding nonvolatile memory cell is slowly discharged. However, in a second case (β), when the nonvolatile memory cell is programmed in the first programming mode, the potential of the channel (MPGM operation channel) in the string 340 including the corresponding nonvolatile memory cell is rapidly discharged.

[0165] In addition, when the non-volatile memory cell is programmed in the second programming mode, the potential of the channel (DPGM operation channel) in the string 340 including the non-volatile memory cell is discharged quickly in the third case (γ) or is discharged slowly in the fourth and fifth cases (δ, ε). Although it can be necessary to discharge the channel potential (DPGM operation channel, MPGM operation channel) so that the potential of the channel corresponds to the ground voltage, the programming operation with the second programming mode can be successfully performed when the potential of the channel is lower than the potential of the bit line BL raised by the page buffer control signal PBSENSE.

[0166] For example, it can be difficult to adjust or change the potential of the bit line BL to control the degree (e.g., the amount of change in the threshold voltage) to which the non-volatile memory cell is programmed in the following cases: the first case (α) when the channel potential (MPGM operation channel) of the string 340 is discharged slowly while the programming operation is performed in the first programming mode; the fourth case (δ) when the channel potential (DPGM operation channel) of the string 340 is discharged slowly while the programming operation is performed in the second programming mode; or the fifth case (ε) when the channel (DPGM operation channel) of the string 340 is floating by the threshold voltage of the transistor connected to the drain select line DSL.

[0167] When the potential of the bit line BL cannot be sufficiently discharged, the degree to which the non-volatile memory cell is programmed is lower than a preset level or a preset amount. Even if the non-volatile memory cell is scheduled to be programmed with the first programming mode or the second programming mode, it can be programmed with the third programming mode (e.g., PGM inhibit mode). In this case, because the non-volatile memory cell is not sufficiently programmed, the memory device 150 can determine that the corresponding non-volatile memory cell is a bad memory cell even if the corresponding non-volatile memory cell is a good (e.g., healthy or normally operating) memory cell.

[0168] According to embodiments, when the memory device 150 overdrives the level of the first control voltage applied via the drain select line DSL, the discharge problem can be solved. Even if the threshold voltage of the first transistor (operated by the first control voltage applied via the drain select line DSL) can inadvertently increase during the programming operation performed on the plurality of non-volatile memory cells 342, the overdrive of the first control voltage can avoid slow discharge. For example, when the potential difference between the first control voltage and the raised threshold voltage of the first transistor is lower than the potential of the bit line BL, the potential of the bit line BL can be increased from the state in which the channel is not fully discharged by the second programming mode. In this case, for example, as described with reference to FIG. 4, because the channel is in a floating state, the second programming mode can not be successfully performed. Figure 7 ​

[0169] As the storage space of the memory device 150 increases, the number of series-connected nonvolatile memory cells included in the string 340 can increase. As the number of nonvolatile memory cells becomes greater, the number of programming operations performed in the string 340 can be greater. Accordingly, it can be reasonable that the threshold voltage of the first transistor included in the string 340 increases according to the number of programming operations. To improve the programming operation, the memory device 150 according to an embodiment is capable of controlling or varying the level of the first control voltage applied via the drain select line DSL in response to the number of times that a program pulse is applied from the string 340.

[0170] Figure 9 Embodiments of a method for controlling discharge of a string and a bit line are illustrated. Specifically, Figure 9 A change in resistance of the programmed nonvolatile memory cell 342 in the string and a change in resistance of the first transistor with respect to a data programming operation of the nonvolatile memory cell connected to the selected word line Sel_WL are described.

[0171] The change in resistance of the programmed nonvolatile memory cell 342 can vary based on the level of a pass voltage Vpass applied to a plurality of word lines MWL connected to the programmed nonvolatile memory cell 342. The change in resistance of the first transistor can vary according to the level of the first control voltage applied via the drain select line DSL.

[0172] Referring to Figure 9 As the level of the pass voltage increases, the resistance of the programmed nonvolatile memory cell 342 can decrease. In addition, as the level of the first control voltage applied via the drain select line DSL increases, the resistance of the first transistor can decrease. Accordingly, when the level of the first control voltage applied via the drain select line DSL increases, the charge of the channel in the string 340 can be sufficiently discharged during a preset operation margin. Thus, the preset operation margin for discharge can be reduced, so that the programming operation can be performed at a faster speed.

[0173] Figure 10 Embodiments of a first control method with respect to a drain select line (DSL) are illustrated.

[0174] Referring to Figure 10 To discharge the charge of the channel of the string 340, the memory device 150 can control the level of the first control voltage applied via the drain select line DSL to be higher than a preset level after the pass voltage Vpass (applied to the unselected word line (Unsel_WL)) exceeds the preset level (e.g., 4V) until the page buffer control signal PBSENSE is activated to perform a second programming mode.

[0175] In this case, when the threshold voltage of the first transistor operated by the first control voltage applied via the drain select line DSL does not increase, it can not be necessary to increase or overdrive the first control voltage above the preset level. Accordingly, in response to the number of programming operations performed in the string 340, the memory device 150 can selectively increase or overdrive the first control voltage applied via the drain select line DSL above the preset level. For example, when the programming pulse is repeatedly applied by the ISPP operation and / or when the programming pulse is applied more than a preset number of times (e.g., last one to five cycles of the programming pulse in the ISPP operation), the first control voltage applied via the drain select line DSL can be overdriven to remain above the preset level (i.e., DSL OVD "on").

[0176] According to embodiments, whether to overdrive the first control voltage applied via the drain select line DSL above the preset level can be determined based on which word line is performed a programming operation from the first transistor in the string 340. For example, as the non-volatile memory cells subjected to the programming operation are closer to the source line SL, the first control voltage applied via the drain select line DSL can be overdriven to remain above the preset level.

[0177] Figure 11 Embodiments regarding a second control method for a drain select line (DSL) are illustrated.

[0178] Referring to Figure 11 To discharge the charge of the channel in the string 340, the memory device 150 can control or maintain the level of the first control voltage applied via the drain select line DSL above the preset level after activating the page buffer control signal PBSENSE until the programming pulse or pass voltage is not applied.

[0179] The discharge rate can depend on the resistance of the string 340. The resistance of the string 340 can vary based on the threshold voltage of the non-volatile memory cell or the first transistor and the temperature inside the memory device 150. For example, as the temperature inside the memory device 150 increases, the resistance of the string 340 can decrease. However, as the temperature decreases, the resistance can increase.

[0180] In addition, as more number of programming pulses are applied during the data programming operation, the temperature of the string 340 in the memory device 150 can increase. Accordingly, the memory device 150 can determine the initial level of the first control voltage applied via the drain select line DSL in response to the temperature at the time when the first programming pulse is applied during the ISPP operation. Then, because the temperature of the string can increase according to the number of times the programming pulse is applied, the memory device 150 can gradually decrease the level of the first control voltage applied via the drain select line DSL.

[0181] However, the level of the first control voltage applied via the drain select line DSL can be maintained to be greater than or equal to a minimum level capable of turning on the first transistor. The degree to which the level of the first control voltage applied via the drain select line DSL (i.e., DSL turn-on voltage) is reduced can be determined based on the operating characteristics of the memory device 150

[0182] According to embodiments, the memory device 150 can store a table regarding the degree to which the level of the first control voltage is reduced from an initial level of the first control voltage applied via the drain select line DSL according to the temperature inside the memory device 150 and / or the number of times of programming pulse application

[0183] Figure 12 An example of a table for controlling a drain select line (DSL) is illustrated. Figure 12 Some of the values shown can show a ratio rather than an absolute value. Embodiments of the present disclosure can not be limited by the values shown in Figure 12 as the values can vary depending on the characteristics of the memory device 150.

[0184] According to embodiments, the control circuit 180 or the voltage supply circuit 170 described with reference to Figure 1 may determine the level of the first control voltage applied via the drain select line DSL based on the table described with reference to Figure 12

[0185] With reference to Figure 12 , the first table [A] can set an initial level of the first control voltage applied to the drain select line DSL (i.e., DSL initial setup) according to the operating environment (e.g., internal temperature) of the memory device 150. For example, the initial level of the first control voltage applied to the string 340 via the drain select line DSL is 1, which is a setting independent of temperature. At -40 degrees Celsius, the level of the first control voltage can be increased by 2.25 times. At 40 degrees Celsius, the level of the first control voltage can be increased by 2.15 times.

[0186] The second table [B] can set how much higher than a preset level to drive the first control voltage applied via the drain select line DSL (i.e., DSL OVD level). For example, the drive level of the first control voltage applied to the string 340 via the drain select line DSL is 1, which is a setting independent of temperature (e.g., the drive level of the first control voltage is equal to the preset level). At -40 degrees Celsius, the first control voltage can be driven to be increased by 2.35 times the preset level. At 40 degrees Celsius, the first control voltage can be driven to be increased by 2.25 times the preset level.

[0187] By Figure 12 ​​The first table [A] and the second table [B] shown, the memory device 150 can adjust or change the level of the first control voltage applied via the drain select line DSL according to the operating environment (e.g., the temperature inside the memory device 150).

[0188] Figure 13 Embodiments of a first program operation of the memory device 150 are illustrated. The first program operation can include receiving a program command and program data from the controller 130 to start the program operation (operation 910) and determining that the program data is completely programmed into the non-volatile memory cells (operation 922, “Yes”) to terminate the program operation (operation 924).

[0189] When the program operation starts, the memory device 150 can determine how much higher the initial level of the first control voltage applied via the drain select line DSL is than the preset level (i.e., DSL OVD level) or whether to change or adjust the level of the first control voltage (i.e., whether to change or adjust the level of the first control voltage) in response to the operating environment (e.g., the temperature inside the memory device 150) (i.e., TEMP) (operation 912). For example, the memory device 150 can determine the level of the first control voltage based on referring to the first table [A] and the second table [B] described above. Figure 12 Figure 12 For example, the memory device 150 can change or adjust the level of the first control voltage, e.g., how much higher the level of the first control voltage is changed from the initial value and / or the preset level.

[0190] ​The memory device 150 can perform the ISPP operation for a data program operation. A plurality of program pulses can be applied to program a data item into the non-volatile memory cell. The operations of applying the program pulse and performing a verify operation corresponding to the applied program pulse can be considered as a cycle or period of the ISPP operation. The memory device 150 can compare a current cycle (pulse cycle) regarding a number of times of applying the program pulse to the non-volatile memory cell with a predetermined cycle value (TM set or set cycle) set for changing or adjusting a level of the first control voltage applied via the drain select line DSL (operation 914). If the current cycle (pulse cycle) is equal to or less than the predetermined cycle value (TM set cycle) (Yes in operation 914), the memory device 150 can perform overdrive of increasing the first control voltage having a level higher than a preset level (i.e., DSL OVD on) (operation 918). On the contrary, if the current cycle (pulse cycle) is greater than the predetermined cycle value (TM set cycle) (No in operation 914), the memory device 150 can not perform overdrive of increasing the first control voltage having a level higher than a preset level (i.e., DSL OVD off) (operation 916). For example, the first control voltage can be overdriven when the number of times of applying the program pulse is greater than a preset value. However, the first control voltage can not be overdriven when the number of times of applying the program pulse is equal to or less than the preset value.

[0191] When the first control voltage applied via the drain select line DSL is determined (operations 918, 916), the memory device 150 can perform a program operation of applying a program pulse (i.e., PGM pulse) and a verify operation (i.e., verify operation) corresponding to the program pulse (operation 920). According to an embodiment, the memory device 150 can perform the program operation and the verify operation based on one of the programming modes described above and / or the ISPP operation according to the program pulse. Figures 3A to 6 The programming mode described above and / or the ISPP operation performs the program operation and the verify operation according to the program pulse.

[0192] After performing the program operation corresponding to the program pulse, the memory device 150 can determine whether data is programmed in the non-volatile memory cell according to a result of the performed verify operation (Yes in operation 922), and then the memory device 150 can terminate the program operation (operation 924). If it is determined that data is not programmed in the non-volatile memory cell according to a result of the verify operation corresponding to the program pulse (No in operation 922), the memory device 150 can perform a next program operation. Before performing the next program operation, the memory device 150 can compare the current cycle (pulse cycle) with the predetermined cycle value (TM set cycle) set for changing or adjusting the first control voltage applied via the drain select line (DSL).

[0193] Figure 14 Embodiments of the second program operation are illustrated. When the memory device 150 receives a program command and program data from the controller 130, the second program operation can be started (operation 810). If the program data is programmed into the non-volatile memory cells (i.e., PGM pass) (“Yes” in operation 820), the second program operation can be terminated (operation 824).

[0194] When the program operation is started, the memory device 150 can determine an initial value of the first control voltage applied via the drain select line DSL in response to an operating environment (e.g., temperature (TEMP)) (operation 812). For example, the memory device 150 can refer to a reference Figure 12 The described first table [A] (e.g., a look-up table (LUT)) determines the initial value of the first control voltage.

[0195] The memory device 150 can compare a current level of the first control voltage applied via the drain select line (DSL level) with a minimum value set for the first control voltage (TM set or establish DSL MIN level) (operation 814). According to embodiments, the memory device 150 can calculate the minimum level of the first control voltage applied via the drain select line DSL (TM set DSL MIN level) in response to an operating environment (e.g., internal temperature) and / or a number of times the program pulse is applied, or the memory device 150 can include a table for storing a preset minimum value (TM set DSL MIN level).

[0196] If the current level of the first control voltage (DSL level) is equal to or less than the minimum value set for the first control voltage (TM set DSL MIN level) (“No” in operation 814), the memory device 150 can adjust or change the current level of the first control voltage (DSL level) based on the operating environment (e.g., internal temperature) and the minimum value corresponding to the number of times the program pulse is applied (operation 816). If the current level of the first control voltage (DSL level) is greater than the minimum value set for the first control voltage (TM set DSL MIN level) (“Yes” in operation 814), the current level of the first control voltage (DSL level) can be used as is (e.g., not changed or adjusted).

[0197] When the level of the first control voltage applied via the drain select line DSL is determined (operations 814, 816), the memory device 150 can perform a program operation (perform PGM pulse) and a verify operation (verify operation) corresponding to the program pulse (operation 818). According to embodiments, the program operation and the verify operation can be performed based on referring to a reference Figures 3A to 6The described multiple programming modes and ISPP operations to perform programming operations and verify operations according to a program pulse.

[0198] After performing the programming operation corresponding to the program pulse, the memory device 150 can determine that the data is programmed in the non-volatile memory cell according to the result of the verify operation (YES in operation 820), so that the memory device 150 can terminate the programming operation (operation 824). When the memory device 150 can determine that the data has not been programmed in the non-volatile memory cell according to the result of the verify operation corresponding to the program pulse (NO in operation 820), the level of the first control voltage applied to the drain select line DSL can be adjusted to a preset level (for example, refer to Figure 11 The described changing level of the first control voltage (i.e., DSL level = DSL level - step) (operation 822).

[0199] After changing the level of the first control voltage applied via the drain select line DSL (operation 822), the memory device 150 can perform the operation 814 of comparing the current level of the first control voltage (DSL level) applied via the drain select line DSL with the minimum value (TM set DSL MIN level) set for the first control voltage.

[0200] Referring to Figure 13 and Figure 14 Before applying the program pulse during the first programming operation and the second programming operation to program the data into the non-volatile memory cell, the memory device 150 can determine the level of the first control voltage applied to the drain select line DSL. Thereafter, the level of the first control voltage applied via the drain select line DSL can be determined to have a certain level with reference to Figure 10 and Figure 11 The described operation timing, the first control voltage applied via the drain select line DSL can be determined to have a certain level. When the first control voltage is applied, the charge in the channel of the string 340 can be discharged.

[0201] According to one or more of the foregoing embodiments, a semiconductor device can program a non-volatile memory cell with data in different modes in response to a program verify result during an incremental step pulse programming (ISPP) operation. During the ISPP operation, the semiconductor device can adjust or change the level of a control voltage applied via a bit line select line or a drain select line (DSL) so that the programming operation speed can be improved.

[0202] Furthermore, one or more embodiments include a semiconductor device that can separate non-volatile memory cells into three groups subject to normal program operation (MPGM), double verify program (DPGM), and program inhibit (PGM inhibit) in response to program verify results during an incremental step pulse programming (ISPP) operation. After determining the applied program pulse based on a program state, the semiconductor device can change or adjust a control voltage level applied to a bit line select line or drain select line (DSL) according to the program pulse and operating environment, thereby reducing the time taken for bit line or channel discharge.

[0203] The methods, processes and / or operations described herein can be executed by code or instructions to be executed by a computer, a processor, a controller, or other signal processing apparatus. The computer, processor, controller, or other signal processing apparatus can be those described herein or others besides. Since the algorithms that form the basis of the methods (or the operations of the computer, processor, controller, or other signal processing apparatus) are detailed, the code or instructions for implementing the operations of the method embodiments can transform the computer, processor, controller, or other signal processing apparatus into a special purpose processor for executing the methods herein.

[0204] Furthermore, another embodiment can include a computer readable medium, such as a non-transitory computer readable medium, for storing the above-described code or instructions. The computer readable medium can be a volatile or non-volatile memory or other storage device which can be removably or fixedly coupled to a computer, processor, controller, or other signal processing apparatus that will execute the code or instructions for executing the operations of the method or device embodiments herein.

[0205] The controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features of the embodiments disclosed herein may, for example, be implemented in non-transitory logic which can include hardware, software, or both. When implemented at least partly in hardware, the controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features can be, for example, any of a variety of integrated circuits, including, but not limited to, application specific integrated circuits, field programmable gate arrays, combinations of logic gates, system on a chip, microprocessors, or other types of processing or control circuits.

[0206] When implemented at least partially in software, the controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features can include, among other things, a memory or other storage for storing code or instructions to be executed by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device can be those described herein or others. Since the algorithms that form the basis of the methods (or operation of the computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments can transform the computer, processor, controller, or other signal processing device into a special purpose processor for performing the methods described herein.

[0207] While the present teachings have been illustrated and described in detail in the drawings and foregoing description, the skilled person will be aware that various changes and modifications can be made without departing from the spirit and scope of the present teachings as defined in the appended claims. Furthermore, the embodiments can be combined to form additional embodiments.

[0208] Cross Reference to Related Applications

[0209] This patent application claims priority to Korean Patent Application No. 10-2021-0083197, filed on June 25, 2021, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device comprising: A memory structure comprising at least one non-volatile memory cell storing multiple bits of data; as well as The controller, the controller: During a data programming operation, programming verification is performed after a first programming pulse is applied to the at least one non-volatile memory cell. The data programming operation includes applying multiple programming pulses to program multiple bits of data into the at least one non-volatile memory cell, and the first programming pulse is one of the multiple programming pulses. Based on the results of the programming verification, a programming mode for the at least one non-volatile memory cell is determined, and Based on the programming mode, at least one of the levels of the first control voltage is changed, wherein the first control voltage is applied to the drain select line DSL associated with the at least one non-volatile memory cell. Wherein, the controller: The level of the first control voltage is determined in response to the temperature of the memory device, and The level of the first control voltage is determined in response to the number of programming pulses applied to the at least one non-volatile memory cell during the data programming operation, and Wherein, the controller: The number of programming pulses applied to the at least one non-volatile memory cell during the data programming operation is compared with a predetermined number of times the level of the first control voltage is changed or adjusted. The decision to apply overvoltage drive is made based on the comparison results.

2. The memory device according to claim 1, wherein, The memory structure includes: A first transistor, connected between the at least one non-volatile memory cell and a bit line, operates in response to a first control voltage applied to the drain select line DSL; and A second transistor, connected between the at least one non-volatile memory cell and the source line, operates in response to a second control voltage applied to the string select line SSL. The at least one non-volatile memory cell is connected between the first transistor and the second transistor and stores the multi-bit data through the plurality of programming pulses.

3. The memory device according to claim 2, wherein, The at least one non-volatile memory cell includes N transistors connected in series between the first transistor and the second transistor, and the controller programs the multi-bit data into the at least one non-volatile memory cell in the order of the transistor connected to the first transistor to the other transistor connected to the second transistor.

4. The memory device according to claim 1, wherein, After determining the level of the first control voltage, the controller applies a programming pulse and performs programming verification corresponding to the programming pulse.

5. The memory device according to claim 1, wherein, The controller reduces the level of the first control voltage to a predetermined level corresponding to the number of programming pulses applied to the at least one non-volatile memory cell during the data programming operation.

6. The memory device according to claim 5, wherein, The controller prevents the level of the first control voltage from falling below the minimum level required to operate the transistor connected to the drain select line DSL.

7. The memory device according to claim 1, wherein, The programming mode corresponding to the second programming pulse is determined to be one of a first mode, a second mode, and a third mode, wherein the first mode is to apply the second programming pulse to change or adjust the threshold voltage of the at least one non-volatile memory cell to a first level, the first level being equal to or greater than the level caused by the first programming pulse; The second mode is to apply the second programming pulse to change or adjust the threshold voltage of the at least one non-volatile memory cell to a second level, which is lower than the level caused by the first programming pulse; The third mode is to apply the second programming pulse to at least one non-volatile memory cell that is prohibited from changing the threshold voltage.

8. The memory device according to claim 7, wherein, When the programming mode is the second mode, the controller changes the level of the first control voltage.

9. The memory device according to claim 1, wherein, The controller increases the level of the pass voltage applied to the memory structure, the level of the first control voltage applied to the drain select line DSL, or the level of the second control voltage applied to the serial select line SSL.

10. A memory system comprising: A memory device comprising a plurality of non-volatile memory cells; as well as The controller receives write commands and write data from the host, determines the storage location of the write data in the memory device, and transmits the write data to the memory device. During a data programming operation that includes applying multiple programming pulses to program the write data into the plurality of non-volatile memory cells, the memory device: Determine the programming mode that causes a change in the threshold voltage of the plurality of non-volatile memory cells, and Based on the programming mode, at least one of the levels of the first control voltage is changed, wherein the first control voltage is to be applied to the drain select line DSL associated with the plurality of nonvolatile memory cells. Wherein, the memory device: The level of the first control voltage is determined in response to the temperature of the memory device, and The level of the first control voltage is determined in response to the number of programming pulses applied to the plurality of non-volatile memory cells during the data programming operation, and Wherein, the memory device: The number of programming pulses applied to the plurality of non-volatile memory cells during the data programming operation is compared with a predetermined number of times the level of the first control voltage is changed or adjusted. The decision to apply overvoltage drive is made based on the comparison results.

11. The memory system according to claim 10, wherein, The programming mode corresponding to the second programming pulse is determined to be one of the first mode, the second mode, and the third mode, wherein the first mode is to apply the second programming pulse to change or adjust the threshold voltage of the plurality of non-volatile memory cells to a first level, which is equal to or greater than the level caused by the first programming pulse; The second mode is to apply the second programming pulse to change or adjust the threshold voltage of the plurality of non-volatile memory cells to a second level, which is lower than the level caused by the first programming pulse; The third mode is to apply the second programming pulse to the plurality of non-volatile memory cells that are prohibited from changing the threshold voltage.

12. The memory system according to claim 11, wherein, The memory device changes the potential of the bit lines connected to the plurality of non-volatile memory cells.

13. The memory system according to claim 10, wherein, The memory device avoids the level of the first control voltage being lower than the minimum level for operating the transistor connected to the drain select line DSL.

14. The memory system of claim 10, wherein, The memory device increases the level of the pass voltage applied to the memory device, the level of the first control voltage applied to the drain select line DSL, or the level of the second control voltage applied to the serial select line SSL.

15. A memory system comprising: A memory device comprising a string disposed between a bit line and a common source line and connected to a voltage supply circuit via a drain select line and at least one word line, the string comprising a drain select transistor connected in series and at least one memory cell, the drain select transistor being connected to the drain select line and the memory cell being connected to the word line; as well as A controller, coupled to the memory device and controlling the memory device to perform programming operations on the memory cells, the programming operations including multiple programming loops, is also included. The voltage supply circuit increases the level of the setting control voltage to be applied to the drain selection line during one or more initial periods of the plurality of programming cycles. Wherein, the controller: The level of the setting control voltage is determined in response to the temperature of the memory device, and The level of the setting control voltage is determined in response to the number of programming pulses applied to the at least one memory cell during the programming operation, and Wherein, the controller: The number of programming pulses applied to the at least one memory cell during the programming operation is compared with a predetermined number of times the level of the setting control voltage is changed or adjusted. The decision to apply overvoltage drive is made based on the comparison results.

16. The memory system according to claim 15, wherein, The level of the control voltage is determined in response to the temperature of the memory device or the number of the plurality of programming cycles.

Images