A Circuit Optimization Method and Device for Meeting Multi-Voltage Operation

Abstract

The present application provides a circuit optimization method for satisfying multi-voltage operation. The method includes: obtaining a plurality of preset circuits that satisfy the principle of circuit function equivalence; obtaining the operating probability, circuit delay, and circuit power consumption of a first preset circuit under various preset voltage conditions, where the first preset circuit is any one of the plurality of preset circuits, and the various preset voltage conditions are a plurality of operating voltages that satisfy the normal operation of the first preset circuit; calculating the product of the circuit power consumption and delay of the first preset circuit according to the operating probability, circuit delay, and circuit power consumption of the first preset circuit under various preset voltage conditions; and determining a preferred circuit from the plurality of preset circuits according to the product of the circuit power consumption and delay of the first preset circuit. Thus, an optimization method is provided for a circuit with a large operating voltage variation range, improving the operating performance of a circuit that satisfies multi-voltage operation.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit design automation, and particularly to a circuit optimization method and device for multi-voltage operation. Background Art

[0002] Traditional circuits with variable operating voltages mostly operate within a relatively small voltage change range, and the circuit operates within a specific voltage range. As the low-power design of circuits increasingly tends to different application scenarios, the requirements for circuit performance and power consumption of the same circuit are different in different application scenarios. By adopting the variable operating voltage strategy, different operating voltages can be selected according to the requirements of circuit performance and power consumption in different application scenarios, which can reduce unnecessary power consumption. However, the circuit performance, power consumption, and robustness of the same circuit structure vary greatly under different operating voltages. Especially when the operating voltage change range is very large, the circuit structure suitable for high-voltage operation may not be suitable for low-voltage operation. Similarly, the circuit structure suitable for low-voltage operation may not be suitable for high-voltage operation.

[0003] Therefore, the traditional circuit optimization method is not applicable to optimizing circuits that operate across regions with a large operating voltage range. There is an urgent need for a new circuit optimization method to solve the optimization problem of multi-voltage operating circuits with a large operating voltage range, so as to improve the operating performance of multi-voltage operating circuits. Summary of the Invention

[0004] In view of this, the present application provides a circuit optimization method and device for multi-voltage operation, which are used to solve the optimization problem of circuits with a large operating voltage change range, so as to improve the operating performance of multi-voltage operating circuits.

[0005] The technical solutions are as follows:

[0006] In a first aspect, an embodiment of the present application provides a circuit optimization method for multi-voltage operation, and the method includes:

[0007] Obtain a plurality of preset circuits, and the plurality of preset circuits satisfy the circuit function equivalence principle;

[0008] Obtain the operating probability, circuit delay, and circuit power consumption of a first preset circuit under various preset voltage conditions, where the first preset circuit is any one of the plurality of preset circuits, and the various preset voltage conditions are a plurality of operating voltages that satisfy the normal operation of the first preset circuit;

[0009] Calculate the circuit power-delay product of the first preset circuit according to the operating probability, circuit delay, and circuit power consumption of the first preset circuit under various preset voltage conditions;

[0010] Determine an optimal circuit from the multiple preset circuits according to the power-delay product of the first preset circuit.

[0011] Optionally, before obtaining the operating probability, circuit delay, and circuit power consumption of the first preset circuit under various preset voltage conditions, the method further includes:

[0012] Optimize the size parameters of the devices in the first preset circuit to obtain an optimized first preset circuit, where the size parameters include at least one of gate length, gate width, and the number of gates, and the circuit delay of the optimized first preset circuit under various preset voltage conditions meets the preset circuit delay design requirements.

[0013] Optionally, the preset circuit delay design requirements include:

[0014] The circuit delay of the optimized first preset circuit under various preset voltage conditions is less than the delay design index corresponding to each of the preset voltage conditions, and the delay margin corresponding to the optimized first preset circuit is the smallest or the relative delay margin corresponding to the optimized first preset circuit is the smallest.

[0015] Optionally, the obtaining the operating probability, circuit delay, and circuit power consumption of the first preset circuit under various preset voltage conditions includes:

[0016] Obtain the operating probability, circuit delay, and circuit power consumption of the optimized first preset circuit under various preset voltage conditions;

[0017] The calculating the power-delay product of the first preset circuit according to the operating probability, circuit delay, and circuit power consumption of the first preset circuit under various preset voltage conditions includes:

[0018] Using the operating probability of the optimized first preset circuit under various preset voltage conditions as weights, calculate the power-delay product of the first preset circuit according to the circuit delay and circuit power consumption of the optimized first preset circuit under various preset voltage conditions.

[0019] Optionally, the obtaining the circuit delay of the first preset circuit under various preset voltage conditions includes:

[0020] Obtain the average circuit delay and the mean square deviation of the circuit delay of the first preset circuit under various preset voltage conditions;

[0021] Calculate the circuit delay according to the average circuit delay and the mean square deviation of the circuit delay of the first preset circuit under various preset voltage conditions.

[0022] Optionally, the method further includes:

[0023] Calculate the robustness value of the first preset circuit according to the working probability and circuit delay of the first preset circuit under each preset voltage condition;

[0024] Determining a preferred circuit from the multiple preset circuits according to the power-delay product of the first preset circuit includes:

[0025] Determine the preferred circuit from the multiple preset circuits according to the power-delay product of the first preset circuit, the robustness value, the preset power-delay product weight, and the preset robustness value weight.

[0026] In a second aspect, an embodiment of the present application provides a circuit optimization device that satisfies multi-voltage operation. The device includes:

[0027] A first acquisition module, configured to acquire a plurality of preset circuits, and the plurality of preset circuits satisfy the circuit function equivalence principle;

[0028] A second acquisition module, configured to acquire the working probability, circuit delay, and circuit power consumption of the first preset circuit under each preset voltage condition, where the first preset circuit is any one of the plurality of preset circuits, and each preset voltage condition is a plurality of operating voltages that satisfy the normal operation of the first preset circuit;

[0029] A first calculation module, configured to calculate the power-delay product of the first preset circuit according to the working probability, circuit delay, and circuit power consumption of the first preset circuit under each preset voltage condition;

[0030] A determination module, configured to determine a preferred circuit from the plurality of preset circuits according to the power-delay product of the first preset circuit.

[0031] Optionally, the device further includes:

[0032] An optimization module, configured to optimize the size parameters of the devices in the first preset circuit before the second acquisition module acquires the working probability, circuit delay, and circuit power consumption of the first preset circuit under each preset voltage condition, to obtain an optimized first preset circuit, where the size parameters include at least one of gate length, gate width, and the number of gates, and the circuit delay of the optimized first preset circuit under each preset voltage condition meets the preset circuit delay design requirements.

[0033] Optionally, the second acquisition module includes:

[0034] The delay acquisition sub-module is used to obtain the average circuit delay value and the mean square deviation of circuit delay of the first preset circuit under various preset voltage conditions; and calculate the circuit delay according to the average circuit delay value and the mean square deviation of circuit delay of the first preset circuit under various preset voltage conditions.

[0035] Optionally, the device further includes:

[0036] A second calculation module, configured to calculate a robustness value of the first preset circuit according to the working probability and the circuit delay of the first preset circuit under various preset voltage conditions;

[0037] The determining module is specifically configured to determine the preferred circuit from the multiple preset circuits according to the circuit power-delay product, the robustness value, the preset circuit power-delay product weight, and the preset robustness value weight of the first preset circuit.

[0038] The above technical solution has the following beneficial effects:

[0039] The embodiment of the present application provides a circuit optimization method for satisfying multi-voltage operation. When executing the method, multiple preset circuits are obtained, and the multiple preset circuits satisfy the circuit function equivalence principle; the working probability, the circuit delay, and the circuit power consumption of the first preset circuit under various preset voltage conditions are obtained, where the first preset circuit is any one of the multiple preset circuits, and the various preset voltage conditions are multiple working voltages that satisfy the normal operation of the first preset circuit; calculate the circuit power-delay product of the first preset circuit according to the working probability, the circuit delay, and the circuit power consumption of the first preset circuit under various preset voltage conditions; determine the preferred circuit from the multiple preset circuits according to the circuit power-delay product of the first preset circuit. Thus, an optimization method is provided for a circuit with a large working voltage change range, and the optimization problem of a circuit with a large working voltage change range is solved to improve the working performance of a circuit that satisfies multi-voltage operation.

[0040] The embodiment of the present application also provides a device corresponding to the above circuit optimization method for satisfying multi-voltage operation, which has the same beneficial effects as the above method. Description of the Drawings

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application, and those of ordinary skill in the art can also obtain other drawings according to the provided drawings without creative efforts.

[0042] Figure 1The simulation diagram of the delay performance of adders with different circuit structures provided by the embodiments of the present application under different voltages;

[0043] Figure 2 The schematic flowchart of a circuit optimization method for multi-voltage operation provided by the embodiments of the present application;

[0044] Figure 3 The schematic diagram of the delay simulation curve of adders with different circuit structures provided by the embodiments of the present application;

[0045] Figure 4 The schematic diagram of the structure of a circuit optimization device for multi-voltage operation provided by the embodiments of the present application. Detailed implementation manners

[0046] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0047] As introduced in the background art, the circuit performance, power consumption, and robustness of the same circuit structure vary greatly under different operating voltages. Especially when the operating voltage change range is large, the circuit structure suitable for higher voltage operation may not be suitable for lower voltage operation. Refer to Figure 1 , which provides the simulation diagrams of the delay performance of adders with three circuit structures under different voltages. Among them, the adders with the three circuit structures are the carry-lookahead adder CLA, the ripple-carry adder RCA, and the sense-amplifier pass-transistor logic adder SAPTL_ADD. It can be seen from Figure 1 that the delay performance of the same circuit structure is different under different operating voltage conditions, and the delay performance of different circuit structures is also different under the same operating voltage conditions.

[0048] How to provide an optimization method for a circuit with a large operating voltage change range to solve the optimization problem of a circuit with a large operating voltage change range and improve the operating performance of a multi-voltage operating circuit. The embodiments of the present application provide a circuit optimization method for multi-voltage operation. Please refer to Figure 2 The schematic flowchart of a circuit optimization method for multi-voltage operation shown, and the method may include:

[0049] Step S100: Obtain a plurality of preset circuits, and the plurality of preset circuits satisfy the circuit function equivalence principle;

[0050] Specifically, multiple preset circuits can be designed based on the principle of equivalent sub - circuit functions, through manual or circuit synthesis design tools, to obtain multiple circuits with the same function, performance meeting the index requirements, different structures / architectures, and capable of operating at multiple voltages.

[0051] For ease of subsequent calculation and explanation, in this embodiment, multiple voltages are represented as M voltages, and multiple circuits are represented as N circuits, where both M and N are positive integers greater than 1.

[0052] It can be understood that for any operating voltage condition among the M voltages, at least one circuit suitable for this operating voltage point can be determined according to the design knowledge database. That is, the M voltages correspond to at least M circuits, and thus the value of M should be greater than or equal to N.

[0053] It should be noted that the circuit synthesis design tools can be, for example, SPICE / PSPICE, EWB, Matlab, SystemView, Multisim, MMICAD, etc. The embodiments of this application do not limit them.

[0054] Step S200: Obtain the working probability, circuit delay, and circuit power consumption of the first preset circuit under each preset voltage condition, where the first preset circuit is any one of the multiple preset circuits, and each preset voltage condition is multiple operating voltages that enable the first preset circuit to work properly.

[0055] Specifically, this step can be achieved by using a circuit synthesis design tool, such as a SPICE circuit simulation tool, to calculate the working probability, circuit delay, and circuit power consumption of the first preset circuit under each preset voltage condition, or it can also be obtained through manual calculation, such as calculation based on device models, Kirchhoff's Current Law (KCL), and Kirchhoff's Voltage Law (KVL).

[0056] It should be noted that the first preset circuit is any one of the multiple preset circuits, and the preset voltage condition is multiple operating voltage conditions that enable the first preset circuit to work properly. It can be understood that the preset voltage condition can be determined according to the design requirements of the preset circuit in the previous steps, since the preset circuit is designed to meet multiple operating voltage conditions.

[0057] For ease of subsequent calculation and explanation, in this embodiment, the working probabilities of the N preset circuits at the M voltages are represented as: p1, p2, p3, … p n ; the circuit delays are represented as: t n,1,delay , t n,2,delay , … t n,i,delay ; the circuit power consumptions are respectively represented as: P n,1 , P n,2 , … P n,i; where n is the nth preset circuit, n = 1, 2, …, N, and i is the ith voltage, i = 1, 2, …, M.

[0058] As an alternative implementation, calculating the circuit delay of the preset circuit in step S200 may include: obtaining the average value and the mean square deviation of the circuit delay of the first preset circuit under various preset voltage conditions; calculating the circuit delay based on the average value and the mean square deviation of the circuit delay of the first preset circuit under various preset voltage conditions; which can be expressed as:

[0059]

[0060] where, is the average value of the circuit delay, is the mean square deviation of the circuit delay, and the value of k is generally not less than 3.

[0061] See Figure 3 shows the simulation curves of the delay data and the probability distribution of the occurrence of the delay data of three circuit structures under the voltage condition of 0.6V, as well as the corresponding circuit delay line segments. It can be seen that the circuit delay values and their corresponding probabilities of the three adder circuits are different, and the magnitude relationship of the calculated circuit delay values is: t delay-SAPTL_ADD < t delay-CLA < t delay-RCA .

[0062] It can be understood that from the perspective of circuit yield, in order to ensure the normal operation of the circuit, the selection of the clock signal frequency is based on the average value of the delay obtained by statistical analysis. Considering its statistical distribution, the circuit delay used to determine the clock signal frequency of the circuit can be set to the sum of the average value of the circuit delay and k times the mean square deviation of the circuit delay. In this way, the accuracy of the obtained circuit delay can be guaranteed. It should be noted that the average value of the circuit delay and the mean square deviation of the circuit delay can be obtained through statistical analysis by a simulation tool.

[0063] Step S300: Calculate the circuit power-delay product of the first preset circuit according to the operating probability, circuit delay, and circuit power consumption of the first preset circuit under various preset voltage conditions;

[0064] Specifically, calculate the circuit power-delay product of the preset circuit according to the operating probability, circuit delay, and circuit power consumption obtained through the foregoing steps, which is expressed as:

[0065] where n = 1, 2, …, N.

[0066] Thus, through PDP nThe power-delay product corresponding to each preset circuit can be calculated. It can be understood that the power-delay product of the circuit reflects the performance of the preset circuit structure under various working voltage conditions.

[0067] Substituting the circuit delay obtained in step S200 into the power-delay product calculation formula of the circuit, we can get:

[0068]

[0069] or

[0070]

[0071] where n = 1, 2, …, N.

[0072] Step S400: Determine the optimal circuit from the multiple preset circuits according to the power-delay product of the first preset circuit.

[0073] Specifically, according to the power-delay products of each preset circuit calculated in the foregoing steps, the circuit with the smallest power-delay product is determined as the optimal circuit from each preset circuit, which is expressed as follows:

[0074] min{PDP1, PDP2, …, PDP n , …, PDP N}.

[0075] Thus, the optimal circuit is determined from each preset circuit through the power-delay product that can reflect the performance of the preset circuit structure under various working voltage conditions. By comprehensively considering the performance of each preset circuit under different working voltage conditions, a circuit optimization method for multi-voltage operation is provided for circuits with a large working voltage change range, improving the performance of circuits that can operate at multiple voltages.

[0076] As an optional implementation manner, before executing step S200 in the embodiments of the present application, the method may further include:

[0077] Optimizing the size parameters of the devices in the first preset circuit to obtain an optimized first preset circuit, where the size parameters include at least one of the gate length, gate width, and number of gates, and the circuit delay of the optimized first preset circuit under each preset voltage condition meets the preset circuit delay design requirements.

[0078] Specifically, after obtaining multiple preset circuits, preprocessing should also be performed on each preset circuit. The preprocessing specifically refers to optimizing the size parameters of the components in the circuit. The size parameters of the components may include at least one of the gate length, gate width, and number of gates.

[0079] It is understandable that the optimized preset circuit obtained by optimizing the size parameters of the components of the preset circuit should have improved circuit delay characteristics under various operating voltage conditions. Specifically, the circuit delay of the optimized first preset circuit under various preset voltage conditions meets the preset circuit delay design requirements.

[0080] It should be noted that the size parameters of the components in the circuit will affect circuit performance parameters such as the threshold voltage, propagation delay, and current driving ability of the components. By optimizing the size parameters of the components in the preset circuit, each preset circuit can be the optimal circuit structure scheme for subsequent optimization selection, avoiding interference from the size parameters of circuit components on the actual implementation of the circuit optimization scheme, and improving the accuracy of the circuit optimization method.

[0081] As an optional implementation manner, the preset circuit delay design requirements include: the circuit delay of the optimized first preset circuit under various preset voltage conditions is less than the delay design index corresponding to each of the preset voltage conditions, and the delay margin corresponding to the optimized first preset circuit is the smallest or the relative delay margin corresponding to the optimized first preset circuit is the smallest.

[0082] Specifically, the circuit delay of the optimized circuit under various preset voltage conditions is less than the delay design index t i,spec , i = 1, 2,..., M. It should be noted that the delay design index t i,spec corresponding to each preset voltage condition can be set by the staff according to the circuit design standard, or can be obtained by the electronic design automation (EDA) software tool through upper-layer design optimization calculation. This embodiment does not limit the determination method of the delay design index.

[0083] In this embodiment, the delay margin corresponding to the optimized first preset circuit can be expressed as:

[0084]

[0085] Or

[0086]

[0087] Where t i,spec is the delay design index corresponding to the i-th voltage condition, and t n,i,delay < t i,spec .

[0088] In this embodiment, the relative delay margin corresponding to the optimized first preset circuit can be expressed as:

[0089]

[0090] or

[0091]

[0092] wherein, t i,spec is the delay design index corresponding to the i-th voltage condition, t n,i,delay < t i,spec .

[0093] Substituting the circuit delay calculated in step S200 into the delay margin, we get:

[0094]

[0095] or

[0096]

[0097] Substituting the circuit delay calculated in step S200 into the relative delay margin, we get:

[0098]

[0099] or

[0100]

[0101] wherein,

[0102] From the above, the optimization process of the preset circuit enables the subsequent comparison of each preset circuit to be based on the best-case scenario of each preset circuit after size optimization for the delay target, avoiding the interference of circuit element size parameters on the actual execution of the circuit optimization scheme, and improving the accuracy of the circuit optimization method.

[0103] As an optional implementation manner, after the optimization process of the size parameters of the components in the preset circuit, in step S200 of the embodiment of the present application, the obtaining of the working probability, circuit delay, and circuit power consumption of the first preset circuit under each preset voltage condition may include:

[0104] Step S201: Obtain the working probability, circuit delay, and circuit power consumption of the optimized first preset circuit under each preset voltage condition;

[0105] Step S202: The calculating of the circuit power-delay product of the first preset circuit according to the working probability, circuit delay, and circuit power consumption of the first preset circuit under each preset voltage condition includes:

[0106] Step S203: Using the operating probabilities of the optimized first preset circuit under various preset voltage conditions as weights, calculate the power-delay product of the first preset circuit according to the circuit delay and circuit power consumption of the optimized first preset circuit under various preset voltage conditions.

[0107] As described above, calculating the power-delay product of the preset circuit based on the optimized preset circuit can avoid the interference of circuit element size parameters on the actual implementation of the circuit optimization scheme and improve the accuracy of the circuit optimization method.

[0108] As an optional implementation manner, the method may further include: calculating a robustness value of the first preset circuit according to the operating probabilities and circuit delays of the first preset circuit under various preset voltage conditions;

[0109] Specifically, calculating the robustness value of the preset circuit according to the operating probabilities and circuit delays of the preset circuit under various voltage conditions, where the robustness value represents the error resistance ability and anti-interference ability of the preset circuit, and can be expressed as:

[0110]

[0111] Or

[0112]

[0113] where n = 1, 2, …, N, is the average value of circuit delays, is the mean square deviation of circuit delays, and p i is the operating probability of the preset circuit under various voltage conditions.

[0114] Based on the obtained robustness value of the preset circuit, step S400 in the embodiments of the present application may include: determining the optimal circuit from the multiple preset circuits according to the power-delay product, robustness value, preset power-delay product weight, and preset robustness value weight of the first preset circuit.

[0115] It can be understood that the determination of the optimal circuit not only considers the preset power-delay product but also considers the robustness value parameter of the preset circuit, that is, considers the anti-interference and error resistance abilities of the circuit, making the determination of the optimal circuit more objective and accurate.

[0116] It should be noted that in the embodiments of the present application, the preferred circuit can also be determined only by the robustness parameter of the preset circuit, that is, step S400 includes: determining the preferred circuit from the multiple preset circuits according to the robustness of the first preset circuit. The parameters specifically considered for determining the preferred circuit can be set by those skilled in the art according to the circuit function requirements, and can be determined by the circuit power-delay product of the preset circuit, can be determined by the circuit robustness of the preset circuit, or can be jointly determined by combining the circuit power-delay product of the preset circuit and the circuit robustness of the preset circuit.

[0117] Specifically, the robustness of multiple preset circuits can be expressed as:

[0118] min{Robustness1,Robustness2,…,Robustness n ,…,Robustness N}

[0119] Determining the preferred circuit from the multiple preset circuits according to the circuit power-delay product, robustness, preset circuit power-delay product weight, and preset robustness weight of the first preset circuit can be achieved by setting the optimization objective function Obj of the circuit corresponding to preset circuit n n as the minimum value obtained by adjusting the circuit device size, expressed as:

[0120]

[0121] or

[0122]

[0123] where the set circuit power-delay product reference value PDP ref and the reference robustness Robustness ref , and their respective weights are w PDP and w robust . It can be understood that PDP ref and Robustness ref and the corresponding weights w PDP and w robust are set by those skilled in the art according to experience and different functional circuit structures, and the present embodiment does not limit them.

[0124] Select the preset circuit corresponding to the minimum value of Obj1, Obj2, …, Obj n , …, Obj N as the preferred circuit, that is:

[0125] minimize{Obj1, Obj2, …, Obj n , …, ObjN}

[0126] Therefore, the determination of the optimal circuit not only considers the preset circuit power-delay product, but also considers the robustness value parameter of the preset circuit, that is, the anti-interference and anti-error capabilities of the circuit, making the determination of the optimal circuit more objective and accurate.

[0127] In summary, the embodiment of the present application provides a circuit optimization method for multi-voltage operation. When executing the method, multiple preset circuits are obtained, and the multiple preset circuits satisfy the circuit function equivalence principle; the working probability, circuit delay, and circuit power consumption of the first preset circuit under each preset voltage condition are obtained, where the first preset circuit is any one of the multiple preset circuits, and each preset voltage condition is a plurality of working voltages that satisfy the normal operation of the first preset circuit; the circuit power-delay product of the first preset circuit is calculated according to the working probability, circuit delay, and circuit power consumption of the first preset circuit under each preset voltage condition; the optimal circuit is determined from the multiple preset circuits according to the circuit power-delay product of the first preset circuit. Therefore, an optimization method is provided for a circuit with a large working voltage change range, solving the optimization problem of a circuit with a large working voltage change range to improve the working performance of a multi-voltage operation circuit.

[0128] Corresponding to the above method, the embodiment of the present application further provides a circuit optimization device for multi-voltage operation. Please refer to Figure 4 , which shows a schematic structural diagram of the device, and may include: a first acquisition module 401, a second acquisition module 402, a first calculation module 403, and a determination module 404, where,

[0129] The first acquisition module 401 is configured to acquire multiple preset circuits, and the multiple preset circuits satisfy the circuit function equivalence principle;

[0130] The second acquisition module 402 is configured to acquire the working probability, circuit delay, and circuit power consumption of the first preset circuit under each preset voltage condition, where the first preset circuit is any one of the multiple preset circuits, and each preset voltage condition is a plurality of working voltages that satisfy the normal operation of the first preset circuit;

[0131] The first calculation module 403 is configured to calculate the circuit power-delay product of the first preset circuit according to the working probability, circuit delay, and circuit power consumption of the first preset circuit under each preset voltage condition;

[0132] The determination module 404 is configured to determine the optimal circuit from the multiple preset circuits according to the circuit power-delay product of the first preset circuit.

[0133] As a preferred embodiment, the device further includes:

[0134] An optimization module 405, configured to optimize the size parameters of the devices in the first preset circuit before the second acquisition module acquires the operating probability, circuit delay, and circuit power consumption of the first preset circuit under various preset voltage conditions, so as to obtain an optimized first preset circuit, where the size parameters include at least one of gate length, gate width, and the number of gates, and the circuit delay of the optimized first preset circuit under various preset voltage conditions meets the preset circuit delay design requirements.

[0135] As a preferred embodiment, the preset circuit delay design requirements include: the circuit delay of the optimized first preset circuit under various preset voltage conditions is less than the delay design index corresponding to each of the preset voltage conditions, and the delay margin corresponding to the optimized first preset circuit is the smallest or the relative delay margin corresponding to the optimized first preset circuit is the smallest.

[0136] As a preferred embodiment, the first calculation module 403 is specifically configured to: acquire the operating probability, circuit delay, and circuit power consumption of the optimized first preset circuit under various preset voltage conditions;

[0137] The first calculation module 403 is specifically configured to calculate the power-delay product of the first preset circuit based on the operating probability of the optimized first preset circuit under various preset voltage conditions as weights and the circuit delay and circuit power consumption of the optimized first preset circuit under various preset voltage conditions.

[0138] As a preferred embodiment, the second acquisition module 402 includes:

[0139] A delay acquisition sub-module 4021, configured to acquire the average circuit delay and the mean square deviation of the circuit delay of the first preset circuit under various preset voltage conditions; calculate the circuit delay based on the average circuit delay and the mean square deviation of the circuit delay of the first preset circuit under various preset voltage conditions.

[0140] As a preferred embodiment, the device further includes:

[0141] A second calculation module 406, configured to calculate the robustness value of the first preset circuit according to the operating probability and the circuit delay of the first preset circuit under various preset voltage conditions;

[0142] The determination module 404 is specifically configured to determine the preferred circuit from the multiple preset circuits according to the power-delay product of the first preset circuit, the robustness value, the preset power-delay product weight, and the preset robustness value weight.

[0143] In summary, the embodiment of the present application provides a circuit optimization device for multi-voltage operation, including: a first acquisition module for acquiring a plurality of preset circuits that satisfy the principle of circuit function equivalence; a second acquisition module for acquiring the working probability, circuit delay, and circuit power consumption of a first preset circuit under various preset voltage conditions, where the first preset circuit is any one of the plurality of preset circuits, and the various preset voltage conditions are a plurality of working voltages that satisfy the normal operation of the first preset circuit; a first calculation module for calculating the power-delay product of the first preset circuit according to the working probability, circuit delay, and circuit power consumption of the first preset circuit under various preset voltage conditions; and a determination module for determining a preferred circuit from the plurality of preset circuits according to the power-delay product of the first preset circuit. Thus, the device provided in this embodiment can provide an optimization method for a circuit with a large working voltage change range, solve the optimization problem of a circuit with a large working voltage change range, and improve the working performance of a multi-voltage operation circuit.

[0144] It should be noted that the steps and related technical features executed by each module in the circuit optimization device for multi-voltage operation provided in the embodiment of the present application correspond to those of a circuit optimization method for multi-voltage operation provided in the embodiment of the application. The description of the device part can refer to the embodiment of the foregoing method part, and will not be elaborated here.

[0145] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other.

[0146] Those skilled in the art can understand that the flowchart shown in the figure is only an example in which the embodiments of the present application can be implemented, and the scope of application of the embodiments of the present application is not limited by any aspect of this flowchart.

[0147] In several embodiments provided by the present application, it should be understood that the disclosed methods, devices, and equipment can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection can be through some communication interfaces. The indirect coupling or communication connection of the device or unit can be in an electrical, mechanical, or other form.

[0148] The unit described as a separation component may or may not be physically separated. The component shown as a unit may or may not be a physical unit, that is, it may be located in one place or may be distributed across multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, in each embodiment of the present application, each functional unit can be integrated into a processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit.

[0149] If the above-mentioned function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0150] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments shown herein, but rather will be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A circuit optimization method for multi-voltage operation, characterized in that Including: Obtain a plurality of preset circuits, where the plurality of preset circuits satisfy the principle of equivalent circuit functions; Obtain the working probability, circuit delay, and circuit power consumption of a first preset circuit under various preset voltage conditions, where the first preset circuit is any one of the plurality of preset circuits, and the various preset voltage conditions are a plurality of operating voltages that satisfy the normal operation of the first preset circuit; Calculate the power-delay product of the first preset circuit according to the working probability, circuit delay, and circuit power consumption of the first preset circuit under various preset voltage conditions, including: ; where n = 1, 2, …, N; i = 1, 2, …, M; where is the operating probability of the nth preset circuit at the ith voltage, is the circuit power consumption of the nth preset circuit at the ith voltage, is the circuit delay of the nth preset circuit at the ith voltage; Determine a preferred circuit from the plurality of preset circuits according to the power-delay product of the first preset circuit; Calculate the robustness value of the first preset circuit according to the working probability and circuit delay of the first preset circuit under various preset voltage conditions, including: = ， Or, ; where n = 1, 2, …, N, is the average circuit delay, is the mean square deviation of the circuit delay, is the operating probability of the nth preset circuit at the ith voltage; The step of determining a preferred circuit from the plurality of preset circuits according to the power-delay product of the first preset circuit includes: determining the preferred circuit from the plurality of preset circuits according to the power-delay product of the first preset circuit, the robustness value, a preset power-delay product weight, and a preset robustness value weight.

2. The method according to claim 1, wherein Before obtaining the working probability, circuit delay, and circuit power consumption of the first preset circuit under various preset voltage conditions, the method further includes: Optimize the size parameters of the devices in the first preset circuit to obtain an optimized first preset circuit, where the size parameters include at least one of the gate length, gate width, and number of gates, and the circuit delay of the optimized first preset circuit under various preset voltage conditions meets the preset circuit delay design requirements.

3. The method according to claim 2, wherein The preset circuit delay design requirements include: The circuit delay of the optimized first preset circuit under various preset voltage conditions is less than the delay design index corresponding to each of the preset voltage conditions, and the delay margin corresponding to the optimized first preset circuit is the smallest or the relative delay margin corresponding to the optimized first preset circuit is the smallest.

4. The method according to claim 3, characterized in that, The step of obtaining the working probability, circuit delay, and circuit power consumption of the first preset circuit under various preset voltage conditions includes: Obtain the working probability, circuit delay, and circuit power consumption of the optimized first preset circuit under various preset voltage conditions; The step of calculating the power-delay product of the first preset circuit according to the working probability, circuit delay, and circuit power consumption of the first preset circuit under various preset voltage conditions includes: Using the working probability of the optimized first preset circuit under various preset voltage conditions as a weight, calculate the power-delay product of the first preset circuit according to the circuit delay and circuit power consumption of the optimized first preset circuit under various preset voltage conditions.

5. The method according to claim 1, characterized in that, The step of obtaining the circuit delay of the first preset circuit under various preset voltage conditions includes: Obtain the average value and variance of the circuit delay of the first preset circuit under various preset voltage conditions; Calculate the circuit delay according to the average value and variance of the circuit delay of the first preset circuit under various preset voltage conditions.

6. A circuit optimization device for multi-voltage operation, characterized in that, The device includes: The first acquisition module is configured to acquire a plurality of preset circuits, and the plurality of preset circuits satisfy the principle of equivalent circuit functions; The second acquisition module is configured to acquire the working probability, circuit delay, and circuit power consumption of the first preset circuit under various preset voltage conditions, where the first preset circuit is any one of the plurality of preset circuits, and the various preset voltage conditions are a plurality of working voltages that satisfy the normal operation of the first preset circuit; The first calculation module is configured to calculate the power-delay product of the first preset circuit according to the working probability, circuit delay, and circuit power consumption of the first preset circuit under various preset voltage conditions; The first calculation module specifically calculates the power-delay product of the first preset circuit based on the following formula: ; where n = 1, 2, …, N; i = 1, 2, …, M; where is the operating probability of the nth preset circuit at the ith voltage, is the circuit power consumption of the nth preset circuit at the ith voltage, is the circuit delay of the nth preset circuit at the ith voltage; The determination module is configured to determine a preferred circuit from the plurality of preset circuits according to the power-delay product of the first preset circuit; The second calculation module is configured to calculate the robustness value of the first preset circuit according to the working probability and circuit delay of the first preset circuit under various preset voltage conditions; The second calculation module specifically calculates the robustness value of the first preset circuit based on the following formula: = ， Or, ; where n = 1, 2, …, N, is the average circuit delay, is the standard deviation of the circuit delay, is the operating probability of the nth preset circuit under the ith voltage condition; The determination module is specifically configured to determine the preferred circuit from the plurality of preset circuits according to the power-delay product of the first preset circuit, the robustness value, the preset power-delay product weight, and the preset robustness value weight.

7. The device according to claim 6, characterized in that, The device further includes: The optimization module is configured to optimize the size parameters of the devices in the first preset circuit before the second acquisition module acquires the working probability, circuit delay, and circuit power consumption of the first preset circuit under various preset voltage conditions, to obtain an optimized first preset circuit, where the size parameters include at least one of gate length, gate width, and the number of gates, and the circuit delay of the optimized first preset circuit under various preset voltage conditions satisfies the preset circuit delay design requirements.

8. The device according to claim 6, characterized in that, The second acquisition module includes: The delay acquisition sub-module is configured to acquire the average circuit delay and the mean square deviation of the circuit delay of the first preset circuit under various preset voltage conditions; and calculate the circuit delay according to the average circuit delay and the mean square deviation of the circuit delay of the first preset circuit under various preset voltage conditions.

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