Method for generating scan chains across board boundaries

Abstract

The application discloses a cross-circuit-board boundary scan chain generation method, characterized by comprising the following steps: obtaining a to-be-tested chip which has created a pin library and adding the to-be-tested chip to a testable chip list; in a traversal process, other testable chips upstream of a current testable chip are found along a TDI of the current testable chip, and other testable chips downstream of the current testable chip are found along a TDO of the current testable chip, and the testable chips found are sequenced in an order from upstream to downstream; according to a test requirement, testable chips of the same type in the testable chip list are connected in series according to the testable chip sequencing to form an executable scan chain; a TDI of the executable scan chain is the TDI of the first scan chain before being connected in series, a TDO of the executable scan chain is the TDO of the nth scan chain before being connected in series, and n>1. The application can reduce port resource occupation and improve test efficiency under the condition of limited hardware resources and without reducing test coverage.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a method for generating cross-circuit board boundary scan chains. Background Technology

[0002] Boundary scan testing emerged in the 1990s. With the advent of large-scale integrated circuits, printed circuit board manufacturing processes have become increasingly smaller and thinner, making traditional ICT testing inadequate for the testing requirements of these products. Due to the numerous pins on chips, the small size of components, and the extremely high density of boards, probe testing is simply impossible. A new testing technology has emerged, defined by the Joint Test Action Group (JTAG) as boundary scan testing.

[0003] Boundary scan is a set of design rules applied at the integrated circuit level, allowing software to mitigate the ever-increasing costs of designing, manufacturing, and testing digital systems. Extremely difficult printed circuit board testing problems that previously required specialized testing methods can now be handled easily and quickly by boundary scan.

[0004] Boundary scan testing primarily targets digital logic structures and focuses mainly on areas outside the integrated circuit chip. Boundary scan can perform interconnect testing and diagnostics between boundary scan-enabled chips, as well as varying degrees of internal testing within boundary scan-enabled chips.

[0005] With the rapid advancements in integrated circuit technology, integrated circuits are becoming increasingly larger and denser, leading to a growing number of interfaces on the motherboards under test. These interfaces require the design of matching transition boards for testing. Since each test transition board has at least one chip supporting boundary scan, they are identified as one or more separate scan chains. However, the number of configurable TAP ports is limited by hardware resources. Therefore, a cross-board scan chain generation method is needed to connect some test transition boards in series to reuse some TAP ports and alleviate the burden on hardware resources. Summary of the Invention

[0006] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0007] The technical problem to be solved by the present invention is to provide a method for generating cross-circuit board boundary scan chains that can reduce port resource usage under limited hardware resources and without reducing test coverage.

[0008] To solve the above-mentioned technical problems, the present invention provides a method for generating cross-circuit board boundary scan chains, comprising the following steps:

[0009] S1, retrieve the chip under test whose pin library has been created, and add it to the list of testable chips;

[0010] S2, the list of testable chips, during the traversal process, searches for other testable chips upstream along the TDI of the current testable chip, and searches for other testable chips downstream along the TDO of the current testable chip, and numbers the found testable chips in order from upstream to downstream.

[0011] S3. According to the test requirements, the interfaces of the same type to be tested in the list of testable chips are connected in series according to the order of the testable chips to form an execution scan chain;

[0012] The TDI of the executable scan chain is taken from the TDI of the first scan chain before it is concatenated, and the TDO of the executable scan chain is taken from the TDO of the nth scan chain before it is concatenated, where n>1.

[0013] Optionally, a virtual connector can be used to connect the two testable chips with the same type of interface.

[0014] Optionally, a virtual jumper is provided between the two testable chips.

[0015] Alternatively, the cross-circuit board boundary scan chain generation method may be further improved by including:

[0016] S4. Determine the scan chains to be merged and their order based on the test requirements, and obtain the number of scan chains to be merged, denoted as m.

[0017] Then, the scan chains are numbered according to the order of the testable chips. The first scan chain is numbered 1, the second scan chain is numbered 2, and the last scan chain is numbered m.

[0018] S5, create m-1 new virtual nodes, change the TDO configuration of the nth scan chain and the TDI configuration of the (n+1)th scan chain, m-1≥n≥1;

[0019] Place the TDO pin on the TDO node of the nth scan chain onto the nth virtual node, and place the TDI pin on the TDI node of the (n+1)th scan chain onto the nth virtual node.

[0020] S6. Randomly select a chip under test from the scan chain before merging as the central device, and start searching along the TDI node and TDO node of the central device to both sides, finally forming a complete scan chain that includes all the chips under test before merging.

[0021] This invention uses a virtual connector to connect the TDO / TDI of some chips under test on the circuit board under test and the TDI / TDO of chips under test on the circuit board to be merged. This connection allows the boundary scan software to expand to both sides along the TDI / TDO of any chip under test in the chain when identifying the scan chain, thereby finding a complete scan chain that includes all chips under test in the chain. This reduces port resource usage and improves test efficiency under limited hardware resources and without reducing test coverage. Attached Figure Description

[0022] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:

[0023] Figure 1 This is a schematic diagram of the existing technology scanning chain structure.

[0024] Figure 2 This is a schematic diagram of the scanning chain structure of the present invention. Figure 1 .

[0025] Figure 3 This is a schematic diagram of the scanning chain structure of the present invention. Figure 2 . Detailed Implementation

[0026] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "combined" to another element, the element can be directly connected or combined to the other element, or there may be intermediate elements. The difference is that when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals always denote the same elements.

[0027] First embodiment;

[0028] The cross-circuit board boundary scan chain generation method provided by this invention includes the following steps:

[0029] S1, retrieve the chip under test whose pin library has been created, and add it to the list of testable chips;

[0030] S2, the list of testable chips, during the traversal process, searches for other testable chips upstream along the TDI of the current testable chip, and searches for other testable chips downstream along the TDO of the current testable chip, and numbers the found testable chips in order from upstream to downstream.

[0031] S3. According to the test requirements, the interfaces of the same type to be tested in the list of testable chips are connected in series according to the order of the testable chips to form an execution scan chain;

[0032] The TDI of the executable scan chain is taken from the TDI of the first scan chain before it is concatenated, and the TDO of the executable scan chain is taken from the TDO of the nth scan chain before it is concatenated, where n>1;

[0033] Among them, the two testable chips are connected by a virtual connector through the same type of interface, and a virtual jumper is also provided between the two testable chips.

[0034] The following chip test examples, combined with the above embodiments, further illustrate the principle of the present invention;

[0035] Assume the BSI test setup has 6 TAP ports available for simultaneous testing.

[0036] Assuming the motherboard under test already has a CPU chain, PCH chain, CPLD chain, and IDRAC chain, and now there are four additional memory slots (dimm1, dimm2, dimm3, and dimm4) and two PCIe slots (boss_pcie and m2_pcie) that need to be tested, then according to the attached... Figure 1 The implementations shown for the dimm3, dimm4, boss_pcie, and m2_pcie interfaces will not be able to be assigned to test ports, thus reducing test coverage.

[0037] The solution provided by this invention is adopted:

[0038] Insert a virtual connector dimm1.cn1 onto the TDO of the chip under test (DUT) on dimm1.

[0039] Insert virtual connector dimm2.cn1 on the TDI of the chip under test (DUT) and virtual connector dimm2.cn2 on the TDO.

[0040] Insert virtual connector dimm3.cn1 on the TDI of the chip under test (DUT) and virtual connector dimm3.cn2 on the TDO.

[0041] Insert a virtual connector (dimm4.cn1) onto the TDI of the chip under test (DUT) using dimm4.

[0042] Merge dimm1.cn1 and dimm2.cn1 to generate VirtualJumper1.

[0043] Merge dimm2.cn2 and dimm3.cn1 to generate VirtualJumper2.

[0044] Merge dimm3.cn2 and dimm4.cn1 to generate VirtualJumper3.

[0045] In this way, when the boundary scan software identifies the scan chain, it can extend to both sides along the TDI and TDO nodes of any chip under test in the chain, thereby generating a scan chain containing dimm1, dimm2, dimm3 and dimm4. Under limited hardware resources and without reducing test coverage, it can reduce port resource usage.

[0046] Second embodiment;

[0047] The cross-circuit board boundary scan chain generation method provided by this invention includes the following steps:

[0048] S1, retrieve the chip under test whose pin library has been created, and add it to the list of testable chips;

[0049] S2, the list of testable chips, during the traversal process, searches for other testable chips upstream along the TDI of the current testable chip, and searches for other testable chips downstream along the TDO of the current testable chip, and numbers the found testable chips in order from upstream to downstream.

[0050] S3. According to the test requirements, the interfaces of the same type to be tested in the list of testable chips are connected in series according to the order of the testable chips to form an execution scan chain;

[0051] The TDI of the executable scan chain is taken from the TDI of the first scan chain before it is concatenated, and the TDO of the executable scan chain is taken from the TDO of the nth scan chain before it is concatenated, where n>1;

[0052] S4. Determine the scan chains to be merged and their order based on the test requirements, and obtain the number of scan chains to be merged, denoted as m.

[0053] Then, the scan chains are numbered according to the order of the testable chips. The first scan chain is numbered 1, the second scan chain is numbered 2, and the last scan chain is numbered m.

[0054] S5, create m-1 new virtual nodes, change the TDO configuration of the nth scan chain and the TDI configuration of the (n+1)th scan chain, m-1≥n≥1;

[0055] Place the TDO pin on the TDO node of the nth scan chain onto the nth virtual node, and place the TDI pin on the TDI node of the (n+1)th scan chain onto the nth virtual node.

[0056] S6. Randomly select a chip under test from the scan chain before merging as the central device, and start searching along the TDI node and TDO node of the central device to both sides, finally forming a complete scan chain that includes all the chips under test before merging.

[0057] The advantage of the second embodiment compared to the first embodiment is that it does not require the addition of additional circuit board components. Instead, it connects the chips under test corresponding to the same type of interface by directly modifying the network topology of the circuit board. The second embodiment is simpler to operate, but it modifies the network topology of the original circuit board and is not reversible.

[0058] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless expressly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.

[0059] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A method of generating a boundary scan chain across a circuit board, the method comprising: The method comprises the following steps: S1, obtaining a to-be-tested chip having created a pin library and adding the to-be-tested chip to a testable chip list; S2, in the process of traversing the testable chip list, searching for other testable chips upstream along a TDI of a current testable chip and searching for other testable chips downstream along a TDO of the current testable chip, and sequentially arranging the found testable chips from upstream to downstream; S3, according to a test requirement, connecting testable chips of the same type in the testable chip list in the testable chip sequence to form an executable scan chain; The TDI of the executable scan chain is the TDI of the first scan chain before being connected, the TDO of the executable scan chain is the TDO of the nth scan chain before being connected, and n is greater than or equal to 1; S4, according to a test requirement, determining scan chains to be merged and a sequence of the scan chains, obtaining a number of scan chains to be merged, and setting the number of scan chains to be merged as m; Then, the scan chains are sequentially arranged according to the testable chip sequence, the first scan chain is sequentially arranged as No. 1, the second scan chain is sequentially arranged as No. 2, and the last scan chain is sequentially arranged as No. m; S5, newly creating m-1 virtual nodes, changing a TDO configuration of the nth scan chain and a TDI configuration of the n+1th scan chain, and m-1 is greater than or equal to n and n is greater than or equal to 1; placing a TDO pin on a TDO node of the nth scan chain on the nth virtual node and placing a TDI pin on a TDI node of the n+1th scan chain on the nth virtual node; S6, randomly selecting a to-be-tested chip on a scan chain before being merged as a central device, searching along a TDI node and a TDO node of the central device to two sides, and finally forming a complete scan chain containing all to-be-tested chips before being merged.

2. The method for generating a cross-circuit-board boundary scan chain according to claim 1, wherein: The same type of interfaces of two testable chips are connected through a virtual connector.

3. The method of claim 2, wherein: Virtual jumpers are further arranged between the two testable chips.

Images