A charge pump circuit with a reference branch

Abstract

The present application is a charge pump circuit with a reference branch, specifically relating to the technical field of phase-locked loop circuits. In the circuit, the output end of the second switch tube is connected to the third node; the third node is connected to the non-inverting input end of the first operational amplifier; the third node is also grounded through the fifth switch tube; the output end of the first switch tube is connected to the fourth node; the fourth node is grounded through the fourth switch tube; the fourth node is also connected to the output end of the first operational amplifier; the output end of the third switch tube is sequentially grounded through the input end of the charge and discharge unit, the output end of the charge and discharge unit and the sixth switch tube; the control end of the second operational amplifier is connected to the second node, the non-inverting input end of the second operational amplifier is connected to the first node, the inverting input end of the second operational amplifier is connected to the second node; the inverting input end of the first operational amplifier is connected to the second node. Based on the above circuit, current matching can be increased to reduce voltage fluctuations.

Description

Technical Field

[0001] The present application relates to the technical field of phase-locked loop circuits, and in particular to a charge pump circuit with a reference branch. Background Art

[0002] A phase-locked loop (PLL) is a crucial module in analog and mixed-signal circuits. It tracks the phase and frequency of an input signal and outputs a phase-locked, low-jitter signal at another frequency. A charge pump is used in a PLL to convert the digital signal output by the phase detector into an analog signal, which controls the frequency of a voltage-controlled oscillator (VCO). When the PLL is locked to a certain frequency, even the slightest jitter can alter the VCO's output frequency, affecting the overall PLL performance. Therefore, the charge pump's output voltage must be stable, ensuring current matching within the charge pump.

[0003] To ensure current matching in charge pumps, existing technologies employ the following measures: 1. Increasing the channel length of the current mirror MOS transistor; 2. Using a cascode configuration for the current mirror MOS transistor; and 3. Using an op amp to clamp the output voltage, ensuring that the output voltage is consistent with the voltage at the charge and discharge nodes. These existing technologies effectively address current mirror mismatch when the charge pump output voltage is half the power supply voltage.

[0004] However, when the output voltage of the charge pump is close to the ground potential, the existing technology cannot guarantee the matching of the current. Summary of the Invention

[0005] The present application provides a charge pump circuit with a reference branch, and the technical solution is as follows.

[0006] Provided is a charge pump circuit with a reference branch, the circuit comprising a reference branch, a first branch, a second branch, and a third branch;

[0007] In the reference branch, the input terminal of the second switch tube MP2 is connected to the power supply voltage terminal, and the output terminal of the second switch tube MP2 is connected to the third node C; the third node C is connected to the non-inverting input terminal of the first operational amplifier A1; the third node C is also grounded through the fifth switch tube MN2;

[0008] In the first branch, the first current source is grounded via the seventh switch tube M7;

[0009] In the second branch, the input terminal of the first switch transistor MP1 is connected to the power supply voltage terminal, and the output terminal of the first switch transistor MP1 is connected to a fourth node D; the fourth node D is grounded through the fourth switch transistor MN1; the fourth node D is also connected to the output terminal of the first operational amplifier A1;

[0010] In the third branch, the input end of the third switch tube MP3 is connected to the power supply voltage end, and the output end of the third switch tube is grounded through the input end of the charge and discharge unit, the output end of the charge and discharge unit, and the sixth switch tube MN3 in sequence;

[0011] The charge and discharge unit includes a first charge and discharge switch tube SW1, a second charge and discharge switch tube SW2, a third charge and discharge switch tube SW3, a fourth charge and discharge switch tube SW4 and a second operational amplifier A2;

[0012] The input end of the charge and discharge unit is connected to the second node B through the third charge and discharge switch tube SW3, and the second node B is connected to the output end of the charge and discharge unit through the first charge and discharge switch tube SW1;

[0013] The input end of the charge and discharge unit is connected to the first node A through the fourth charge and discharge switch tube SW4, and the first node A is connected to the output end of the charge and discharge unit through the second charge and discharge switch tube SW2;

[0014] The control terminal of the second operational amplifier A2 is connected to the second node B, the non-inverting input terminal of the second operational amplifier A2 is connected to the first node A, and the inverting input terminal of the second operational amplifier A2 is connected to the second node B;

[0015] The inverting input terminal of the first operational amplifier A1 is connected to the second node B;

[0016] The first node is also connected to the output voltage terminal;

[0017] The first switch tube MP1, the second switch tube MP2 and the third switch tube MP3 form a current mirror structure; the control end of the first switch tube MP1 is connected to the fourth node D;

[0018] The fourth switch transistor MN1 , the fifth switch transistor MN2 , the sixth switch transistor MN3 and the seventh switch transistor M7 form a current mirror structure.

[0019] In a possible implementation, the control-end input signal DNB of the first charge-discharge switch tube SW1 is opposite to the control-end input signal DN of the second charge-discharge switch tube SW2 .

[0020] In a possible implementation, the control-end input signal UP of the third charge-discharge switch tube SW3 is opposite to the control-end input signal UPB of the fourth charge-discharge switch tube SW4 .

[0021] In a possible implementation, the third charge and discharge switch tube SW3 and the fourth charge and discharge switch tube SW4 are PMOS tubes, and the first charge and discharge switch tube SW1 and the second charge and discharge switch tube SW2 are NMOS tubes.

[0022] In a possible implementation, the first switch transistor MP1 , the second switch transistor MP2 , and the third switch transistor MP3 are PMOS transistors, and the fourth switch transistor MN1 , the fifth switch transistor MN2 , the sixth switch transistor MN3 , and the seventh switch transistor M7 are NMOS transistors.

[0023] In a possible implementation, the circuit further includes an eighth switch tube M1, a ninth switch tube M2, a tenth switch tube M3, an eleventh switch tube M4, a twelfth switch tube M5, and a thirteenth switch tube M6;

[0024] The input end of the eighth switch tube M1 is connected to the output end of the first switch tube MP1, and the output end of the eighth switch tube M1 is connected to the fourth node D; the fourth node D is connected to the input end of the fourth switch tube MN1 through the eleventh switch tube M4;

[0025] The input end of the ninth switch tube M2 is connected to the output end of the second switch tube MP2, and the output end of the ninth switch tube M2 is connected to the third node C; the third node C is connected to the input end of the fifth switch tube MN2 through the twelfth switch tube M5;

[0026] The input end of the tenth switch tube M3 is connected to the output end of the third switch tube MP3, and the output end of the tenth switch tube M3 is connected to the input end of the charge and discharge unit; the input end of the thirteenth switch tube M6 is connected to the output end of the charge and discharge unit, and the output end of the tenth single switch tube M6 is connected to the input end of the sixth switch tube MN3.

[0027] In a possible implementation, the eighth switch tube M1 , the ninth switch tube M2 , and the tenth switch tube M3 form a current mirror structure.

[0028] In a possible implementation, the eleventh switch tube M4 , the twelfth switch tube M5 , and the thirteenth switch tube M6 form a current mirror structure.

[0029] In a possible implementation, the eighth switch tube M1, the ninth switch tube M2, and the tenth switch tube M3 are PMOS tubes;

[0030] The eleventh switch transistor M4 , the twelfth switch transistor M5 , and the thirteenth switch transistor M6 are NMOS transistors.

[0031] In a possible implementation, the output voltage terminal is further grounded via a first capacitor C1.

[0032] The technical solution provided by this application may have the following beneficial effects:

[0033] In the charge pump circuit with a reference branch shown in the present application, the circuit includes a reference branch, a first branch, a second branch, and a third branch; in the reference branch, the input end of the second switch tube MP2 is connected to the power supply voltage end, and the output end of the second switch tube MP2 is connected to the third node C; the third node C is connected to the non-inverting input end of the first operational amplifier A1; the third node C is also grounded through the fifth switch tube MN2; in the first branch, the first current source is grounded through the seventh switch tube M7; in the second branch, the input end of the first switch tube MP1 is connected to the power supply voltage end, and the output end of the first switch tube MP1 is connected to the fourth node D; the fourth node D is grounded through the fourth switch tube MN1; the fourth node D is also connected to the output end of the first operational amplifier A1; in the third branch, the input end of the third switch tube MP3 is connected to the power supply voltage end, and the output end of the third switch tube is grounded through the input end of the charge and discharge unit, the output end of the charge and discharge unit, and the sixth switch tube MN3 in sequence; the charge and discharge unit includes the first charge and discharge switch tube SW1, the second charge and discharge switch tube SW2, the third charge and discharge switch tube SW3, and the The switch tube SW3, the fourth charge and discharge switch tube SW4 and the second operational amplifier A2; the input end of the charge and discharge unit is connected to the second node B through the third charge and discharge switch tube SW3, and the second node B is connected to the output end of the charge and discharge unit through the first charge and discharge switch tube SW1; the input end of the charge and discharge unit is connected to the first node A through the fourth charge and discharge switch tube SW4, and the first node A is connected to the output end of the charge and discharge unit through the second charge and discharge switch tube SW2; the control end of the second operational amplifier A2 is connected to the second node B, the non-inverting input end of the second operational amplifier A2 is connected to the first node A, and the inverting input end of the second operational amplifier A2 is connected to the second node B; the inverting input end of the first operational amplifier A1 is connected to the second node B; the first node is also connected to the output voltage end; the first switch tube MP1, the second switch tube MP2 and the third switch tube MP3 form a current mirror structure; the control end of the first switch tube MP1 is connected to the fourth node D; the fourth switch tube MN1, the fifth switch tube MN2, the sixth switch tube MN3 and the seventh switch tube M7 form a current mirror structure. When the charge pump switches between operating states and the voltage output terminal voltage CP_OUT becomes too low, causing the current of the sixth switch MN3 to be less than that of the third switch MP3, resulting in a current mismatch, the current of the third switch MP3 can be reduced accordingly. Therefore, the above circuit structure can improve current matching and reduce voltage fluctuations when implementing the charge pump function, thereby optimizing the noise characteristics of the phase-locked loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0035] Figure 1 The figure is a schematic structural diagram of a charge pump circuit with a reference branch according to an exemplary embodiment.

[0036] Figure 2 A schematic structural diagram of a charge pump circuit with a reference branch according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0037] The following will clearly and completely describe the technical solution of this application in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0038] It should be understood that the "indication" mentioned in the embodiments of this application can be a direct indication, an indirect indication, or an indication of an association. For example, "A indicates B" can mean that A directly indicates B, for example, B can be obtained through A; it can also mean that A indirectly indicates B, for example, A indicates C, and B can be obtained through C; it can also mean that there is an association between A and B.

[0039] In the description of the embodiments of the present application, the term "corresponding" may indicate a direct or indirect correspondence between the two, or an association relationship between the two, or a relationship between indication and being indicated, configuration and being configured, etc.

[0040] In an embodiment of the present application, "predefinition" can be achieved by pre-saving corresponding codes, tables or other methods that can be used to indicate relevant information in a device (for example, including a terminal device and a network device). This application does not limit its specific implementation method.

[0041] Figure 1 is a schematic structural diagram of a charge pump circuit with a reference branch according to an exemplary embodiment, and by setting the following in the circuit Figure 1 The circuit structure shown can increase current matching to reduce voltage fluctuation when realizing the charge pump function. Figure 1 As shown, the circuit includes a reference branch, a first branch, a second branch, and a third branch;

[0042] In the reference branch, the input terminal of the second switch tube MP2 is connected to the power supply voltage terminal, and the output terminal of the second switch tube MP2 is connected to the third node C; the third node C is connected to the non-inverting input terminal of the first operational amplifier A1; the third node C is also grounded through the fifth switch tube MN2;

[0043] In the first branch, the first current source is grounded via the seventh switch tube M7;

[0044] In the second branch, the input terminal of the first switch tube MP1 is connected to the power supply voltage terminal, and the output terminal of the first switch tube MP1 is connected to the fourth node D; the fourth node D is grounded through the fourth switch tube MN1; the fourth node D is also connected to the output terminal of the first operational amplifier A1;

[0045] In the third branch, the input end of the third switch tube MP3 is connected to the power supply voltage end, and the output end of the third switch tube is grounded in sequence through the input end of the charge and discharge unit, the output end of the charge and discharge unit, and the sixth switch tube MN3;

[0046] The charge and discharge unit includes a first charge and discharge switch tube SW1, a second charge and discharge switch tube SW2, a third charge and discharge switch tube SW3, a fourth charge and discharge switch tube SW4 and a second operational amplifier A2;

[0047] The input end of the charge and discharge unit is connected to the second node B through the third charge and discharge switch tube SW3, and the second node B is connected to the output end of the charge and discharge unit through the first charge and discharge switch tube SW1;

[0048] The input end of the charge and discharge unit is connected to the first node A through the fourth charge and discharge switch tube SW4, and the first node A is connected to the output end of the charge and discharge unit through the second charge and discharge switch tube SW2;

[0049] The control terminal of the second operational amplifier A2 is connected to the second node B, the non-inverting input terminal of the second operational amplifier A2 is connected to the first node A, and the inverting input terminal of the second operational amplifier A2 is connected to the second node B;

[0050] The inverting input terminal of the first operational amplifier A1 is connected to the second node B;

[0051] The first node is also connected to the output voltage terminal;

[0052] The first switch tube MP1, the second switch tube MP2 and the third switch tube MP3 form a current mirror structure; the control terminal of the first switch tube MP1 is connected to the fourth node D;

[0053] The fourth switch MN1 , the fifth switch MN2 , the sixth switch MN3 , and the seventh switch M7 form a current mirror structure.

[0054] In a possible implementation, the control-end input signal DNB of the first charge-discharge switch tube SW1 is opposite to the control-end input signal DN of the second charge-discharge switch tube SW2 .

[0055] In a possible implementation, the control-end input signal UP of the third charge-discharge switch tube SW3 is opposite to the control-end input signal UPB of the fourth charge-discharge switch tube SW4 .

[0056] In a possible implementation, the third charge and discharge switch tube SW3 and the fourth charge and discharge switch tube SW4 are PMOS tubes, and the first charge and discharge switch tube SW1 and the second charge and discharge switch tube SW2 are NMOS tubes.

[0057] In a possible implementation, the first switch transistor MP1 , the second switch transistor MP2 , and the third switch transistor MP3 are PMOS transistors, and the fourth switch transistor MN1 , the fifth switch transistor MN2 , the sixth switch transistor MN3 , and the seventh switch transistor M7 are NMOS transistors.

[0058] In a possible implementation, the output voltage terminal is further grounded via a first capacitor C1.

[0059] A phase-locked loop (PLL) synchronizes the frequency and phase of a controlled oscillator with an input reference signal. A charge pump PLL adds a charge pump between the phase detector and loop filter of a conventional PLL. The basic principle of a charge pump is to charge a capacitor and then transfer the charge to another circuit. A mismatch between the charge and discharge currents in a charge pump can generate noise and affect the performance of the entire PLL. Therefore, it is necessary to prevent this mismatch in the charge pump.

[0060] Figure 1 The operating principle of the charge pump circuit with reference branch shown is as follows:

[0061] The working state of the charge pump circuit is divided into four states according to whether the control terminal input signal UP of the third charge and discharge switch tube SW3 and the control terminal input signal DN of the second charge and discharge switch tube SW2 are high level, as follows:

[0062] When UP is high and DN is low, the fourth charge and discharge switch tube SW4 is turned on, the second charge and discharge switch tube SW2 is turned off, and the third switch tube MP3 charges the first capacitor C1, so that the voltage CP_OUT at the output voltage terminal increases.

[0063] When UP is low and DN is high, the fourth charge and discharge switch tube SW4 is turned off, the second charge and discharge switch tube SW2 is turned on, and the third switch tube MP3 discharges the first capacitor C1, so that the voltage CP_OUT at the output voltage terminal decreases.

[0064] When UP is low and DN is low, the fourth charge-discharge switch SW4 is turned off, and the second charge-discharge switch SW2 is turned off, cutting off the charge and discharge paths for the first capacitor C1. Since the leakage current is very small after the switches are turned off, it can be roughly assumed that the voltage at the output voltage terminal CP_OUT remains unchanged.

[0065] When UP is high and DN is high, the fourth charge-discharge switch SW4 is turned on, and the second charge-discharge switch SW2 is turned on, simultaneously opening the charging and discharging paths for the first capacitor C1. At this time, if the currents of the third switch MP3 and the sixth switch MN3 are fully matched, the voltage CP_OUT at the output voltage terminal remains unchanged.

[0066] It should be noted that pbias is connected to the gates of the first, second and third switching transistors MP1, MP2 and MP3, and nbias is connected to the gates of the fourth, fifth and sixth switching transistors MN1, MN2 and MN3. pbias and nbias are bias voltages.

[0067] However, in actual application scenarios, it is difficult to fully match the currents of the third switch MP3 and the sixth switch MN3. Furthermore, due to the periodicity of the input reference signal of the phase-locked loop (PLL), the four aforementioned state cycles may occur, particularly cycles in which the charging and discharging paths for the first capacitor C1 are simultaneously opened or disconnected. This causes fluctuations in the voltage CP_OUT at the output voltage terminal. The greater the amplitude of the fluctuation in the voltage CP_OUT at the output voltage terminal, the worse the noise characteristics of the entire PLL. Therefore, it is necessary to ensure that the currents of the third switch MP3 and the sixth switch MN3 match when the charging and discharging paths for the first capacitor C1 are simultaneously opened or disconnected, that is, when UP and DN are simultaneously low or high.

[0068] First, when UP is low and DN is low, the functions of the third charge-discharge switch SW3, the first charge-discharge switch SW1, and the second operational amplifier A2 are described. When UP is low and DN is low, the fourth charge-discharge switch SW4 is off, the second charge-discharge switch SW2 is off, the third charge-discharge switch SW3 is on, and the first charge-discharge switch SW1 is on. At this point, if the circuit does not include the third charge-discharge switch SW3 and the first charge-discharge switch SW1, the source voltage of the fourth charge-discharge switch SW4 will be pulled up to the power supply voltage VDD, and the source voltage of the third charge-discharge switch SW3 will be pulled down to ground GND. At this point, if UP is switched to a high level, that is, the third switch MP3 charges the first capacitor C1, the voltage difference between the source and drain of the fourth charge-discharge switch SW4 will produce a charge sharing effect, causing the voltage CP_OUT at the output voltage terminal to fluctuate.

[0069] At this time, if the circuit includes a third charge and discharge switch tube SW3, a first charge and discharge switch tube SW1, and a second operational amplifier A2, then since the inverting input terminal and the output terminal of the operational amplifier A2 are both connected to the second node B, the voltages of the first node A connected to the non-inverting input terminal and the second node B are equal. Furthermore, the third charge and discharge switch tube SW3 and the first charge and discharge switch tube SW1 make the drain-source voltages of the fourth charge and discharge switch tube SW4 and the second charge and discharge switch tube SW2 equal. At this time, the state in which the third switch tube MP3 charges the first capacitor C1 is switched. Since the drain-source voltages of the fourth charge and discharge switch tube SW4 and the second charge and discharge switch tube SW2 are equal, the charge sharing effect is reduced, and the fluctuation of the voltage CP_OUT at the output voltage terminal is reduced.

[0070] However, when UP is at a high level and DN is at a high level, when the voltage CP_OUT at the output voltage terminal drops to close to the ground potential GND, the voltage Vgs of the gate of the sixth switch tube MN3 relative to the source is small, and the sixth switch tube MN3 enters a linear region, resulting in a smaller current mirrored by the sixth switch tube MN3 from the fourth switch tube MN1. At this time, the third switch tube MP3 normally mirrors the current of the first switch tube MP1, and the current of the third switch tube MP3 is greater than that of the sixth switch tube MN3, resulting in poor current matching between the two switch tubes.

[0071] Therefore, a reference branch is needed to address the aforementioned issue. When the voltage CP_OUT at the output voltage terminal decreases, the voltage at the first node A also decreases, which in turn decreases the voltage at the second node B. Since the second node B is connected to the inverting input of the first operational amplifier A1, and the voltage at the non-inverting input of the first operational amplifier A1 (i.e., the voltage at the third node C) remains unchanged, the voltage at the output terminal of the first operational amplifier A1 increases. This increases the voltage at the fourth node D connected to the output terminal of the first operational amplifier A1, which in turn increases the gate voltage of the first switch MP1 connected to the fourth node D. This reduces the current in the first switch MP1, and therefore the current in the third switch MP3. This reduces the current in the third switch MP3 and thus better matches the current in the sixth switch MN3. This reduces fluctuations in the voltage CP_OUT at the output voltage terminal and improves the noise characteristics of the phase-locked loop.

[0072] In summary, in the charge pump circuit with a reference branch shown in the present application, the circuit includes a reference branch, a first branch, a second branch, and a third branch; in the reference branch, the input end of the second switch tube MP2 is connected to the power supply voltage end, and the output end of the second switch tube MP2 is connected to the third node C; the third node C is connected to the non-inverting input end of the first operational amplifier A1; the third node C is also grounded through the fifth switch tube MN2; in the first branch, the first current source is grounded through the seventh switch tube M7; in the second branch, the input end of the first switch tube MP1 is connected to the power supply voltage end, and the output end of the first switch tube MP1 is connected to the fourth node D; the fourth node D is grounded through the fourth switch tube MN1; the fourth node D is also connected to the output end of the first operational amplifier A1; in the third branch, the input end of the third switch tube MP3 is connected to the power supply voltage end, and the output end of the third switch tube is grounded in sequence through the input end of the charge and discharge unit, the output end of the charge and discharge unit, and the sixth switch tube MN3; the charge and discharge unit includes the first charge and discharge switch tube SW1, the second charge and discharge switch tube SW2, the third a charge-discharge switch tube SW3, a fourth charge-discharge switch tube SW4, and a second operational amplifier A2; the input end of the charge-discharge unit is connected to the second node B through the third charge-discharge switch tube SW3, and the second node B is connected to the output end of the charge-discharge unit through the first charge-discharge switch tube SW1; the input end of the charge-discharge unit is connected to the first node A through the fourth charge-discharge switch tube SW4, and the first node A is connected to the output end of the charge-discharge unit through the second charge-discharge switch tube SW2; the control end of the second operational amplifier A2 is connected to the second node B, the non-inverting input end of the second operational amplifier A2 is connected to the first node A, and the inverting input end of the second operational amplifier A2 is connected to the second node B; the inverting input end of the first operational amplifier A1 is connected to the second node B; the first node is also connected to the output voltage end; the first switch tube MP1, the second switch tube MP2, and the third switch tube MP3 form a current mirror structure; the control end of the first switch tube MP1 is connected to the fourth node D; the fourth switch tube MN1, the fifth switch tube MN2, the sixth switch tube MN3, and the seventh switch tube M7 form a current mirror structure. When the charge pump switches between operating states and the voltage output terminal voltage CP_OUT becomes too low, causing the current of the sixth switch MN3 to be less than that of the third switch MP3, resulting in a current mismatch, the current of the third switch MP3 can be reduced accordingly. Therefore, the above circuit structure can improve current matching and reduce voltage fluctuations when implementing the charge pump function, thereby optimizing the noise characteristics of the phase-locked loop.

[0073] Further, in Figure 1On the basis of the above, a cascaded switching tube method can also be used to increase the impedance of the input end and the output end of the charging and discharging unit, so that the drain voltage of the third switching tube MP3 and the sixth switching tube MN3 changes less with the voltage CP_OUT of the voltage output end, thereby reducing the influence of the voltage CP_OUT of the voltage output end on the current matching of the third switching tube MP3 and the sixth switching tube MN3. Figure 2 FIG. 1 shows a schematic diagram of a charge pump circuit with a reference branch according to an embodiment of the present application. Figure 2 As shown, in a possible implementation, the circuit further includes an eighth switch tube M1, a ninth switch tube M2, a tenth switch tube M3, an eleventh switch tube M4, a twelfth switch tube M5, and a thirteenth switch tube M6;

[0074] The input end of the eighth switch tube M1 is connected to the output end of the first switch tube MP1, and the output end of the eighth switch tube M1 is connected to the fourth node D; the fourth node D is connected to the input end of the fourth switch tube MN1 through the eleventh switch tube M4;

[0075] The input end of the ninth switch tube M2 is connected to the output end of the second switch tube MP2, and the output end of the ninth switch tube M2 is connected to the third node C; the third node C is connected to the input end of the fifth switch tube MN2 through the twelfth switch tube M5;

[0076] The input end of the tenth switch tube M3 is connected to the output end of the third switch tube MP3, and the output end of the tenth switch tube M3 is connected to the input end of the charge and discharge unit; the input end of the thirteenth switch tube M6 is connected to the output end of the charge and discharge unit, and the output end of the tenth single switch tube M6 is connected to the input end of the sixth switch tube MN3.

[0077] like Figure 2 As shown, in a possible implementation, the eighth switch tube M1 , the ninth switch tube M2 and the tenth switch tube M3 form a current mirror structure.

[0078] like Figure 2 As shown, in a possible implementation, the eleventh switch tube M4 , the twelfth switch tube M5 and the thirteenth switch tube M6 form a current mirror structure.

[0079] like Figure 2 As shown, in a possible implementation, the eighth switch tube M1, the ninth switch tube M2 and the tenth switch tube M3 are PMOS tubes;

[0080] The eleventh switch transistor M4 , the twelfth switch transistor M5 , and the thirteenth switch transistor M6 are NMOS transistors.

[0081] It should be noted that pcbias is connected to the gates of the eighth switch M1, the ninth switch M2, and the tenth switch M3, and ncbias is connected to the gates of the eleventh switch M4, the twelfth switch M5, and the thirteenth switch M6. pcbias and ncbias are bias voltages.

[0082] In summary, in the charge pump circuit with a reference branch shown in the present application, the circuit includes a reference branch, a first branch, a second branch, and a third branch; in the reference branch, the input end of the second switch tube MP2 is connected to the power supply voltage end, and the output end of the second switch tube MP2 is connected to the third node C; the third node C is connected to the non-inverting input end of the first operational amplifier A1; the third node C is also grounded through the fifth switch tube MN2; in the first branch, the first current source is grounded through the seventh switch tube M7; in the second branch, the input end of the first switch tube MP1 is connected to the power supply voltage end, and the output end of the first switch tube MP1 is connected to the fourth node D; the fourth node D is grounded through the fourth switch tube MN1; the fourth node D is also connected to the output end of the first operational amplifier A1; in the third branch, the input end of the third switch tube MP3 is connected to the power supply voltage end, and the output end of the third switch tube is grounded in sequence through the input end of the charge and discharge unit, the output end of the charge and discharge unit, and the sixth switch tube MN3; the charge and discharge unit includes the first charge and discharge switch tube SW1, the second charge and discharge switch tube SW2, the third a charge-discharge switch tube SW3, a fourth charge-discharge switch tube SW4, and a second operational amplifier A2; the input end of the charge-discharge unit is connected to the second node B through the third charge-discharge switch tube SW3, and the second node B is connected to the output end of the charge-discharge unit through the first charge-discharge switch tube SW1; the input end of the charge-discharge unit is connected to the first node A through the fourth charge-discharge switch tube SW4, and the first node A is connected to the output end of the charge-discharge unit through the second charge-discharge switch tube SW2; the control end of the second operational amplifier A2 is connected to the second node B, the non-inverting input end of the second operational amplifier A2 is connected to the first node A, and the inverting input end of the second operational amplifier A2 is connected to the second node B; the inverting input end of the first operational amplifier A1 is connected to the second node B; the first node is also connected to the output voltage end; the first switch tube MP1, the second switch tube MP2, and the third switch tube MP3 form a current mirror structure; the control end of the first switch tube MP1 is connected to the fourth node D; the fourth switch tube MN1, the fifth switch tube MN2, the sixth switch tube MN3, and the seventh switch tube M7 form a current mirror structure. When the charge pump switches between operating states and the voltage output terminal voltage CP_OUT becomes too low, causing the current of the sixth switch MN3 to be less than that of the third switch MP3, resulting in a current mismatch, the current of the third switch MP3 can be reduced accordingly. Therefore, the above circuit structure can improve current matching and reduce voltage fluctuations when implementing the charge pump function, thereby optimizing the noise characteristics of the phase-locked loop.

[0083] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0084] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A charge pump circuit with a reference branch, characterized in that: The circuit includes a reference branch, a first branch, a second branch, and a third branch; In the reference branch, the input terminal of the second switch tube MP2 is connected to the power supply voltage terminal, and the output terminal of the second switch tube MP2 is connected to the third node C; the third node C is connected to the non-inverting input terminal of the first operational amplifier A1; the third node C is also grounded through the fifth switch tube MN2; In the first branch, the first current source is grounded via the seventh switch tube M7; In the second branch, the input terminal of the first switch transistor MP1 is connected to the power supply voltage terminal, and the output terminal of the first switch transistor MP1 is connected to a fourth node D; the fourth node D is grounded through the fourth switch transistor MN1; the fourth node D is also connected to the output terminal of the first operational amplifier A1; In the third branch, the input end of the third switch tube MP3 is connected to the power supply voltage end, and the output end of the third switch tube is grounded through the input end of the charge and discharge unit, the output end of the charge and discharge unit, and the sixth switch tube MN3 in sequence; The charge and discharge unit includes a first charge and discharge switch tube SW1, a second charge and discharge switch tube SW2, a third charge and discharge switch tube SW3, a fourth charge and discharge switch tube SW4 and a second operational amplifier A2; The input end of the charge and discharge unit is connected to the second node B through the third charge and discharge switch tube SW3, and the second node B is connected to the output end of the charge and discharge unit through the first charge and discharge switch tube SW1; The input end of the charge and discharge unit is connected to the first node A through the fourth charge and discharge switch tube SW4, and the first node A is connected to the output end of the charge and discharge unit through the second charge and discharge switch tube SW2; The control terminal of the second operational amplifier A2 is connected to the second node B, the non-inverting input terminal of the second operational amplifier A2 is connected to the first node A, and the inverting input terminal of the second operational amplifier A2 is connected to the second node B; The inverting input terminal of the first operational amplifier A1 is connected to the second node B; The first node is also connected to the output voltage terminal; The first switch tube MP1, the second switch tube MP2 and the third switch tube MP3 form a current mirror structure; the control end of the first switch tube MP1 is connected to the fourth node D; The fourth switch transistor MN1 , the fifth switch transistor MN2 , the sixth switch transistor MN3 and the seventh switch transistor M7 form a current mirror structure.

2. The circuit according to claim 1, wherein: The control terminal input signal DNB of the first charge and discharge switch tube SW1 is opposite to the control terminal input signal DN of the second charge and discharge switch tube SW2.

3. The circuit according to claim 1, wherein: The control terminal input signal UP of the third charge and discharge switch tube SW3 is opposite to the control terminal input signal UPB of the fourth charge and discharge switch tube SW4.

4. The circuit according to any one of claims 1 to 3, characterized in that The third charge and discharge switch tube SW3 and the fourth charge and discharge switch tube SW4 are PMOS tubes, and the first charge and discharge switch tube SW1 and the second charge and discharge switch tube SW2 are NMOS tubes.

5. The circuit according to any one of claims 1 to 3, characterized in that: The first switch transistor MP1 , the second switch transistor MP2 , and the third switch transistor MP3 are PMOS transistors, and the fourth switch transistor MN1 , the fifth switch transistor MN2 , the sixth switch transistor MN3 , and the seventh switch transistor M7 are NMOS transistors.

6. The circuit according to any one of claims 1 to 3, characterized in that: The circuit further includes an eighth switch tube M1, a ninth switch tube M2, a tenth switch tube M3, an eleventh switch tube M4, a twelfth switch tube M5 and a thirteenth switch tube M6; The input end of the eighth switch tube M1 is connected to the output end of the first switch tube MP1, and the output end of the eighth switch tube M1 is connected to the fourth node D; the fourth node D is connected to the input end of the fourth switch tube MN1 through the eleventh switch tube M4; The input end of the ninth switch tube M2 is connected to the output end of the second switch tube MP2, and the output end of the ninth switch tube M2 is connected to the third node C; the third node C is connected to the input end of the fifth switch tube MN2 through the twelfth switch tube M5; The input end of the tenth switch tube M3 is connected to the output end of the third switch tube MP3, and the output end of the tenth switch tube M3 is connected to the input end of the charge and discharge unit; the input end of the thirteenth switch tube M6 is connected to the output end of the charge and discharge unit, and the output end of the thirteenth switch tube M6 is connected to the input end of the sixth switch tube MN3.

7. The circuit according to claim 6, characterized in that The eighth switch tube M1 , the ninth switch tube M2 and the tenth switch tube M3 form a current mirror structure.

8. The circuit according to claim 6, characterized in that The eleventh switch tube M4 , the twelfth switch tube M5 and the thirteenth switch tube M6 form a current mirror structure.

9. The circuit according to claim 6, characterized in that The eighth switch tube M1, the ninth switch tube M2 and the tenth switch tube M3 are PMOS tubes; The eleventh switch transistor M4 , the twelfth switch transistor M5 , and the thirteenth switch transistor M6 are NMOS transistors.

10. The circuit according to claim 1, wherein: The output voltage terminal is also grounded via a first capacitor C1.

Images