Two-step sawtooth single slope ADC

Abstract

The invention discloses a two-step sawtooth single slope ADC, which comprises a pixel array, a row driving circuit, a ramp generator, a comparator module, a counter and a register. In each comparator module, a No. 1 comparator is connected to a No. 1 MOS tube and a No. 2 MOS tube, and a No. 2 comparator is connected to a No. 3 MOS tube and a No. 4 MOS tube; the positive input end of the No. 1 comparator is connected to the output end of the column pixel circuit via a No. 1 capacitor, the negative input end of the No. 1 comparator is connected to the output end of the ramp generator via a No. 1 switch, the No. 2 switch and the No. 4 capacitor connected in series are connected in parallel between the two ends of the No. 1 switch, the gate of the No. 5 MOS tube is connected between the No. 2 switch and the No. 4 capacitor, one end of the No. 3 switch is connected between the No. 2 switch and the No. 4 capacitor, and the other end is connected to a reference voltage; the No. 2 capacitor and the No. 3 capacitor are connected between the No. 1 comparator and the No. 2 comparator. The invention can save the long conversion time of the SS ADC, reduce the power consumption of the SS ADC circuit, has a simple structure, and ensures the high precision of the ADC.

Description

Technical Field

[0001] The present invention relates to the field of CMOS image sensor readout circuits, and more particularly to a two-step sawtooth single slope ADC. Background Art

[0002] CIS is widely used in the field of mobile devices, such as wearable devices, smartphones, and tablets, where extended battery life is required. The main module in the readout circuit is the ADC, which accounts for a large proportion of power consumption. Compared with other structures, a column-parallel single slope (SS) ADC is used in most cases because it can achieve good linearity with a relatively simple structure. Increasing the resolution and frame rate of CIS will lead to an increase in the quantization period and clock frequency of the SS ADC, respectively, which directly leads to an increase in power consumption. Therefore, research on low power consumption of SS ADC has important practical significance.

[0003] In a CMOS image sensor with column-parallel SS ADC, each column of SS ADC consists of a comparator, a counter, and a register, and the ramp generator is shared by all column SS ADCs. Each comparator in the column compares the ramp signal with the input signal from the pixel array, and then, when the input signal exceeds the ramp signal, the comparator output is changed so that the counter starts counting until the ramp signal ends and the count is completed. The result is latched and then read out through the subsequent circuit. Therefore, the SS ADC requires at least a 2p clock step to perform a P-bit A / D conversion.

[0004] The comparator compares the ramp signal Vin_ramp with the signal Vin_pixel. Due to the non-ideal factors such as mismatch, response delay and charge injection in the comparator itself, if the pixel signal is quantized once, the technical result will cause poor linearity due to the existence of irrational factors. To address this problem, digital correlated double sampling technology is generally used for traditional SS ADC. This technology eliminates mismatch, response delay and charge injection by quantizing the reset voltage and pixel voltage and taking the difference. Summary of the invention

[0005] The purpose of the present invention is to overcome the deficiencies in the prior art and propose a two-step sawtooth single slope ADC. In the traditional digital correlated double sampling SS ADC, a new low-power SS ADC working mode is realized. The multi-stage SS ADC of the present design can save the long conversion time of the SS ADC and reduce the power consumption of the SS ADC circuit. The structure is simple and the high precision of the ADC is guaranteed.

[0006] The objectives of the present invention are achieved through the following technical solutions.

[0007] The two-step serrated single-slope ADC of the present invention includes a pixel array, a row driving circuit, a ramp generator, and an ADC array. Each column of SS ADCs in the ADC array is composed of a comparator module, a counter, and a register. The row driving circuit provides driving signals for the pixel circuits in each row of the pixel array simultaneously. One input terminal of each comparator module is connected to the ramp generator, and the other input terminal is connected to the pixel circuits in the corresponding column in the pixel array. The output terminal of each comparator module is connected to the input terminals of the corresponding counter and register. It is characterized in that each comparator module includes a first comparator and a second comparator. A first MOS transistor is connected between the positive input terminal and the positive output terminal of the first comparator. A second MOS transistor is connected between the negative input terminal and the negative output terminal of the first comparator. A third MOS transistor is connected between the positive input terminal and the positive output terminal of the second comparator. A fourth MOS transistor is connected between the negative input terminal and the negative output terminal of the second comparator. The negative output terminal of the second comparator is used as the output terminal and is connected to the input terminals of the corresponding counter and register. The positive input terminal of the first comparator is connected to the output terminal of the column pixel circuit through a first capacitor. The negative input terminal of the first comparator is connected to the output terminal of the ramp generator through a first switch. A second switch and a fourth capacitor connected in series are connected in parallel between the two ends of the first switch. The gate of a fifth MOS transistor is connected between the second switch and the fourth capacitor. One end of a third switch is connected between the second switch and the fourth capacitor, and the other end is connected to a reference voltage. A second capacitor is connected between the positive output terminal of the first comparator and the positive input terminal of the second comparator. A third capacitor is connected between the negative output terminal of the first comparator and the negative input terminal of the second comparator. The positive output terminal of the first comparator is grounded through a fifth capacitor. The negative output terminal of the first comparator is grounded through a sixth capacitor.

[0008] The quantization period is divided into a reset stage, a coarse quantization stage, and a low / high differential input stage;

[0009] First, in the reset stage, when the ramp generator signal Vin_ramp > the column pixel circuit output signal Vin_pixel, the counter starts to count, and then enters the coarse quantization stage. At this time, an intermediate value voltage Vc is set for Vin_ramp and compared with Vin_pixel. If Vc < Vin_pixel, it enters the low differential input stage. If Vc > Vin_pixel, it enters the high differential input stage, and at this time the counter counts Qx;

[0010] Deform the ramp in the low / high differential input stage into three sawtooth shapes, including sub-step voltage segments P[1:3] and sub-ramp segments S[1:3], and the sub-step voltages are VP[1:3] respectively. At this time, perform sub-coarse quantization according to the magnitude relationship between Vin_pixel in the low / high differential input stage and VP[1:3]. For each sub-coarse quantization, if Vin_pixel < VP[i], the counter counts 2 M , where M is the number of bits corresponding to the sub-coarse quantization. After the sub-coarse quantization is completed, the sub-ramp segment where Vin_pixel overlaps with Vin_ramp will be subjected to fine quantization;

[0011] The final output result is obtained by subtracting the quantization result in the reset stage from the sum of the quantization results in the coarse quantization stage and the low / high differential input stage.

[0012] Compared with the prior art, the beneficial effects brought by the technical solution of the present invention are:

[0013] The present invention proposes a 12-bit low-power column-parallel single-slope analog-to-digital converter that applies digital correlated double sampling technology to a CMOS image sensor. The proposed SS ADC reduces power consumption in two ways. First, two-step quantization is achieved through the voltage difference between the upper and lower plates of the capacitor. Second, a sawtooth ramp is used to save the power consumption generated by the counter by combining coarse quantization and fine quantization. The proposed SS ADC is designed using 0.11μm CIS process technology. The main clock frequency is 250MHz, the row conversion time is 12.8μs, and the power supplies for the analog part and the digital part are 3.3V and 1.5V respectively. The results show that the power consumption of the current-steering ramp generator is 23.29mW, and the power consumption of a single-column SS ADC is 30.7μW. Compared with the traditional single-column SS ADC, the energy consumption in one conversion cycle can be reduced by 43-47%, and the energy consumption of a 1000-column image sensor array can be reduced by 25%. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic block diagram of the column-parallel SS ADC structure;

[0015] Figure 3 It is a simplified circuit diagram of the comparator module;

[0016] Figure 2 It is a timing diagram of the digital correlated double sampling SS ADC;

[0017] Figure 4 It is a schematic diagram of the quantization result of the two-step quantization SS ADC in stage A;

[0018] Figure 5 It is a schematic diagram of the quantization result of the two-step quantization SS ADC in stage B;

[0019] Figure 6It is a schematic diagram of the critical point quantization result of the two-step quantization SS ADC A stage;

[0020] Figure 7 It is a schematic diagram of the critical point quantization result of the two-step quantization SS ADC B stage;

[0021] Figure 8 It is a schematic diagram of sawtooth SS ADC quantization results;

[0022] Fig. 9 It is a schematic diagram of sawtooth SS ADC quantization calibration results;

[0023] Fig.10 The figure is a schematic diagram of the two-step sawtooth SS ADC quantization calibration results.

[0024] Figure symbols: OPA1 comparator No. 1, OPA2 comparator No. 2, M1 MOS tube No. 1, M2 MOS tube No. 2, M3 MOS tube No. 3, M4 MOS tube No. 4, M5 MOS tube No. 5, S1 switch No. 1, S2 switch No. 2, S3 switch No. 3, C1 capacitor No. 1, C2 capacitor No. 2, C3 capacitor No. 3, C4 capacitor No. 4, C5 capacitor No. 5, C6 capacitor No. 6, GND ground. DETAILED DESCRIPTION

[0025] The present invention will be further described below in conjunction with the accompanying drawings.

[0026] The two-step sawtooth monoslope ADC of the present invention adopts Figure 1 The column parallel SS ADC structure shown mainly includes a pixel array, a row driving circuit, a ramp generator, and an ADC array. Each column SS ADC in the ADC array is composed of a comparator module, a counter, and a register. The row driving circuit provides a driving signal to the pixel circuits in each row of the pixel array at the same time. One input end of each comparator module is connected to the ramp generator, which is shared by all column SS ADCs, and the other input end is connected to the corresponding column pixel circuit in the pixel array. The output end of each comparator module is connected to the input end of the corresponding counter and register.

[0027] Each comparator module structure is as follows Figure 2As shown, it includes a comparator No. 1 OPA1 and a comparator No. 2 OPA2, wherein a MOS tube No. 1 M1 is connected between the positive input terminal and the positive output terminal of the comparator No. 1 OPA1, a MOS tube No. 2 M2 is connected between the negative input terminal and the negative output terminal of the comparator No. 1 OPA1, a MOS tube No. 3 M3 is connected between the positive input terminal and the positive output terminal of the comparator No. 2 OPA2, a MOS tube No. 4 M4 is connected between the negative input terminal and the negative output terminal of the comparator No. 2 OPA2, and the negative output terminal of the comparator No. 2 OPA2 is connected to the input terminal of the corresponding counter and register as an output terminal. The positive input end of the first comparator OPA1 is connected to the output end of the column pixel circuit via the first capacitor C1, the negative input end of the first comparator OPA1 is connected to the output end of the ramp generator via the first switch S1, the second switch S2 and the fourth capacitor C4 connected in series are connected in parallel between the two ends of the first switch S1, the gate of the fifth MOS tube M5 is connected between the second switch S2 and the fourth capacitor C4, one end of the third switch S3 is connected between the second switch S2 and the fourth capacitor C4, and the other end is connected to the reference voltage Vref. The second capacitor C2 is connected between the positive output end of the first comparator OPA1 and the positive input end of the second comparator OPA2, the third capacitor C3 is connected between the negative output end of the first comparator OPA1 and the negative input end of the second comparator OPA2, the positive output end of the first comparator OPA1 is grounded to GND via the fifth capacitor C5, and the negative output end of the first comparator OPA1 is grounded to GND via the sixth capacitor C6.

[0028] like Figure 3 As shown, the comparator module compares the ramp generator signal Vin_ramp with the column pixel circuit output signal Vin_pixel, and the signal Comp_out is the output of the comparator module. The error time t of the signal Comp_out is d The counting result in includes comparator mismatch, response delay and charge injection, which can be eliminated by subtracting the counting results in the quantization stage t2 and the reset stage t1. The result out is the differential quantization result, which is the digital correlated double sampling technology.

[0029] (I) Two-step ADC

[0030] A two-step ADC is an ADC that divides the A / D conversion process into M-bit coarse quantization and N-bit fine quantization, where the number of bits P = M + N is the most ideal. First, the coarse quantization ADC performs an A / D conversion with a large step size, and then the result of the coarse quantization is converted into an analog signal using a DAC. The difference between the input signal and the DAC output is called the residual, which is digitized by the fine ADC. The outputs of the coarse quantization ADC and the fine quantization ADC represent the upper and lower bits of the final ADC, respectively.

[0031] The basic concept of the circuit of the present invention is that the difference between the intermediate value Vc quantized by the capacitor storage ramp and Vref is:

[0032] σV = Vc - Vref (1)

[0033] where Vc is the intermediate value set according to the AD quantization range, and Vref is the reference voltage value provided by the reference voltage source.

[0034] The ramp is divided into two segments of low differential input and high differential input through a capacitor and a switch, such as Figure 4 , the low differential input stage and the high differential input stage. During the reset stage Figure 2 switch S1 and switch S3 of No. 1 are closed, and switch S2 of No. 2 is open. When entering the coarse quantization stage, the difference between the upper plate voltage Vc and the lower plate voltage Vref of the fourth capacitor C4 is σV. If Vin_pixel < Vc, then switch S1 and switch S3 of No. 1 are open, switch S2 of No. 2 is closed, and the difference σV between the upper plate voltage Vc and the lower plate voltage Vref of the fourth capacitor C4 is stored. Therefore, VB = VA - Vref + Vc, where VA is the starting voltage of the low differential input stage and VB is the starting voltage of the high differential input stage.

[0035] Low differential input stage (A stage), as Figure 4 shown, when Vin_ramp > Vin_pixel during the reset stage, the counter starts to count, and the counting result is recorded as R1, which includes errors such as delay and mismatch. Then enter the coarse quantization stage. At this time, Vin_pixel is compared with Vc. If Vin_pixel > Vc, then enter the low differential input stage. When Vin_ramp > Vin_pixel in the low differential input stage, the counting result of the counter is S1, and the quantization result is recorded as out1 = S1 - R1.

[0036] High differential input stage (B stage), as Figure 5 shown, when Vin_ramp > Vin_pixel during the reset stage, the counter starts to count, and the counting result is recorded as R1, which includes errors such as delay and mismatch. Then enter the coarse quantization stage. At this time, Vin_pixel is compared with Vc. If Vin_pixel < Vc, then the counter directly counts Q1 and enters the high differential input stage. When Vin_ramp > Vin_pixel in the high differential input stage, the counting result of the counter is S2, and the quantization result is recorded as out2 = S2 - R1 + Q1.

[0037] Due to the mismatch of the comparator module itself, it may happen that when Vin_ramp>Vc in the coarse quantization stage, it does not enter the low differential input stage, but enters the high differential input stage, resulting in inaccurate counting results, so error correction and calibration are required. Calibration is achieved by adjusting the values ​​of Vc and Vref.

[0038] It is known that VB=VA-Vref+Vc, where VA and Vc are known, and the margin voltage Vd=VB-Vc is set to perform calibration between the low differential input stage and the high differential input stage, so Vref=VA-Vd.

[0039] The value of the margin voltage Vd can be set by the coarse quantization stage to fluctuate around Vc, and the real critical value of the low differential input stage and the high differential input stage can be found. Figure 6 In the low differential input stage, when Vin_ramp>Vin_pixel in the reset stage, the counter starts counting, and the counting result is recorded as R1. In the low differential input stage, when Vin_ramp>Vin_pixel, the counter counting result is S3, and the quantization result is recorded as out3=S3-R1. Figure 7 In the high differential input stage, the counter directly counts Q1. When Vin_ramp>Vin_pixel in the high differential input stage, the counter count result is S4, and the quantization result is recorded as out4=S4-R1+Q1. The value of Vd is adjusted so that out4=out3, and then the appropriate value of Vref is found.

[0040] (II) Sawtooth SS ADC

[0041] The basic principle and working sequence of sawtooth SS ADC are as follows Figure 8 In this design, Figure 8 The signal quantization stage divides the ramp into several parts S[1:10], ten sub-ramps, and the sub-step P[1:10] is added before each sub-ramp S[i] to predict whether the comparator will flip during the corresponding ramp period S[i]. The select pulse signal reflects the above prediction results.

[0042] by Figure 8 Taking the input voltage Vin_pixel in as an example, when Vin_ramp>Vin_pixel in the reset phase, the counter starts counting, and the counting result is recorded as Q1, which includes errors such as delay and mismatch.

[0043] In the signal quantization stage P[1:5] segment, when Vin_ramp>Vin_pixel, it enters the low-frequency counting mode. In the low-frequency counting mode, the signal Vin_clk[M] sends 5 pulses to the Mth bit of the counter. MThe code will be added to the counting result, denoted as Q2. At the P[6] stage, when Vin_ramp < Vin_pixel, the falling edge of the signal means that the comparator will switch in the corresponding ramp period S[6]. Therefore, it only needs to count normally and enter the high-frequency counting mode when the signal Comp_out is at logic high level in the period S[6]. When entering the high-frequency counting mode, the counting result is denoted as Q3. So the result quantized in the signal quantization stage is Q2 + Q3. Therefore, the final counting result is Q0 = Q2 + Q3 - Q1.

[0044] As Fig. 9 shown, when (Vp)6 < Vin_pixel < (Vp)5, the comparator module will switch during the period P[6], which is a normal situation. However, if Vin_pixel is very close, there may be a situation as Fig. 9 (b) shows. The comparator will not switch during the periods P[6] and S[6], resulting in a pre-judgment error. The comparator module will switch in the period P[7], but in the corresponding period S[7], Vin_ramp < Vin_pixel, and the comparator module will not switch, leading to an error in the final quantization result. Among them, (Vp)5 is the voltage value of the fifth sub-stage, and (Vp)6 is the voltage value of the sixth sub-stage.

[0045] To prevent Fig. 9 the error in (b), it is necessary to increase the margin voltage in the periods S[1:10] to ensure that the quantization result is correct. As Fig. 9 (c) shows, part b is the margin voltage of the period S. The addition of the margin voltage can effectively correct Fig. 9 the situation in (b). It can ensure that Fig. 9 the counting result in (c) is consistent with the counting result when the comparator switches normally in the periods P[6] and S[6].

[0046] After adding the margin voltage, if the comparator module switches normally during the periods P[6] and S[6], as Fig. 9 (c) shows, then the counting result of the counter in this period is:

[0047] Q = 2 M + b - (b - a) - c + a - c = 2 M + 2a - 2c (2)

[0048] where b is the margin voltage, c represents the comparator flip delay, and a represents the difference between Vin_pixel and the end of the margin voltage of this period. If the comparator module does not switch normally during the periods P[6] and S[6], as Fig. 9(d), but switching during periods P[7] and S[7], the counting result of the counter is:

[0049] Q'=2 M +ac (3)

[0050] Increasing the margin voltage may cause Q and Q' to be unequal, so calibration is required, such as Fig. 9 As shown in (e), the correction method is to clear the counting result of period S[6], that is, Fig. 9 (c) is deemed to be the same as Fig. 9 (d) is consistent, only the counting result of period S[7] is taken. Figure 8 In the example, the count result at cycle P[6] is locked by the signal latch_control. The signal return is used to send the latch result to the counter of each bit to ensure that it continues to count based on the count result of cycle S[5]. Fig. 9 (e) The signal counter is shown by the red dashed line. Fig. 9 In (e), the high logic returned by the signal in cycle S[7] will reset or set the counter of each bit to the state at the end of cycle S[5], achieving the effect of clearing the count result [6] of cycle S. In addition, due to the switching of the comparator module in cycle P[6] and cycle S[6], the pulse Vin_clk[M] that should appear on the red dashed line of the signal Fig. 9 (e) does not appear, resulting in 2 M To correct this error, Fig. 9 When the situation in (e) occurs, the trigger signal Vin_clk[M] generates a rising edge at cycle P[8], which is transmitted to the Mth bit of the counter, increasing the original count result by 2. M , the counting result at this time is

[0051] Q”=2 M +b-(ba)-c+ac-(2 M +b-(ba)-c)+2 M =2 M +ac=Q' (4)

[0052] When two fine quantization stages occur successively, the error and delay of the comparator module will double. The result of the last P[i] stage is latched by the register, the result of the first fine quantization is cleared, and then 2 is manually recorded. M Therefore, a series of problems caused by comparator misjudgment can be solved by increasing the margin voltage and calibrating the register circuit.

[0053] (III) Two-step sawtooth SS ADC

[0054] Based on the basic principles and working sequences of the above two types of ADCs, the two-step sawtooth single-slope ADC of the present invention mainly divides the quantization period into a reset stage, a coarse quantization stage, and a low / high differential input stage.

[0055] First, in the reset stage, when the ramp generator signal Vin_ramp > the column pixel circuit output signal Vin_pixel, the counter starts counting. Then it enters the coarse quantization stage. At this time, by setting an intermediate voltage Vc for Vin_ramp and comparing it with Vin_pixel. If Vc < Vin_pixel, it enters the low differential input stage; if Vc > Vin_pixel, it enters the high differential input stage, and the counter counts Qx at this time.

[0056] In addition, by respectively setting the voltages at the critical points of the low differential input stage and the high differential input stage to compare Vin_pixel with Vin_ramp for calibration, the appropriate values of Vref and Vc are found. The method here is the same as the Vref and Vc adjustment methods in the above two-step ADC.

[0057] To save the power consumption of the counter, the ramp in the low / high differential input stage is deformed into three sawtooth shapes, including sub-step voltage segments P[1:3] and sub-ramp segments S[1:3], and the sub-step voltages are VP[1:3] respectively. At this time, according to the magnitudes of Vin_pixel and VP[1:3] in the low / high differential input stage, sub-coarse quantization (pre-judgment) is performed. For each sub-coarse quantization, if Vin_pixel < VP[i], the counter counts 2 M , M is the number of bits corresponding to the sub-coarse quantization. After the sub-coarse quantization ends, the sub-ramp segment where Vin_pixel and Vin_ramp overlap will perform fine quantization.

[0058] Due to the errors and mismatches in its comparator module, for the errors and mismatches, by setting the margin voltage of the sub-ramp segment and using the register in the digital circuit to calibrate the output result. The method here is the same as the calibration method in the above two-sawtooth SS ADC.

[0059] The final output result is obtained by subtracting the quantization result of the reset stage from the sum of the quantization results of the coarse quantization stage and the low / high differential input stage.

[0060] For example: The basic principle and working sequence of the two-step sawtooth SS ADC are as Fig.10 shown. In this design, Fig.10In the signal quantization stage, the ramp is divided into sub-step voltage segments P[1:3] and sub-ramp segments S[1:3]. The voltage values in the sub-step stage are VP[1:3] respectively. P[1:3] is added before each ramp S[i] to predict whether the comparator will switch during the corresponding ramp period S[i]. The above prediction result is reflected by the Vin_clk[M] signal.

[0061] Take Fig.10 the input voltage Vin_pixel in (a) as an example. First, the reset signal is quantized in the reset stage, and the counting result is recorded as R1. Then it enters the coarse quantization stage. If Vin_pixel > Vc, the ramp in the quantization signal stage is Fig.10 the low differential input stage in black in (a). At this time, VP[1] < Vin_pixel < VP[2], then the counter in the pre-judgment stage (sub-coarse quantization stage) counts 2 * 2 M , and then enters the S[3] stage for fine quantization Vin_pixel < Vin_ramp, and the counter starts to count, and the counting result is recorded as D1. The final quantization result is Qn1 = S1 - R1 = 2 * 2 M + D1 - R1, and the subtraction is processed by the data processing module.

[0062] Fig.10 Take the input voltage Vin_pixel in (b) as an example. First, the reset signal is quantized in the reset stage, and the counting result is recorded as R2. Then it enters the coarse quantization stage. If Vin_pixel < Vc, the counter counts up Qx, and the value of Qx needs to be determined by the values of Vc and Vref. The ramp in the quantization signal stage is Fig.10 the high differential input stage of the black dotted line in (a). At this time, Vin_pixel < VP[1] (in the dotted line), then the counter in the pre-judgment stage (sub-coarse quantization stage) does not count. Then it enters the S[1] stage for fine quantization Vin_pixel < Vin_ramp, and the counter starts to count, and the counting result is recorded as D2. The final quantization result is Qn2 = S2 - R2 = Qx + D2 - R2, and the subtraction is processed by the data processing module. The voltage margin b segment is used to prevent the error caused by misjudgment in the P[i] stage. The value of the voltage Vd = VP[3] is set slightly lower than Vc, which is used to make the comparator flip at the latest in the P[3] stage for fine quantization and can calibrate the misjudgment in the coarse quantization stage.

[0063] This method speeds up the row conversion time of the SS ADC, reduces the power consumption of the SS ADC by combining coarse quantization, sub-coarse quantization, and fine quantization, and achieves high ADC accuracy with a simple circuit.

[0064] Although the functions and working processes of the present invention have been described above in conjunction with the accompanying drawings, the present invention is not limited to the above-mentioned specific functions and working processes, and the above-mentioned specific implementation methods are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which are all within the protection of the present invention.

Claims

1. A two-step sawtooth single slope ADC, comprising a pixel array, a row driving circuit, a ramp generator, and an ADC array, wherein each column of SS ADC in the ADC array is composed of a comparator module, a counter, and a register, wherein the row driving circuit simultaneously provides a driving signal for the pixel circuits in each row of the pixel array, wherein one input end of each of the comparator modules is connected to the ramp generator, and the other input end is connected to the pixel circuits in the corresponding column in the pixel array, and the output end of each of the comparator modules is connected to the input end of the corresponding counter and register, wherein: Each of the comparator modules includes a first comparator OPA1 and a second comparator OPA2. A first MOS transistor M1 is connected between the positive input terminal and the positive output terminal of the first comparator OPA1. A second MOS transistor M2 is connected between the negative input terminal and the negative output terminal of the first comparator OPA1. A third MOS transistor M3 is connected between the positive input terminal and the positive output terminal of the second comparator OPA2. A fourth MOS transistor M4 is connected between the negative input terminal and the negative output terminal of the second comparator OPA2. The negative output terminal of the second comparator OPA2 is connected as an output terminal to the input terminals of the corresponding counter and register. The positive input terminal of the first comparator OPA1 is connected to the output terminal of the column pixel circuit through a first capacitor C1. The negative input terminal of the first comparator OPA1 is connected to the output terminal of the ramp generator through a first switch S1. A second switch S2 and a fourth capacitor C4 connected in series are connected in parallel between the two ends of the first switch S1. The gate of a fifth MOS transistor M5 is connected between the second switch S2 and the fourth capacitor C4. One end of a third switch S3 is connected between the second switch S2 and the fourth capacitor C4, and the other end is connected to a reference voltage. A second capacitor C2 is connected between the positive output terminal of the first comparator OPA1 and the positive input terminal of the second comparator OPA2. A third capacitor C3 is connected between the negative output terminal of the first comparator OPA1 and the negative input terminal of the second comparator OPA2. The positive output terminal of the first comparator OPA1 is grounded through a fifth capacitor C5. The negative output terminal of the first comparator OPA1 is grounded through a sixth capacitor C6. The quantization period is divided into a reset stage, a coarse quantization stage, and a low / high differential input stage. First, in the reset stage, when the ramp generator signal Vin_ramp > the column pixel circuit output signal Vin_pixel, the counter starts to count, and then enters the coarse quantization stage. At this time, an intermediate value voltage Vc is set for Vin_ramp and compared with Vin_pixel. If Vc < Vin_pixel, it enters the low differential input stage. If Vc > Vin_pixel, it enters the high differential input stage, and at this time the counter counts Qx. Deform the ramp in the low / high differential input stage into three parts of sawtooth shape, including sub-step voltage segments P[1:3] and sub-ramp segments S[1:3], and the sub-step voltages are VP[1:3] respectively; at this time, perform sub-coarse quantization according to the magnitudes of Vin_pixel and VP[1:3] in the low / high differential input stage. For each sub-coarse quantization, if Vin_pixel < VP[i], the counter counts by 2 M , M is the number of bits corresponding to the sub-coarse quantization. After the sub-coarse quantization is completed, the sub-ramp segment where Vin_pixel and Vin_ramp overlap will be subjected to fine quantization; The final output result is obtained by subtracting the quantization result of the reset stage from the sum of the quantization results of the coarse quantization stage and the low / high differential input stage.

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