A method and device for detecting chip connectivity

Abstract

The embodiment of the present invention provides a method and device for detecting the connectivity of a chip. The chip to be detected includes a first module to be detected and a second module to be detected, including the first module to be detected whose port attribute is an output port and the second module to be detected whose port attribute is an input port; the first module to be detected and the second module to be detected have a connection relationship; the output port of the first module to be detected is made to output a sending signal through an assignment instruction; a receiving signal is obtained through the input port of the second module to be detected; if the sending signal of the first module to be detected is the same as the receiving signal of the second module to be detected, it is determined that the first module to be detected is connected to the second module to be detected. By judging whether the sending signal of the first module to be detected is the same as the receiving signal of the second module to be detected, it can be more accurately determined whether the first module to be detected is connected to the second module to be detected.

Description

Technical Field

[0001] The present invention relates to the field of communication detection, and in particular to a method and device for detecting chip connectivity. Background Art

[0002] Since the cost of chip design in advanced processes is extremely high, it is very important to find all design defects and errors through verification activities before tape-out. Therefore, the quality of the chip depends largely on verification. During the chip verification process, a lot of work is done to determine the connectivity of the ports between modules in the chip.

[0003] At present, the method of verifying the connectivity of the ports between modules in the chip is generally functional verification. Specifically, by verifying whether the modules in the chip can work normally, it is confirmed whether the modules in the chip are connected. However, since the normal operation of the modules requires a clear understanding of the working principles of the modules, it is time-consuming and complicated, wasting manpower and material resources.

[0004] In summary, how to easily and quickly determine the connectivity of ports between modules in a chip is a technical problem that urgently needs to be solved. Summary of the invention

[0005] The embodiment of the present invention provides a method and device for detecting chip connectivity, so as to solve the problem that detecting the connectivity of ports between modules in a chip is time-consuming and complicated in the prior art.

[0006] In the first aspect, an embodiment of the present invention provides a method for detecting chip connectivity, wherein the chip to be detected includes a first module to be detected and a second module to be detected, including the first module to be detected whose port attribute is an output port and the second module to be detected whose port attribute is an input port; the first module to be detected and the second module to be detected have a connection relationship; the output port of the first module to be detected is caused to output a sending signal through an assignment instruction; a receiving signal is obtained through the input port of the second module to be detected; if the sending signal of the first module to be detected is the same as the receiving signal of the second module to be detected, it is determined that the first module to be detected and the second module to be detected are connected.

[0007] In the embodiment of the present invention, by judging whether the sending signal of the first module to be detected is the same as the receiving signal of the second module to be detected, it can be more accurately determined whether the signal sent by the output port of the first module to be detected is obtained by the input port of the second module to be detected, and thus it can be more accurately determined whether the first module to be detected is connected to the second module to be detected.

[0008] Optionally, the assignment instructions are multiple assignment instructions that change in a time sequence; there is at least one group of adjacent assignment instructions that are different; if the sending signal of the first module to be detected is the same as the receiving signal of the second module to be detected, it is determined that the first module to be detected is connected to the second module to be detected, including: if the sending signal of the first module to be detected corresponding to each assignment instruction is the same as the receiving signal of the second module to be detected, it is determined that the first module to be detected is connected to the second module to be detected.

[0009] Optionally, the multiple assignment instructions are performed in a first timing sequence; the receiving signal is obtained through the input port of the second module to be detected, including: obtaining the receiving signal through the input port of the second module to be detected according to a second timing sequence; wherein the time difference between the output moment of each assignment instruction in the first timing sequence and the receiving moment in the second timing sequence is the same.

[0010] Optionally, it also includes: if the sending signal of the first module to be detected corresponding to each assignment instruction is not the same as the receiving signal of the second module to be detected, and there is at least one assignment instruction whose sending signal of the first module to be detected is the same as the receiving signal of the second module to be detected, then a prompt message is triggered; the prompt message is used to indicate retesting of the first module to be detected and the second module to be detected.

[0011] Optionally, before triggering the prompt information, the method further includes: determining, through a configuration file, that there is an indirect connection relationship between the first module to be detected and the second module to be detected or that the second module to be detected has a signal conversion function.

[0012] Optionally, causing the output port of the first module to be detected to output a sending signal through an assignment instruction, including: determining that the connection relationship between the first module to be detected and the second module to be detected is a selective connection; causing the output port of the first module to be detected to output a sending signal through a selection signal and an assignment instruction.

[0013] Optionally, causing the output port of the first module to be detected to output a sending signal through an assignment instruction, including: determining that the connection relationship between the first module to be detected and the second module to be detected is a control type connection; causing the output port of the first module to be detected to output a sending signal through a control signal and an assignment instruction.

[0014] In the second aspect, an embodiment of the present invention also provides a device for detecting the connectivity of a chip, wherein the chip to be detected includes a first module to be detected and a second module to be detected; an acquisition unit is used to acquire the first module to be detected whose port attribute is an output port and the second module to be detected whose port attribute is an input port; the first module to be detected and the second module to be detected have a connection relationship; a processing unit, through an assignment instruction, enables the output port of the first module to be detected to output a sending signal; acquires a receiving signal through the input port of the second module to be detected; if the sending signal of the first module to be detected is the same as the receiving signal of the second module to be detected, it is determined that the first module to be detected and the second module to be detected are connected.

[0015] Optionally, the assignment instructions are multiple assignment instructions that change in a time sequence; there is at least one group of adjacent assignment instructions that are different; the processing unit is specifically used to: if the sending signal of the first module to be detected corresponding to each assignment instruction is the same as the receiving signal of the second module to be detected, then it is determined that the first module to be detected is connected to the second module to be detected.

[0016] Optionally, the multiple assignment instructions are performed in a first timing sequence; the processing unit is specifically used to: obtain a received signal through the input port of the second module to be detected in a second timing sequence; wherein the time difference between the output moment of each assignment instruction in the first timing sequence and the receiving moment in the second timing sequence is the same.

[0017] Optionally, the processing unit is also used to: trigger a prompt message if the sending signal of the first module to be detected corresponding to each assignment instruction and the receiving signal of the second module to be detected are not all the same, and there is at least one assignment instruction in which the sending signal of the first module to be detected and the receiving signal of the second module to be detected are the same; the prompt message is used to indicate retesting of the first module to be detected and the second module to be detected.

[0018] Optionally, the processing unit is further used to: determine, through a configuration file, that there is an indirect connection relationship between the first module to be detected and the second module to be detected or that the second module to be detected has a signal conversion function.

[0019] Optionally, the processing unit is specifically used to: determine that the connection relationship between the first module to be detected and the second module to be detected is a selective connection; and enable the output port of the first module to be detected to output a sending signal through a selection signal and an assignment instruction.

[0020] Optionally, the processing unit is specifically used to: determine that the connection relationship between the first module to be detected and the second module to be detected is a control type connection; and enable the output port of the first module to be detected to output a sending signal through a control signal and an assignment instruction.

[0021] In a third aspect, an embodiment of the present invention further provides an electronic device, comprising at least one processor and at least one memory, wherein the memory stores a computer program, and when the program is executed by the processor, the processor executes the method for detecting chip connectivity in the above-mentioned first aspect.

[0022] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, wherein the storage medium stores a program, and when the program is run on a computer, the computer implements the method for detecting chip connectivity in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0024] Figure 1 A flow chart of a method for detecting chip connectivity provided by an embodiment of the present invention;

[0025] Figure 2 A schematic diagram of a direct connection type between modules provided in an embodiment of the present invention;

[0026] Figure 3 A schematic diagram of a shared connection between modules provided by an embodiment of the present invention;

[0027] Figure 4 A schematic diagram of a controlled connection between modules provided by an embodiment of the present invention;

[0028] Figure 5 A flow chart of a method for determining whether modules are connected provided by an embodiment of the present invention;

[0029] Figure 6 A schematic diagram of the structure of a device for detecting chip connectivity provided by an embodiment of the present invention;

[0030] Figure 7 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] In a possible scenario, since the cost of chip design is relatively high, it is necessary to use verification methods to discover defects and errors in chip design before mass production. In the chip verification process, a lot of work is to determine the connectivity of the ports between modules in the chip. The modules in the chip can be divided into two categories. The first type of module is a module that can send a signal with an identifier, and the second type of module is a module that sends a signal without an identifier. For example, if the chip to be tested includes module A and module B, where module A is a module that can send a signal with an identifier, that is, the first type of module, then the connectivity of the ports of module A and module B in the chip to be tested can be detected by a functional verification method. Generally speaking, module A sends a signal to module B, where the signal has an identifier that allows module B to execute instruction 1. After module B receives the signal, it will execute instruction 1 according to the signal, and determine whether module A and module B are connected by confirming whether module B executes instruction 1. However, this method requires a clear understanding of the working principles of module A and module B, and because it is necessary to verify whether the functions between module A and module B are intact, it also takes a lot of time, resulting in a waste of manpower and material resources.

[0033] For another example, if the chip to be tested includes module C and module D, where module C is a module that sends out a signal without an identification, that is, a second-class module, then the connectivity of the ports of module C and module D in the chip to be tested can be detected by manual verification. Specifically, the staff can determine whether module C and module D are connected by checking the code. However, the manual verification method will lead to large errors, low accuracy, and waste of manpower and material resources.

[0034] In summary, the embodiment of the present invention provides a method for detecting chip connectivity, which can realize simple and rapid determination of the connectivity of ports between modules in a chip.

[0035] like Figure 1 FIG. 1 is a flow chart of a method for detecting chip connectivity provided by an embodiment of the present invention, the method comprising the following steps:

[0036] Step 101: Acquire a first module to be detected whose port attribute is an output port and a second module to be detected whose port attribute is an input port.

[0037] In an embodiment of the present invention, the chip to be detected includes a plurality of modules to be detected, wherein each module to be detected corresponds to a port attribute. If it is necessary to determine the connectivity between a first module to be detected and a second module to be detected, then, first, the port attributes of the first module to be detected and the second module to be detected must be obtained. The port attribute of the first module to be detected is an output port, and the port attribute of the second module to be detected is an input port.

[0038] Step 102: Using an assignment instruction, the output port of the first module to be detected outputs a sending signal.

[0039] In the embodiment of the present invention, since the port attribute of the first module to be detected is an output port, the port of the first module to be detected will output a sending signal. Therefore, in order to detect the connectivity between the first module to be detected and the second module to be detected, it is necessary to use an assignment instruction to make the output port of the first module to be detected output a sending signal, so as to facilitate the subsequent comparison between the signal received by the input port of the second module to be detected and the sending signal of the first module to be detected, thereby determining the connectivity between the first module to be detected and the second module to be detected.

[0040] Step 103: Acquire a received signal through an input port of the second module to be detected.

[0041] In the embodiment of the present invention, the received signal of the second module to be detected is obtained through the input port of the second module to be detected, so as to compare the received signal with the transmitted signal to more accurately determine whether the first module to be detected and the second module to be detected are connected.

[0042] Step 104 , determining whether the signal sent by the first module to be detected is the same as the signal received by the second module to be detected, if so, executing step 105 , if not, executing step 106 .

[0043] In the embodiment of the present invention, if the transmission signal of the first module to be detected is the same as the reception signal of the second module to be detected, it means that the transmission signal output by the output port of the first module to be detected is sent to the input port of the second module to be detected. Therefore, it can be determined that the first module to be detected is connected to the second module to be detected. If the transmission signal of the first module to be detected is different from the reception signal of the second module to be detected, it means that the transmission signal of the first module to be detected is not sent to the input port of the second module to be detected. Therefore, it also means that the first module to be detected is not connected to the second module to be detected.

[0044] Step 105: Determine whether the first module to be detected is connected to the second module to be detected.

[0045] Step 106: Determine whether the first module to be detected is not connected to the second module to be detected.

[0046] It can be seen from the above steps 101 to 106 that by judging whether the sending signal of the first module to be detected is the same as the receiving signal of the second module to be detected, it can be more accurately determined whether the signal sent by the output port of the first module to be detected is obtained by the input port of the second module to be detected, and therefore it can be more accurately determined whether the first module to be detected is connected to the second module to be detected.

[0047] In the example of the present invention, in order to facilitate understanding of the present solution, the following introduces the connection method between three types of modules.

[0048] like Figure 2 FIG. 1 is a schematic diagram of a direct connection between modules provided by an embodiment of the present invention. For example, the chip to be detected includes module A and module B, wherein the port attribute of module A is an output port, and the port attribute of module B is an input port. Module A and module B are directly connected without any preconditions.

[0049] like Figure 3 As shown, it is a schematic diagram of a shared connection between modules provided by an embodiment of the present invention. For example, the chip to be detected includes module A, module B and module C, wherein the port attributes of module A and module C are the same, both are output ports, and the port attribute of module B is an input port. Among them, one of module A and module C can be selected to be connected to module B by selecting a signal. For example, if the selection signal is to select module A, module A is connected to module B, and module C is not connected to module B. If the selection signal is to select module C, module C is connected to module B, and module A is not connected to module B.

[0050] like Figure 4 As shown, it is a schematic diagram of a controlled connection between modules provided by an embodiment of the present invention. For example, the chip to be detected includes module A and module B, wherein the port attribute of module A is an output port, and the port attribute of module B is an input port. Whether module A and module B are connected can be determined by a control signal. If the control signal is in agreement with connection, module A and module B are connected. If the control signal is not in agreement with connection, module A and module B are not connected.

[0051] In the embodiment of the present invention, in order to facilitate understanding of the present solution, the present solution is introduced below by taking the interconnection mode between modules as a direct connection type. Since the output port of the first module to be detected is made to output a transmission signal through an assignment instruction, wherein the assignment instruction is a plurality of assignment instructions that change according to a timing sequence, wherein at least one group of adjacent assignment instructions is different, and the plurality of assignment instructions are performed according to a first timing sequence. For example, if there are three assignment instructions, they are arranged according to the first timing sequence, namely, the first assignment instruction, the second assignment instruction and the third assignment instruction. The moment corresponding to the first assignment instruction is the first moment, the moment corresponding to the second assignment instruction is the second moment, and the moment corresponding to the third assignment instruction is the third moment. Among them, the first assignment instruction is different from the second assignment instruction, and the second assignment instruction is different from the third assignment instruction. The input port of the second module to be detected obtains a received signal according to the second timing sequence. Among them, the time difference between the output moment of each assignment instruction in the first timing sequence and the receiving moment in the second timing sequence is the same. Corresponding to the above three assignment instructions, the input port of the second module to be detected will obtain three receiving signals, which are the first receiving signal, the second receiving signal and the third receiving signal according to the second timing sequence. Among them, the time corresponding to the first receiving signal is the fourth time, the time corresponding to the second receiving signal is the fifth time, and the time corresponding to the third receiving signal is the sixth time.

[0052] like Figure 5 FIG. 1 is a flow chart of a method for determining whether modules are connected provided by an embodiment of the present invention. The method comprises the following steps:

[0053] Step 501: at a first moment, using a first assignment instruction, the output port of a first module to be detected outputs a first sending signal.

[0054] In the embodiment of the present invention, at the first moment, the first assignment instruction causes the output port of the first module to be detected to output the first transmission signal. For example, the first moment is 10:00, and the first assignment instruction causes the output port of the first module to be detected to output the first transmission signal.

[0055] Step 502: At a fourth moment, a first received signal is acquired through an input port of a second module to be detected.

[0056] In the embodiment of the present invention, since the fourth moment is after the first moment, after the output port of the first module to be detected outputs the first transmission signal through the first assignment instruction, the input port of the second module to be detected acquires the first reception signal. For example, the fourth moment is 10:01, and the input port of the second module to be detected acquires the first reception signal.

[0057] Step 503, at the fourth moment, determine whether the first transmitted signal and the first received signal are the same, if so, execute step 504, if not, execute step 505.

[0058] In the embodiment of the present invention, if the first transmission signal is the same as the first reception signal, it means that there may be a connection between the first module to be detected and the second module to be detected, and it is necessary to combine with the subsequent to more accurately determine whether there is a connection. If the first transmission signal is different from the first reception signal, it means that the first transmission signal output by the output port of the first module to be detected is not sent to the input port of the second module to be detected, so it can be determined that the first module to be detected is not connected to the second module to be detected.

[0059] Step 504: at a second moment, the output port of the first module to be detected is caused to output a second sending signal through a second assignment instruction.

[0060] In the embodiment of the present invention, since it is determined at the fourth moment that the first transmission signal is the same as the first reception signal, in order to more accurately determine whether the first module to be detected is connected to the second module to be detected, it is necessary to use the second assignment instruction at the second moment to make the output port of the first module to be detected output the second transmission signal, and then facilitate the subsequent judgment of whether the second transmission signal and the second reception signal are the same. The second moment is after the fourth moment. For example, the second moment is 10:02, and the second assignment instruction causes the output port of the first module to be detected to output the second transmission signal.

[0061] Step 505: The first module to be detected is not connected to the second module to be detected.

[0062] Step 506: at a fifth moment, a second received signal is acquired through an input port of a second module to be detected.

[0063] In the embodiment of the present invention, the fifth moment is after the second moment, so when the second assignment instruction is passed, after the output port of the first module to be detected outputs the second transmission signal, the second reception signal is obtained through the input port of the second module to be detected. For example, the fifth module is 10:03, and the second reception signal is obtained through the input port of the second module to be detected.

[0064] Step 507 , at the fifth moment, determine whether the second transmitted signal and the second received signal are the same, if so, execute step 508 , if not, execute step 509 .

[0065] In the embodiment of the present invention, if the second transmission signal and the second reception signal are the same, it means that there may be a connection between the first module to be detected and the second module to be detected, and it is necessary to combine with the subsequent to more accurately determine whether there is a connection. If the second transmission signal and the second reception signal are not the same, it means that the first transmission signal output by the output port of the first module to be detected is not sent to the input port of the second module to be detected, so it can be determined that the first module to be detected is not connected to the second module to be detected.

[0066] Step 508: At a third moment, the output port of the first module to be detected is caused to output a third sending signal through a third assignment instruction.

[0067] In the embodiment of the present invention, since it is determined at the fifth moment that the first transmission signal is the same as the first reception signal, in order to more accurately determine whether the first module to be detected is connected to the second module to be detected, it is necessary to use the third assignment instruction at the third moment to make the output port of the first module to be detected output the third transmission signal, and then facilitate the subsequent judgment of whether the third transmission signal and the third reception signal are the same. The third moment is after the fifth moment. For example, the third moment is 10:04, and the third assignment instruction causes the output port of the first module to be detected to output the third transmission signal.

[0068] Step 509: The first module to be detected is not connected to the second module to be detected.

[0069] In an embodiment of the present invention, the first module to be detected and the second module to be detected are not connected, and then it is necessary to determine whether there is a connection relationship between the first module to be detected and the second module to be detected, and whether the second module to be detected has a signal conversion capability through a configuration file, wherein the signal conversion capability means that the second module to be detected can automatically change the signal during operation. If it is determined through the configuration file that there is an indirect connection relationship between the first module to be detected and the second module to be detected or the second module to be detected has a signal conversion function, a prompt message is triggered, wherein the prompt message is used to indicate that the first module to be detected and the second module to be detected are retested.

[0070] Step 510: At a sixth moment, a third received signal is acquired through an input port of the second module to be detected.

[0071] In the embodiment of the present invention, the sixth moment is after the third moment, so when the third assignment instruction is passed, after the output port of the first module to be detected outputs the third transmission signal, the third reception signal is obtained through the input port of the second module to be detected. For example, the sixth module is 10:05, and the third reception signal is obtained through the input port of the second module to be detected.

[0072] Step 511, at the sixth moment, determine whether the third transmitted signal and the third received signal are the same, if so, execute step 512, if not, execute step 513.

[0073] In an embodiment of the present invention, if the third sending signal and the third receiving signal are the same, it means that the first module to be detected is connected to the second module to be detected. If the third sending signal and the third receiving signal are different, it means that the third sending signal output by the output port of the first module to be detected is not sent to the input port of the second module to be detected. Therefore, it can be determined that the first module to be detected is not connected to the second module to be detected.

[0074] Step 512: The first module to be detected is connected to the second module to be detected.

[0075] Step 513: The first module to be detected is not connected to the second module to be detected.

[0076] In an embodiment of the present invention, the first module to be detected and the second module to be detected are not connected, and then it is necessary to determine whether there is a connection relationship between the first module to be detected and the second module to be detected, and whether the second module to be detected has a signal conversion capability through a configuration file, wherein the signal conversion capability means that the second module to be detected can automatically change the signal during operation. If it is determined through the configuration file that there is an indirect connection relationship between the first module to be detected and the second module to be detected or the second module to be detected has a signal conversion function, a prompt message is triggered, wherein the prompt message is used to indicate that the first module to be detected and the second module to be detected are retested.

[0077] It can be seen from the above steps 501 to 513 that multiple assignment instructions are executed according to the first timing sequence so that the output port of the first module to be detected outputs multiple transmission signals, so that the transmission signals are different in adjacent assignment instructions. In this way, multiple reception signals are obtained from the input port of the second module to be detected according to the second timing sequence, and then by judging whether the reception signal corresponding to each assignment instruction is the same as the transmission signal, it is possible to more accurately determine whether there is connectivity between the first module to be detected and the second module to be detected.

[0078] Based on the same technical concept as above, an embodiment of the present invention also provides a device for detecting chip connectivity, such as Figure 6As shown, the chip to be detected in the device 600 includes a first module to be detected and a second module to be detected; an acquisition unit 601 is used to acquire the first module to be detected whose port attribute is an output port and the second module to be detected whose port attribute is an input port; the first module to be detected and the second module to be detected have a connection relationship; a processing unit 602, through an assignment instruction, enables the output port of the first module to be detected to output a sending signal; obtains a receiving signal through the input port of the second module to be detected; if the sending signal of the first module to be detected is the same as the receiving signal of the second module to be detected, it is determined that the first module to be detected and the second module to be detected are connected.

[0079] Optionally, the assignment instructions are multiple assignment instructions that change in a time sequence; there is at least one group of adjacent assignment instructions that are different; the processing unit 602 is specifically used to: if the sending signal of the first module to be detected corresponding to each assignment instruction is the same as the receiving signal of the second module to be detected, then it is determined that the first module to be detected is connected to the second module to be detected.

[0080] Optionally, the multiple assignment instructions are performed in a first timing sequence; the processing unit 602 is specifically used to: obtain a received signal through the input port of the second module to be detected in a second timing sequence; wherein the time difference between the output moment of each assignment instruction in the first timing sequence and the receiving moment in the second timing sequence is the same.

[0081] Optionally, the processing unit 602 is also used to: trigger a prompt message if the sending signal of the first module to be detected corresponding to each assignment instruction is not the same as the receiving signal of the second module to be detected, and there is at least one assignment instruction in which the sending signal of the first module to be detected is the same as the receiving signal of the second module to be detected; the prompt message is used to indicate retesting of the first module to be detected and the second module to be detected.

[0082] Optionally, the processing unit 602 is further configured to: determine, through a configuration file, that an indirect connection relationship exists between the first module to be detected and the second module to be detected or that the second module to be detected has a signal conversion function.

[0083] Optionally, the processing unit 602 is specifically used to: determine that the connection relationship between the first module to be detected and the second module to be detected is a selective connection; and enable the output port of the first module to be detected to output a sending signal through a selection signal and an assignment instruction.

[0084] Optionally, the processing unit 602 is specifically used to: determine that the connection relationship between the first module to be detected and the second module to be detected is a control type connection; and enable the output port of the first module to be detected to output a sending signal through a control signal and an assignment instruction.

[0085] Based on the same technical concept, the embodiment of the present application also provides an electronic device, such as Figure 7 As shown, the electronic device 700 includes at least one processor 701 and a memory 702 connected to the at least one processor. The specific connection medium between the processor 701 and the memory 702 is not limited in the embodiment of the present application. Figure 7 For example, the processor 701 and the memory 702 are connected via a bus. The bus can be divided into an address bus, a data bus, a control bus, etc.

[0086] In the embodiment of the present application, the memory 702 stores instructions that can be executed by at least one processor 701. The at least one processor 701 can execute the steps included in the aforementioned recharging method by executing the instructions stored in the memory 702.

[0087] Among them, the processor 701 is the control center of the computing device, and can use various interfaces and lines to connect various parts of the computing device, and realize data processing by running or executing instructions stored in the memory 702 and calling data stored in the memory 702. Optionally, the processor 701 may include one or more processing units, and the processor 701 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface, and application programs, and the modem processor mainly processes the issuance of instructions. It is understandable that the above-mentioned modem processor may not be integrated into the processor 701. In some embodiments, the processor 701 and the memory 702 may be implemented on the same chip, and in some embodiments, they may also be implemented separately on independent chips.

[0088] The processor 701 may be a general-purpose processor, such as a central processing unit (CPU), a digital signal processor, an application-specific integrated circuit (ASIC), a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, and may implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present application. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the embodiment of the method for combining the recharge may be directly embodied as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.

[0089] The memory 702 is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs and modules. The memory 702 may include at least one type of storage medium, such as a flash memory, a hard disk, a multimedia card, a card-type memory, a random access memory (Random Access Memory, RAM), a static random access memory (Static Random Access Memory, SRAM), a programmable read-only memory (Programmable Read Only Memory, PROM), a read-only memory (Read Only Memory, ROM), an electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), a magnetic memory, a disk, an optical disk, etc. The memory 702 is any other medium that can be used to carry or store a desired program code in the form of an instruction or data structure and can be accessed by a computer, but is not limited thereto. The memory 702 in the embodiment of the present application can also be a circuit or any other device that can realize a storage function, for storing program instructions and / or data.

[0090] Based on the same technical concept, an embodiment of the present application also provides a computer-readable storage medium, which stores a computer program that can be executed by a computing device. When the program runs on the computing device, the computing device executes the steps of the above-mentioned recharging method.

[0091] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0092] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0093] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0094] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0095] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0096] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for detecting chip connectivity, characterized in that: The chip to be detected includes a first module to be detected and a second module to be detected, including: Acquire a first module to be detected whose port attribute is an output port and a second module to be detected whose port attribute is an input port; the first module to be detected and the second module to be detected have a connection relationship; Using an assignment instruction, the output port of the first module to be detected outputs a sending signal; Acquire a received signal through an input port of the second module to be detected; If the signal sent by the first module to be detected is the same as the signal received by the second module to be detected, it is determined that the first module to be detected is connected to the second module to be detected; The step of causing the output port of the first module to be detected to output a sending signal by assigning a value to the instruction includes: Determining that the connection relationship between the first module to be detected and the second module to be detected is a selective connection; Make the output port of the first module to be detected output a sending signal through a selection signal and an assignment instruction; or The step of causing the output port of the first module to be detected to output a sending signal by assigning a value to the instruction includes: Determining that the connection relationship between the first module to be detected and the second module to be detected is a control type connection; The output port of the first module to be detected is made to output a sending signal through a control signal and an assignment instruction.

2. The method according to claim 1, characterized in that The assignment instructions are multiple assignment instructions that change in time sequence; at least one group of adjacent assignment instructions are different; If the signal sent by the first module to be detected is the same as the signal received by the second module to be detected, determining that the first module to be detected is connected to the second module to be detected, comprising: If the sending signal of the first module to be detected and the receiving signal of the second module to be detected corresponding to each assignment instruction are the same, it is determined that the first module to be detected and the second module to be detected are connected.

3. The method according to claim 2, characterized in that The plurality of assignment instructions are performed in a first time sequence order; The step of acquiring a received signal through an input port of the second module to be detected includes: According to the second timing, a received signal is obtained through the input port of the second module to be detected; wherein the time difference between the output moment of each assignment instruction in the first timing and the reception moment in the second timing is the same.

4. The method according to claim 2, characterized in that Also includes: If the sending signal of the first module to be detected corresponding to each assignment instruction and the receiving signal of the second module to be detected are not all the same, and there is at least one assignment instruction whose sending signal of the first module to be detected and the receiving signal of the second module to be detected are the same, a prompt message is triggered; the prompt message is used to indicate retesting of the first module to be detected and the second module to be detected.

5. The method according to claim 4, characterized in that Before the prompt message is triggered, it also includes: Through the configuration file, it is determined that there is an indirect connection relationship between the first module to be detected and the second module to be detected or the second module to be detected has a signal conversion function.

6. A device for detecting chip connectivity, characterized in that: The chip to be detected includes a first module to be detected and a second module to be detected; An acquisition unit, used for acquiring a first module to be detected whose port attribute is an output port and a second module to be detected whose port attribute is an input port; the first module to be detected and the second module to be detected have a connection relationship; The processing unit causes the output port of the first module to be detected to output a sending signal through an assignment instruction; obtains a receiving signal through the input port of the second module to be detected; and determines that the first module to be detected is connected to the second module to be detected if the sending signal of the first module to be detected is the same as the receiving signal of the second module to be detected; The processing unit is further used to: determine that the connection relationship between the first module to be detected and the second module to be detected is a selective connection; Make the output port of the first module to be detected output a sending signal through a selection signal and an assignment instruction; The processing unit is further used to: determine that the connection relationship between the first module to be detected and the second module to be detected is a control type connection; The output port of the first module to be detected is made to output a sending signal through a control signal and an assignment instruction.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps of any one of the methods of claims 1-5 are implemented.

8. A computer-readable storage medium, characterized in that: It stores a computer program executable by a computer device, and when the program is run on the computer device, the computer device executes the steps of any method described in claims 1-5.

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