Memory testing method and device, electronic equipment and storage medium

Abstract

The application relates to a memory test method and device, electronic equipment and a storage medium. The method comprises the following steps: in response to a memory test request, extracting a target service scenario corresponding to a memory module in a to-be-tested device from the memory test request; determining a test environment description parameter according to the target service scenario, wherein the test environment description parameter represents a target memory access mode and load pressure condition corresponding to the memory module; and obtaining a first memory test result of the memory module in a test environment corresponding to the test environment description parameter. The application improves the pertinence of memory testing and the accuracy of memory test results. The embodiments of the application can be applied to various scenes such as cloud technology, artificial intelligence, intelligent transportation and intelligent entertainment.

Description

Technical Field

[0001] This application relates to the field of Internet communication technology, and in particular to a memory testing method, apparatus, electronic device and storage medium. Background Technology

[0002] With the development of internet communication technology, various internet products have emerged in an endless stream, and the user experience they provide is constantly improving. The normal use of internet products requires the support of related equipment (such as servers). When selecting and maintaining this equipment, testing is often necessary, such as testing the memory modules within it. In related technologies, memory testing platforms often provide memory testing services, but the obtained memory test results are limited by the platform's preset testing methods. This affects the accuracy of the memory test results. Therefore, a more accurate and effective memory testing solution is needed. Summary of the Invention

[0003] To address at least one of the aforementioned technical problems, this application provides a memory testing method, apparatus, electronic device, and storage medium:

[0004] According to a first aspect of this application, a memory testing method is provided, the method comprising:

[0005] In response to a memory test request, the target business scenario corresponding to the memory module in the device under test is extracted from the memory test request;

[0006] The test environment description parameters are determined based on the target business scenario. The test environment description parameters characterize the target memory access mode and load pressure of the memory module.

[0007] Obtain the first memory test result of the memory module under the test environment corresponding to the test environment description parameters.

[0008] According to a second aspect of this application, a memory testing apparatus is provided, the apparatus comprising:

[0009] Scenario determination module: used to extract the target business scenario corresponding to the memory module in the device under test from the memory test request in response to the memory test request;

[0010] Parameter determination module: used to determine test environment description parameters based on the target business scenario, wherein the test environment description parameters characterize the target memory access mode and load pressure of the memory module;

[0011] Result acquisition module: used to acquire the first memory test result of the memory module in the test environment corresponding to the test environment description parameters.

[0012] According to a third aspect of this application, an electronic device is provided, the electronic device including at least one processor and a memory communicatively connected to the at least one processor; wherein the memory stores at least one instruction or at least one program, the at least one instruction or at least one program being loaded and executed by the at least one processor to implement the memory testing method as described in the first aspect.

[0013] According to a fourth aspect of this application, a computer-readable storage medium is provided, wherein at least one instruction or at least one program is stored therein, the at least one instruction or at least one program being loaded and executed by a processor to implement the memory method as described in the first aspect.

[0014] According to a fifth aspect of this application, a computer program product is provided, the computer program product comprising at least one instruction or at least one program segment, the at least one instruction or at least one program segment being loaded and executed by a processor to implement the memory testing method as described in the first aspect.

[0015] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application.

[0016] Implementing this application will have the following beneficial effects:

[0017] In memory testing, test environment description parameters are determined based on the target business scenario corresponding to the memory modules in the device under test. This allows for the acquisition of memory test results within the corresponding test environment, taking into account the needs of the business scenario dimension and reflecting this in the test environment. This improves the targeting and accuracy of memory test results. Furthermore, when reflecting the target business scenario in the test environment, attention is paid to the target memory access patterns and load conditions corresponding to the memory modules. Selecting more representative parameters increases the speed of test environment construction, thereby improving the efficiency of memory testing.

[0018] Other features and aspects of this application will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0019] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1This diagram illustrates an application environment according to an embodiment of the present application.

[0021] Figure 2 A flowchart illustrating a memory testing method according to an embodiment of this application is shown;

[0022] Figure 3 A schematic diagram illustrating the process of performing memory testing on a simulated device according to an embodiment of this application is shown;

[0023] Figure 4 A schematic diagram illustrating the process of obtaining target memory test results according to an embodiment of this application is shown;

[0024] Figure 5 This diagram illustrates a process for obtaining target memory test results based on a first difference and a second difference corresponding to each sub-environment, according to an embodiment of this application.

[0025] Figure 6 A schematic diagram showing an interface for displaying test results of a target memory according to an embodiment of this application;

[0026] Figure 7 This diagram illustrates a flowchart of a memory performance comparison between two systems under test according to an embodiment of this application.

[0027] Figure 8 A flowchart illustrating the process of obtaining target memory test results according to an embodiment of this application is also shown;

[0028] Figure 9 A schematic diagram illustrating the principle of adjusting load pressure using request intervals according to an embodiment of this application is shown;

[0029] Figure 10 A schematic diagram illustrating the memory performance indicators under different load conditions according to embodiments of this application is shown.

[0030] Figure 11 The diagram also illustrates the performance of memory performance indicators under different load conditions according to embodiments of this application.

[0031] Figure 12 A comparison chart of memory performance of different models of devices with the same specifications and operating system according to embodiments of this application is shown.

[0032] Figure 13 A comparison chart of memory performance of different specifications of the same model and operating system according to an embodiment of this application is shown.

[0033] Figure 14 A comparison chart of memory performance of devices of the same model and specifications but different operating systems according to embodiments of this application is shown.

[0034] Figure 15 This diagram illustrates a device block diagram according to an embodiment of the present application;

[0035] Figure 16 A schematic diagram of an electronic device according to an embodiment of this application is shown. Detailed Implementation

[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0037] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or server that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0038] Various exemplary embodiments, features, and aspects of this application will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0039] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0040] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0041] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed description. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0042] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0043] Benchmarking programs: Programs used to measure the highest actual performance of a machine's hardware. They include micro-benchmarking programs and macro-benchmarking programs. Micro-benchmarking programs are mainly used to measure a specific aspect of the performance of a computer system, while macro-benchmarking programs are mainly used to measure the overall performance of a computer system.

[0044] Reference model: The model under test used as a performance baseline.

[0045] System under test (SUT): The system currently being tested.

[0046] Please see Figure 1 , Figure 1 The diagram illustrates an application environment according to an embodiment of this application. The application environment may include a client 10 and a server 20. The client 10 and server 20 can be directly or indirectly connected via wired or wireless communication. A user can send a memory test request to the server 20 through the client 10. The server 20 receives the memory test request, extracts the target business scenario corresponding to the memory module in the device under test from the memory test request, then determines test environment description parameters based on the target business scenario. These test environment description parameters characterize the target memory access mode and load pressure corresponding to the memory module. Finally, the server obtains the memory test results of the memory module under the test environment corresponding to the test environment description parameters. It should be noted that... Figure 1 This is just one example.

[0047] Client 10 can be a physical device such as a smartphone, computer (e.g., desktop computer, tablet, laptop), augmented reality (AR) / virtual reality (VR) device, digital assistant, smart voice interaction device (e.g., smart speaker), smart wearable device, smart home appliance, in-vehicle terminal, etc., or it can be software running on the physical device, such as a computer program. The operating system corresponding to the client can be Android, iOS (a mobile operating system developed by Apple), Linux (an operating system), Microsoft Windows, etc.

[0048] The server-side component 20 can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms. The server may include network communication units, processors, and memory, etc. The server-side component can provide backend services to the corresponding clients.

[0049] In practical applications, the client 10 and server 20 described above can be components of a memory testing platform. Server 20 can embed memory test results into a preset template to obtain page data; then, it sends the page data to client 10, enabling client 10 to display the target page based on the page data. This allows users to more intuitively understand the memory test results through the target page displayed by client 10. The application of preset templates contributes to the standardization and readability of the front-end display page.

[0050] It should be noted that for memory test requests and memory test results that are related to user information, when the embodiments of this application are applied to specific products or technologies, user permission or consent is required, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0051] Figure 2 This diagram illustrates a flow chart of a memory testing method according to an embodiment of this application. Figure 2 As shown, the method includes:

[0052] S201: In response to a memory test request, extract the target business scenario corresponding to the memory module in the device under test from the memory test request;

[0053] In this embodiment, in response to a memory test request, the server extracts the target business scenario corresponding to the memory module in the device under test from the memory test request. The memory test request reveals that the memory module in the device under test is the test target, and the target business scenario is the basis for determining the test environment.

[0054] Memory test requests can be generated in the following ways: 1) The client-provided interactive interface has relevant controls for generating memory test requests, and the user triggers these controls to generate the memory test request. Correspondingly, the client sends the memory test request to the server. 2) The server-provided interactive interface has relevant controls for generating memory test requests, and the user triggers these controls to generate the memory test request. Here, the relevant controls in 1) and 2) may include a first control indicating the input / selection of information about the device under test, and a second control indicating the input / selection of parameters describing the business scenario. A memory test request may include at least one piece of information about the device under test that is input or selected, and at least one parameter describing the business scenario that is input or selected. The at least one parameter describing the business scenario represents the target business scenario.

[0055] The device under test can be a server, such as a physical server or a cloud server. It can also be a mobile phone, computer, etc. The target business scenario reflects the testing requirements of the memory module in the device under test in terms of business scenarios. That is, the target business scenario can be the current application business scenario of the memory module in the device under test, the historical application business scenario of the memory module in the device under test, or the future application business scenario of the memory module in the device under test.

[0056] It should be noted that the memory module here can refer to all the memory of the device under test, or it can refer to a portion of the memory of the device under test. In practical applications, if it refers to a portion of the memory of the device under test, the identification information of that portion of the memory can be incorporated when generating the memory test request.

[0057] S202: Determine the test environment description parameters according to the target business scenario. The test environment description parameters characterize the target memory access mode and load pressure of the memory module.

[0058] In this embodiment, the server determines the test environment description parameters based on the target business scenario. Memory test performance is affected by the test environment. For the same device memory, memory test results often differ under different test environments. Determining the test environment description parameters based on the test requirements of the business scenario is beneficial for subsequently building the corresponding test environment based on these parameters, thereby improving the accuracy and effectiveness of memory test results.

[0059] For the memory module in the device under test, the target business scenario can be determined by the device's operating status and the programs running on it. It can be understood that the target business scenario is more about the device under test as a whole, and the memory module, as a part of this whole, is affected by the target business scenario. The operating status of the device under test can include at least one of the following: CPU status, battery level, network status, temperature status, and screen brightness. The programs running on the device under test can provide program attribute information and program running status information. Program attribute information can include at least one of the following: program type and program version. Program running status information can indicate at least one of the following: foreground / background running status, program access latency, and program access frequency.

[0060] When determining the test environment description parameters based on the target business scenario, it is necessary to consider the relationship between the operating status of the device under test and the memory modules within the device under test, as well as the relationship between the program running on the device under test and the memory modules within the device under test. This application focuses on determining information related to the access patterns and load pressure of the memory modules from these relationships, selecting more representative parameter factors, and thus balancing the accuracy and efficiency of the test environment in a technically sound manner.

[0061] In one embodiment, the memory access mode characterizes the pattern of memory access, and the dimensions involved may include at least one of the following: the presence of read and write operations, the allocation ratio of read and write operations, and the order attribute of read and write operations. The selection of these dimensions facilitates a more granular definition of the memory access mode and enables effective evaluation of memory performance. The presence of read and write operations can include three cases: only read operations exist (read-only), only write operations exist (write-only), and both read and write operations exist simultaneously. The allocation ratio of read and write operations is often for the case of simultaneous read and write operations, and can be proportionally allocated based on operation duration, operation speed, etc. The order attribute of read and write operations can be applied to the three cases of read-only, write-only, and simultaneous read and write operations. The order attribute is used to characterize whether read and write operations access memory sequentially. If the accessed memory addresses are contiguous, the order attribute indicates sequential access; otherwise, the order attribute indicates random access.

[0062] For example, before determining the test environment description parameters according to the target business scenario, the method may further include the following steps: First, based on the target business scenario, determine the operation characteristics of reading and writing operations on the memory module, wherein the operation characteristics are at least one of the following: operation time characteristics, operation speed characteristics, and operation sequence characteristics; then, determine the target memory access mode based on the operation characteristics.

[0063] Memory access patterns are largely influenced by specific business scenarios, and the memory access patterns involved vary across different business scenarios. This study determines the read / write operation characteristics used to define the target memory access pattern based on the target business scenario. This facilitates the accurate reflection of memory access patterns under specific business scenarios in the test environment, thereby ensuring the relevance of memory test results to the target business scenario.

[0064] The operation time characteristics involve both read and write operations. Read operation time characteristics characterize the time-dimensional features of read operations targeting a memory module, while write operation time characteristics characterize the time-dimensional features of write operations targeting a memory module. For example, behavioral data of read (or write) operations are acquired at predetermined time intervals. These predetermined time intervals can be equal or unequal. Based on the behavioral data of read (or write) operations acquired at multiple predetermined time intervals, the execution duration of read (or write) operations within a predetermined time window, the proportion of execution time for each read (or write) operation, and the execution time interval between two adjacent read (or write) operations are determined. A predetermined time window includes at least one predetermined time interval.

[0065] The operation speed characteristics involve both read and write operations. Read operation speed characteristics characterize the speed-related features of read operations on the memory module, such as the maximum read speed, minimum read speed, average read speed, and median read speed within the aforementioned predetermined time window. Write operation speed characteristics characterize the speed-related features of write operations on the memory module, such as the maximum write speed, minimum write speed, average write speed, and median write speed within the aforementioned predetermined time window.

[0066] The operation sequence characteristics involve both read and write operations. These characteristics describe whether read or write operations access memory modules sequentially. For example, within the predetermined time window, they determine the number of sequential read accesses, the number of random read accesses, and the ratio of sequential to random read accesses. Similarly, within the predetermined time window, they determine the number of sequential write accesses, the number of random write accesses, and the ratio of sequential to random write accesses.

[0067] Based on the above introduction to memory access modes, the operational characteristics of read and write operations on memory modules are determined, including whether read operations exist, their timing characteristics, speed characteristics, and order characteristics. Similarly, the existence, timing, speed, and order characteristics of write operations are also determined. The presence and write operations determine the read / write operation settings. The timing (or speed) and timing (or speed) of read and write operations determine the allocation ratio of read and write operations. The order characteristics of read and write operations determine the read / write operation sequence. Accordingly, the target memory access mode can be determined using these factors.

[0068] In practical applications, algorithms can be used to set the presence and allocation ratio of read and write operations under different memory access modes, as shown in Table 1 below:

[0069]

[0070] Table 1

[0071] Furthermore, a set of preset memory access modes can be set, which can include basic memory access modes and extended memory access modes. A test environment built based on basic memory access modes typically covers fundamental scenarios, facilitating basic evaluation of device memory performance. A test environment built based on extended memory access modes allows for more personalized and flexible evaluation of device memory performance. This is because such test environments often cover boundary scenarios (extreme scenarios) and special scenarios (scenarios beyond the basic and boundary scenarios), and correspondingly, boundary and special values ​​for memory performance evaluation can be collected during the test. As shown in Table 2 below, the set of preset memory access modes can be differentiated from a scenario perspective. This differentiation is set based on historical feedback and business needs and can be flexibly adjusted according to actual requirements.

[0072]

[0073]

[0074] Table 2

[0075] For the applications listed in Table 2 above, at least one basic scenario can be selected from the three basic scenarios mentioned above, as needed. It should be understood that the test cases corresponding to each preset memory access mode in the preset memory access mode set are pre-set. A target preset memory access mode that matches the target memory access mode can be selected from the preset memory access mode set, and then the test cases corresponding to the target preset memory access mode can be used to build the test environment to improve memory testing efficiency.

[0076] In one embodiment, the load pressure situation characterizes the load pressure borne by the memory, such as the size of the data volume of the tasks being handled and the changes in the data volume of the tasks being handled. If a task indicates that read and write operations are to be performed on the memory, the size of the number of tasks being handled can characterize the number of read and write operations involved within a first preset time period, and the changes in the number of tasks being handled can characterize the fluctuations in the size of the number of read and write operations involved within two adjacent second preset time periods.

[0077] In memory performance evaluations of related technologies, the focus is typically only on the best performance achievable by the test target, such as maximum bandwidth capacity or minimum network latency. However, it's crucial to understand that while throughput metrics improve with increasing load, latency metrics deteriorate. This is because increased load requires the test target to process more transactions simultaneously, leading to conflicts and longer queue times, thus increasing the latency required for individual transactions. Therefore, it's essential to consider the load conditions determined by the target business scenario.

[0078] Combining the scenarios mentioned above (such as basic scenarios, boundary scenarios, and special scenarios), such as Figure 10 As shown, in a specific test scenario, the relationship between memory bandwidth and memory access latency changes with varying load pressure. This relationship can be divided into the following three stages:

[0079] 1) Near idle state: When the load pressure is low, the memory bandwidth utilization is low, and the memory access latency does not change with the change of memory bandwidth, which is similar to the memory access latency in the completely idle state.

[0080] 2) Gradual increase in load: As the load pressure gradually increases, the memory bandwidth utilization rate becomes higher and higher. Memory access requests need to bear additional queuing and waiting delays, resulting in the overall memory access latency gradually increasing with the memory bandwidth.

[0081] 3) Approaching maximum load: When the load pressure gradually reaches its maximum, the memory bandwidth utilization is already close to the highest level. The increase in load pressure will not significantly increase memory bandwidth as before, but it will increase memory access latency.

[0082] S203: Obtain the first memory test result of the memory module under the test environment corresponding to the test environment description parameters.

[0083] In this embodiment, the server obtains the first memory test result of the memory module in the test environment corresponding to the test environment description parameters. The memory test can be performed directly on the device under test or on a corresponding simulated device. The server can perform the memory test on the device under test or the simulated device based on the test environment description parameters to obtain the memory test result; alternatively, the server can send a memory test command to other execution devices, which will then perform the memory test on the device under test or the simulated device based on the test environment description parameters and return the memory test result to the server. The memory test command carries the test environment description parameters and the device information of the device under test. It should be noted that the following content regarding test environment construction applies to both the server and other execution devices.

[0084] Many factors influence overall memory performance, including memory frequency, memory capacity, memory bandwidth, memory link latency (CAS Latency, cycle), and memory access latency. To fully demonstrate memory performance under different test environments, memory bandwidth and memory access latency are chosen as core metrics for measuring memory performance. The first memory test results and the second memory test results below can include metrics reflecting memory performance, such as memory bandwidth and memory access latency.

[0085] In one embodiment, such as Figure 3 As shown, before obtaining the first memory test result of the memory module under the test environment corresponding to the test environment description parameters, the method further includes:

[0086] S301: Determine the corresponding simulation device based on the device information of the device under test;

[0087] S302: Construct a corresponding test environment based on the test environment description parameters to test the memory module in the simulation device and obtain the second memory test result of the memory module in the simulation device;

[0088] S303: The second memory test result is determined as the first memory test result.

[0089] Using simulated devices for memory testing and applying the results from these simulated devices to the memory testing results of the device under test improves the convenience and applicability of memory testing. The corresponding simulated device is determined based on the device information of the device under test; for example, a device of the same model as the device under test can be used as the simulated device. The device under test can be a physical machine or a virtual machine. Similarly, the simulated device can be either a physical machine or a virtual machine. Since a target business scenario can correspond to at least one target memory access mode and at least one load stress condition, the test environment constructed based on the test environment description parameters can involve at least one sub-environment, and the memory module testing will be performed in each sub-environment. For example, target memory access mode i represents the i-th target memory access mode, and the total number of target memory access modes is N. Load stress condition j represents the j-th load stress condition, and the total number of load stress conditions is M. Therefore, the test environment includes M*N sub-environments.

[0090] Based on the aforementioned step S202, the test environment description parameters are determined to construct the corresponding test environment. This can be achieved by constructing the test environment from two aspects: the target memory access mode and the load stress conditions represented by the test environment description parameters. Specifically, constructing the corresponding test environment based on the test environment description parameters may include the following steps: First, limiting access to the memory modules in the simulated device based on the target memory access mode; then, in the presence of at least two load stress conditions, setting the frequency of memory access requests issued by the central processing unit in the simulated device based on the load stress conditions.

[0091] Such a testing environment can present and reproduce the situations that memory modules face under the target business scenario, thereby improving the accuracy of memory testing. The target memory access pattern, as an access constraint criterion for the memory module, can restrict the existence of read / write operations, the allocation ratio of read / write operations, and the order of read / write operations. These constraints can be implemented using the algorithms in Table 1. The frequency of memory access requests is used to represent the changes in the number of tasks and transactions under at least two load conditions, making control more convenient and accurate.

[0092] In practical applications, 1) different load conditions are more conducive to a comprehensive and holistic evaluation of memory performance. If the number of load conditions corresponding to the target business scenario is less than the threshold, additional load conditions can be added to enrich the testing environment. 2) Load pressure can be adjusted by controlling the frequency of memory access requests issued by the central processing unit. Specifically, this can be achieved by setting the request interval (Inject Delay) between different memory access requests. (See reference...) Figure 9Combining the three states mentioned in step S202 above, the request interval can be set using the following cycle values, such as: near idle state ∈ {2, 8, 15, 50, 100}; gradually increasing pressure state ∈ {200, 300, 400, 500, 700, 1000, 1300}; near maximum load state ∈ {1700, 2500, 3500, 5000, 9000, 20000}.

[0093] In one embodiment, such as Figure 4 , 8 As shown, after obtaining the first memory test result of the memory module in the test environment corresponding to the test environment description parameters, the method further includes:

[0094] S401: Extract memory bandwidth information and memory access latency information from the first memory test results;

[0095] S402: Based on the difference between the memory bandwidth information and the baseline memory bandwidth, and the difference between the memory access latency information and the baseline memory access latency, the target memory test result is obtained. The baseline memory bandwidth and the baseline memory access latency are obtained by performing memory tests on a preset device. The environment for performing memory tests on the preset device is constructed based on the test environment description parameters.

[0096] The first memory test result represents the test result of a single memory module and is relatively independent. The target memory test result represents a comparison of the test results of two memory modules, focusing more on the differences in memory performance between the two memory modules under the same test environment. By selecting a preset device as the comparison object, the target memory test results can more intuitively demonstrate the memory performance of the device under test.

[0097] The preset device can be a pre-configured device of the device under test. It can also be a similar device that is associated with the device under test, such as having similar configurations or versions. In cases where the memory test request indicates at least two devices under test, the preset device can be any one of those devices, or it can be the device with the worst memory performance among the two devices, such as the device with worse memory bandwidth and memory access latency in the corresponding first memory test results. Figure 11 As shown, Figure 11This diagram illustrates the performance of two devices with different memory performance characteristics under various memory access modes and load conditions. The X-axis represents memory access latency (in nanoseconds), and the Y-axis represents memory bandwidth (in MB / s). The memory performance difference between the two devices can be represented by memory latency and memory bandwidth. For example, with the same memory access latency, machine1 (device 1) has better memory bandwidth than machine2 (device 2).

[0098] The differences between memory bandwidth information and the baseline memory bandwidth, and the differences between memory access latency information and the baseline memory access latency, can be characterized by differences, ratios, etc. The target memory test results are a fusion of these two types of differences.

[0099] Furthermore, in the presence of at least two target memory access modes and at least two load stress conditions, the test environment determined based on the test environment description parameters includes a target number of sub-environments, wherein the target number is the product of the total number of target memory access modes and the total number of load stress conditions, the baseline memory bandwidth includes the sub-baseline bandwidth of each sub-environment, and the baseline memory access latency includes the sub-baseline latency of each sub-environment.

[0100] Accordingly, the step of extracting memory bandwidth information and memory access latency information from the first memory test results may include the following steps: extracting sub-bandwidth information and sub-latency information for each sub-environment from the first memory test results;

[0101] The process of obtaining the target memory test result based on the difference between the memory bandwidth information and the baseline memory bandwidth, and the difference between the memory access latency information and the baseline memory access latency, may include the following steps: First, for each sub-environment, determine the first difference between the sub-bandwidth information and the sub-baseline bandwidth in the sub-environment, and determine the second difference between the sub-latency information and the sub-baseline latency in the sub-environment; then, based on the first difference and the second difference corresponding to each sub-environment, obtain the target memory test result.

[0102] For example, target memory access mode i represents the i-th target memory access mode, and the total number of target memory access modes is N. Load stress j represents the j-th load stress, and the total number of load stresses is M. Then, the test environment includes M*N sub-environments, and sub-environment k represents the k-th sub-environment.

[0103] For the device under test (SUT), the sub-bandwidth information under sub-environment k can be represented by throughput (SUT, k) (i.e., Throughput(SUT, k)), and the sub-latency information under sub-environment k can be represented by latency (SUT, k) (i.e., Latency(SUT, k)). For the preset device (Ref), the sub-bandwidth information under sub-environment k can be represented by throughput (Ref, k) (i.e., Throughput(Ref, k)), and the sub-latency information under sub-environment k can be represented by latency (Ref, k) (i.e., Latency(Ref, k)).

[0104] The first difference corresponding to sub-environment k can be expressed as: The second difference corresponding to sub-environment k can be expressed as: By fusing all first and second differences at the sub-environment level to obtain the target memory test results, this finer-grained difference determination helps improve the accuracy of the target memory test results.

[0105] The following section will provide a detailed introduction to the integration of differences in sub-environment dimensions. For example... Figure 5 As shown, each load stress condition corresponds to an environment description dimension. The target memory test result is obtained based on the first difference and the second difference corresponding to each sub-environment, including:

[0106] S501: Based on the first difference corresponding to each sub-environment, for each environment description dimension, determine the first difference representation under the environment description dimension, and based on the first difference representation corresponding to each environment description dimension, obtain the bandwidth difference representation.

[0107] S502: Based on the second difference corresponding to each of the sub-environments, for each of the environment description dimensions, determine the second difference representation under the environment description dimension, and based on the second difference representation corresponding to each of the environment description dimensions, obtain the delay difference representation;

[0108] S503: Based on the bandwidth difference characterization and the latency difference characterization, the target memory test results are obtained.

[0109] Steps S501 and S502 can be viewed as an aggregation of metrics related to load stress. Continuing with the example above, bandwidth difference characterization... Delay difference characterization in This represents the first difference representation under the environmental description dimension j. This represents the second difference representation under the environmental description dimension j. The bandwidth difference representation and latency difference representation, as the aggregation result, are fused to obtain the target memory test result. Considering the difference between memory bandwidth and memory access latency, the difference data under the same type of indicator are aggregated first, and then the aggregation results of the two types of indicators are fused. This approach balances the accuracy and efficiency of obtaining the target memory test result.

[0110] When fusing the aggregation results of the two types of indicators, a second round of index aggregation based on the memory access mode dimension can be performed on the aggregation results. That is, each target memory access mode corresponds to a memory access mode dimension. Obtaining the target memory test result based on the bandwidth difference representation and the latency difference representation includes: first, determining the sub-bandwidth difference representation under each memory access mode dimension from the bandwidth difference representation, and obtaining the target bandwidth difference representation based on the sub-bandwidth difference representation under each memory access mode dimension; then, determining the sub-latency difference representation under each memory access mode dimension from the latency difference representation, and obtaining the target latency difference representation based on the sub-latency difference representation under each memory access mode dimension; and finally, obtaining the target memory test result based on the target bandwidth difference representation and the target latency difference representation.

[0111] Using the example above, the target bandwidth difference is characterized. Target delay difference characterization in This represents the sub-bandwidth difference under memory access mode dimension i. This represents the sub-latency difference characterization under memory access mode dimension i. The target memory test results can be represented as follows:

[0112]

[0113] It should be noted that, 1) from an application perspective, the importance of memory bandwidth and access latency varies depending on the specific application; different workloads have different sensitivities to memory bandwidth and memory access latency. For example, high-performance computing workloads are more sensitive to bandwidth, while online transaction processing (OLTP) services are more sensitive to memory access latency. When memory performance evaluation has a clearly defined workload, the impact of memory bandwidth and memory access latency on overall performance can be analyzed by characterizing the load features, thereby determining the weight of the comprehensive evaluation value. Accordingly, the target memory test results can be expressed as follows: Where x represents the weight of the target bandwidth difference representation and y represents the weight of the target latency difference representation.

[0114] 2) In some cases, you can choose only one of memory bandwidth or memory access latency for memory performance evaluation, such as setting x or y to 0 in 1) above.

[0115] 3) The calculation process described above, from the first memory test result to the target memory test result, can also be applied to the evaluation of network performance, storage performance, etc. For example, for network performance evaluation, after collecting network bandwidth and network latency under different test dimensions, a similar method can be used to comprehensively evaluate network performance. For storage performance evaluation, after collecting the number of read / write operations per second (IOPS) and latency under different test dimensions, a similar method can be used to comprehensively evaluate storage performance.

[0116] In practical applications, the aforementioned differences and their representations can refer to the performance improvement ratio of the tested device relative to a preset device with worse memory performance. Whether it's the aggregation of indicators based on load stress or memory access patterns, the geometric mean can be used for calculation. The multiplicative effect in speedup calculation skews the distribution, resulting in a logarithmic distribution, while the additive effect ensures a symmetrical frequency distribution, resulting in a normal distribution. The most accurate way to calculate the mean of a log-normal distribution is the geometric mean. The geometric mean transforms the overall data into a logarithmic form and calculates the result in a normal distribution, thus obtaining a mean distribution that better reflects the overall data.

[0117] Taking the system under test (such as the server resources used for performance evaluation) as the device under test and the reference model (such as the model under test used as a performance baseline) as the preset device, the performance index data of the system under test under different load pressures in a single test scenario (corresponding to the target memory access mode mentioned above) are collected by benchmark testing tools (such as micro-benchmark programs). The collection results are shown in Table 3 below: Reference model, used to calculate the performance speedup ratio with other systems under test.

[0118]

[0119] Table 3

[0120] The results obtained from the data collection in Table 3 above and the data collection results of the reference model are shown in Table 4 below:

[0121]

[0122]

[0123] Table 4

[0124] The overall speedup ratio of throughput (corresponding to the sub-bandwidth difference representation) and the overall speedup ratio of latency (corresponding to the sub-latency difference representation) of the tested system in a single scenario are obtained through the above calculation method, as shown in Table 5 below. It should be noted that the test scenarios here represent different target memory access mode scenarios.

[0125]

[0126] Table 5

[0127] Furthermore, when the memory test request indicates at least two devices under test, the preset device can be a pre-configured device for any of the devices under test, such as a device known to have poor memory performance. This allows the same preset device to be used when evaluating the memory performance of both devices. For example, the ratio of the target memory test result of system under test 1 to the target memory test result of system under test 2 can be expressed as follows:

[0128]

[0129] This ratio calculation allows for a more intuitive and readable evaluation of the memory performance of two tested systems. Figure 7 The provided diagram illustrates the implementation.

[0130] The memory testing scheme provided in this application provides a reference for selecting test scenarios in memory performance evaluation. It filters out the main scenarios affecting memory performance from numerous test scenarios, thus more comprehensively reflecting the overall performance of the memory module. This scheme can provide comprehensive performance evaluation results for memory performance comparison (such as the target memory test results mentioned above). It aggregates and calculates performance indicator data from numerous test scenarios through a comprehensive evaluation method, thereby providing a more intuitive comparison of the overall performance differences of the memory modules. This scheme can also save testing time for memory performance evaluation by dividing test scenarios and selecting more representative scenarios, reducing the additional testing time overhead caused by repeated testing or incomplete testing. Figure 6 The interface displays the comprehensive performance evaluation results. Furthermore, a performance ranking feature can be provided when displaying the comprehensive performance evaluation results for existing models. This allows for a comprehensive comparison of memory performance rankings, avoiding erroneous conclusions drawn from judging performance based on data from a single test scenario. Figure 12-14 The table below shows a comparison of memory performance across different dimensions for the models listed in Table 5, using comprehensive performance evaluation results. Figure 12 Pay attention to comparing the memory performance differences between different models of devices with the same specifications and operating system. Figure 13 Pay attention to comparing the memory performance differences between devices of the same model and operating system but with different specifications. Figure 14Pay attention to the differences in memory performance between devices of the same model and specifications but with different operating systems.

[0131]

[0132]

[0133] Table 6

[0134] As can be seen from the technical solutions provided in the embodiments of this application above, in memory testing, the embodiments of this application determine the test environment description parameters based on the target business scenario corresponding to the memory module in the device under test, so as to obtain the memory test results in the test environment corresponding to the test environment description parameters. This takes into account the needs of the business scenario dimension and reflects this in the test environment, improving the targeting of memory testing and the accuracy of memory test results. At the same time, when reflecting the target business scenario in the test environment, attention is paid to the target memory access mode and load pressure corresponding to the memory module, selecting more representative parameter factors, which improves the speed of test environment construction and thus improves the efficiency of memory testing.

[0135] This application also provides a memory testing device, such as... Figure 15 As shown, the memory testing device 150 includes:

[0136] Scene determination module 1501: In response to a memory test request, extracts the target business scene corresponding to the memory module in the device under test from the memory test request;

[0137] Parameter determination module 1502: used to determine test environment description parameters according to the target business scenario, wherein the test environment description parameters characterize the target memory access mode and load pressure of the memory module;

[0138] Result acquisition module 1503: used to acquire the first memory test result of the memory module in the test environment corresponding to the test environment description parameters.

[0139] It should be noted that the apparatus and method embodiments described in the device embodiments are based on the same inventive concept.

[0140] In some embodiments, the functions or modules of the apparatus provided in this application can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0141] This application also provides a computer-readable storage medium storing at least one instruction or at least one program segment, which is loaded and executed by a processor to implement the above-described method. The computer-readable storage medium may be a non-volatile computer-readable storage medium.

[0142] This application also provides an electronic device, which includes at least one processor and a memory communicatively connected to the at least one processor; wherein the memory stores at least one instruction or at least one program, and the at least one instruction or at least one program is loaded and executed by the at least one processor to implement the above method.

[0143] Electronic devices can be provided as terminals, servers, or other forms of devices.

[0144] Figure 16 A block diagram of an electronic device according to an embodiment of this application is shown. For example, electronic device 1900 may be provided as a server. (Refer to...) Figure 16 The electronic device 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by the processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1922 is configured to execute instructions to perform the methods described above.

[0145] Electronic device 1900 may also include a power supply component 1926 configured to perform power management of electronic device 1900, a wired or wireless network interface 1950 configured to connect electronic device 1900 to a network, and an input / output (I / O) interface 1958. Electronic device 1900 can operate on an operating system stored in memory 1932, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, or similar.

[0146] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by a processing component 1922 of an electronic device 1900 to perform the above-described method.

[0147] This application may be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of this application.

[0148] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0149] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0150] The computer program instructions used to perform the operations of this application may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C+, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuits, such as programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), are personalized by utilizing the status information of the computer-readable program instructions. These electronic circuits can execute the computer-readable program instructions to implement various aspects of this application.

[0151] Various aspects of this application are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0152] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0153] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0154] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which includes one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions specified in the blocks may occur in a different order than those specified in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0155] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technological improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A memory testing method, characterized in that, The method includes: In response to a memory test request, the target business scenario corresponding to the memory module in the device under test is extracted from the memory test request; The test environment description parameters are determined based on the target business scenario. The test environment description parameters characterize the target memory access mode and load pressure of the memory module. Obtain the first memory test result of the memory module under the test environment corresponding to the test environment description parameters; In the presence of at least two target memory access modes and at least two load stress conditions, sub-bandwidth information and sub-latency information for each sub-environment are extracted from the first memory test results; the test environment determined based on the test environment description parameters includes a target number of sub-environments, where the target number is the product of the total number of target memory access modes and the total number of load stress conditions; For each sub-environment, a first difference between the sub-bandwidth information and the sub-reference bandwidth in the sub-environment is determined, and a second difference between the sub-latency information and the sub-reference latency in the sub-environment is determined; the reference memory bandwidth includes the sub-reference bandwidth in each sub-environment, and the reference memory access latency includes the sub-reference latency in each sub-environment; the reference memory bandwidth and the reference memory access latency are obtained by performing memory tests on a preset device, and the environment for performing memory tests on the preset device is constructed based on the test environment description parameters; Based on the first difference and the second difference corresponding to each sub-environment, the target memory test results are obtained.

2. The method according to claim 1, characterized in that, Before determining the test environment description parameters based on the target business scenario, the method further includes: Based on the target business scenario, the operation characteristics for reading and writing operations on the memory module are determined, and the operation characteristics are at least one of the following: operation time characteristics, operation speed characteristics, and operation sequence characteristics. The target memory access mode is determined based on the operational characteristics.

3. The method according to claim 1, characterized in that, Before obtaining the first memory test result of the memory module under the test environment corresponding to the test environment description parameters, the method further includes: The corresponding simulation device is determined based on the device information of the device to be tested; Based on the test environment description parameters, a corresponding test environment is constructed to test the memory module in the simulated device, and a second memory test result of the memory module in the simulated device is obtained. The second memory test result is determined as the first memory test result.

4. The method according to claim 3, characterized in that, The construction of the corresponding test environment based on the test environment description parameters includes: Access to the memory modules in the simulated device is limited based on the target memory access mode; In the presence of at least two of the aforementioned load pressure conditions, the frequency at which the central processing unit in the simulation device issues memory access requests is set based on the load pressure conditions.

5. The method according to claim 1, characterized in that, Each load stress condition corresponds to an environment description dimension. The target memory test results are obtained based on the first difference and the second difference corresponding to each sub-environment, including: Based on the first difference corresponding to each of the sub-environments, for each of the environment description dimensions, a first difference representation under the environment description dimension is determined, and based on the first difference representation corresponding to each of the environment description dimensions, a bandwidth difference representation is obtained. Based on the second difference corresponding to each of the sub-environments, for each of the environment description dimensions, a second difference representation under the environment description dimension is determined, and based on the second difference representation corresponding to each of the environment description dimensions, a delay difference representation is obtained. Based on the bandwidth difference characterization and the latency difference characterization, the target memory test results are obtained.

6. A memory testing device, characterized in that, The device includes: Scenario determination module: used to extract the target business scenario corresponding to the memory module in the device under test from the memory test request in response to the memory test request; Parameter determination module: used to determine test environment description parameters based on the target business scenario, wherein the test environment description parameters characterize the target memory access mode and load pressure of the memory module; Result Acquisition Module: Used to acquire the first memory test result of the memory module in the test environment corresponding to the test environment description parameters; In the presence of at least two target memory access modes and at least two load pressure conditions, extracting sub-bandwidth information and sub-latency information for each sub-environment from the first memory test result; The test environment determined based on the test environment description parameters includes a target number of sub-environments, the target number being the product of the total number of target memory access modes and the total number of load pressure conditions; For each sub-environment, determining a first difference between the sub-bandwidth information and the sub-baseline bandwidth in the sub-environment, and determining a second difference between the sub-latency information and the sub-baseline latency in the sub-environment; The baseline memory bandwidth includes the sub-baseline bandwidth in each sub-environment, and the baseline memory access latency includes the sub-baseline latency in each sub-environment; The baseline memory bandwidth and the baseline memory access latency are obtained by performing memory tests on a preset device, and the environment for performing memory tests on the preset device is constructed based on the test environment description parameters; Based on the first difference and the second difference corresponding to each sub-environment, the target memory test result is obtained.

7. The apparatus according to claim 6, characterized in that, The device is further configured to: before determining the test environment description parameters according to the target business scenario, determine the operation characteristics of reading and writing operations on the memory module according to the target business scenario, wherein the operation characteristics are at least one of the following: operation time characteristics, operation speed characteristics, and operation sequence characteristics; The target memory access mode is determined based on the operational characteristics.

8. The apparatus according to claim 6, characterized in that, The device is further configured to: before obtaining the first memory test result of the memory module in the test environment corresponding to the test environment description parameters, determine the corresponding simulation device based on the device information of the device under test; construct the corresponding test environment based on the test environment description parameters to test the memory module in the simulation device, and obtain the second memory test result of the memory module in the simulation device; The second memory test result is determined as the first memory test result.

9. The apparatus according to claim 8, characterized in that, The construction of the corresponding test environment based on the test environment description parameters includes: Access to the memory modules in the simulated device is limited based on the target memory access mode; In the presence of at least two of the aforementioned load pressure conditions, the frequency at which the central processing unit in the simulation device issues memory access requests is set based on the load pressure conditions.

10. The apparatus according to claim 6, characterized in that, Each load stress condition corresponds to an environment description dimension. The target memory test results are obtained based on the first difference and the second difference corresponding to each sub-environment, including: Based on the first difference corresponding to each of the sub-environments, for each of the environment description dimensions, a first difference representation under the environment description dimension is determined, and based on the first difference representation corresponding to each of the environment description dimensions, a bandwidth difference representation is obtained. Based on the second difference corresponding to each of the sub-environments, for each of the environment description dimensions, a second difference representation under the environment description dimension is determined, and based on the second difference representation corresponding to each of the environment description dimensions, a delay difference representation is obtained. Based on the bandwidth difference characterization and the latency difference characterization, the target memory test results are obtained.

11. An electronic device, characterized in that, The electronic device includes at least one processor and a memory communicatively connected to the at least one processor; wherein the memory stores at least one instruction or at least one program, the at least one instruction or at least one program being loaded and executed by the at least one processor to implement the memory testing method as described in any one of claims 1-5.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores at least one instruction or at least one program, which is loaded and executed by a processor to implement the memory testing method as described in any one of claims 1-5.

13. A computer program product, characterized in that, The computer program product includes at least one instruction or at least one program segment, which is loaded and executed by a processor to implement the memory testing method as described in any one of claims 1-5.

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