A row data scanning readout circuit for an image sensor

Abstract

The present invention provides a row data scanning readout circuit of an image sensor, comprising: a pixel array, comprising a plurality of pixel units; the input end of the electrical signal conversion module is electrically connected to the output end of the pixel unit; the input end of the row data latch is electrically connected to the output end of the electrical signal conversion module; the input end of the readout unit is electrically connected to the output end of the row data latch; the output end of the readout unit is electrically connected to the input end of the data processing module through a data bus, the data processing module comprises a comparator, the positive input end of the comparator is electrically connected to the data bus, the reverse input end of the comparator inputs a reference voltage, and the comparator compares the voltage difference between the data bus voltage and the reference voltage to realize data reading. The row data scanning readout circuit of an image sensor disclosed by the present invention can ensure the accurate output of data during large array and long distance transmission.

Description

Technical Field

[0001] The present invention relates to the field of image sensors, and in particular to a row data scanning and reading circuit of an image sensor. Background Art

[0002] The image sensor is provided with a row scanning circuit, through which data is read out. When the pixel array area is too large and the data bus is too long, the data bus is segmented to avoid errors in the sampling output of the subsequent circuit, which will increase power consumption and area, as well as complicate the timing to a certain extent. If the size of the buffer is increased to improve the driving capability, it is easy to increase the vertical height of the array, resulting in unstable data readout and errors. Summary of the invention

[0003] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a row data scanning and reading circuit for an image sensor, which can ensure accurate data output when the pixel array is too large and the data bus line is too long.

[0004] To achieve the above-mentioned object and other related objects, the present invention provides a row data scanning and reading circuit of an image sensor, comprising:

[0005] A pixel array, comprising a plurality of pixel units, and the pixel array outputs an electrical signal;

[0006] An electrical signal conversion module, wherein an input end of the electrical signal conversion module is electrically connected to an output end of the pixel unit, and the electrical signal conversion module outputs digital signal data;

[0007] A row data latch, wherein an input end of the row data latch is electrically connected to an output end of the electrical signal conversion module;

[0008] A row scanning readout module, comprising a plurality of readout units, wherein the input end of the readout unit is electrically connected to the output end of the row data latch; and

[0009] A data processing module, wherein the input end of the data processing module is electrically connected to the output end of the readout unit through a data bus, the data processing module includes a comparator, the positive input end of the comparator is electrically connected to the data bus, the reverse input end of the comparator inputs a reference voltage, and the voltage difference between the data bus voltage and the reference voltage is compared by the comparator.

[0010] In one embodiment of the present invention, the row scan readout module further includes a signal generation module, the output end of the signal generation module is electrically connected to the input end of the readout unit, and the signal generation module outputs a row scan selection signal and a precharge reset signal.

[0011] In one embodiment of the present invention, the readout unit includes a first transistor, a gate of the first transistor is electrically connected to an output end of the row data latch, and a source of the first transistor is grounded.

[0012] In one embodiment of the present invention, the read-out unit also includes a second transistor, the gate of the second transistor is electrically connected to the row scan selection signal output terminal of the signal generating module, the source of the second transistor is electrically connected to the drain of the first transistor, and the drain of the second transistor is electrically connected to the data bus.

[0013] In one embodiment of the present invention, the read-out unit also includes a third transistor, the gate of the third transistor is electrically connected to the pre-charge reset signal output terminal of the signal generating module, the source of the third transistor is connected to the power supply voltage, and the drain of the third transistor is electrically connected to the data bus.

[0014] In one embodiment of the present invention, the comparator includes a sampling capacitor, a lower plate of the sampling capacitor is electrically connected to the data bus through a sampling switch, and the lower plate of the sampling capacitor is also input with the reference voltage through a sampling capacitor reset switch.

[0015] In an embodiment of the present invention, the comparator further includes a first inverter, an input end of the first inverter is electrically connected to the upper plate of the sampling capacitor, and the first inverter is connected in parallel with a first comparator reset switch.

[0016] In an embodiment of the present invention, the comparator further includes a capacitor between two-stage inverters, and a lower plate of the capacitor between the two-stage inverters is electrically connected to the output end of the first inverter.

[0017] In one embodiment of the present invention, the comparator further includes a second inverter, the input end of the second inverter is electrically connected to the upper plate of the intermediate capacitor of the two-stage inverter, and the second inverter is connected in parallel with a second comparator reset switch.

[0018] In an embodiment of the present invention, the comparator further includes a third inverter, and an input terminal of the third inverter is electrically connected to an output terminal of the second inverter.

[0019] In an embodiment of the present invention, the data processing module further includes a data processing and restoring unit, and an input end of the data processing and restoring unit is electrically connected to an output end of the third inverter.

[0020] In an embodiment of the present invention, the signal generating module includes a plurality of triggers, and the output terminals of the triggers are electrically connected to the input terminals of the AND gates.

[0021] The present invention provides an image sensor, comprising the row data scanning readout circuit of the image sensor mentioned above.

[0022] As described above, the present invention provides a row data scanning readout circuit of an image sensor, wherein a plurality of readout units are provided, and a precharge reset signal and a row scan selection signal are generated by a signal generation module, so as to control the readout units to sequentially read the data output by the corresponding column row data latches. The readout units are electrically connected to the comparator through the data bus, and the voltage difference between the data bus voltage and the reference voltage is compared by the comparator to complete the accurate output of the read data. In this embodiment, the accurate reading of the data can be completed by comparing the data bus voltage and the reference voltage. At the same time, the circuit structure is simple, and when a large array is transmitted over a long distance, the longitudinal height of the array can be greatly reduced, thereby reducing the chip area and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0024] Figure 1 Shown is a schematic structural diagram of a row data scanning readout circuit of an image sensor;

[0025] Figure 2 Shown is a structural schematic diagram of a row data scanning readout circuit of an image sensor of the present invention;

[0026] Figure 3 Shown is a schematic structural diagram of a readout unit of the present invention;

[0027] Figure 4 Shown is a schematic diagram of the connection structure of the signal generating module of the present invention;

[0028] Figure 5 Shown is a circuit operation timing principle diagram of the signal generating module of the present invention;

[0029] Figure 6 The display is a schematic diagram of the circuit operation timing of the present invention;

[0030] Figure 7 Shown is a schematic diagram of the structure of a comparator of the present invention;

[0031] Figure 8 Shown is a schematic structural diagram of an inverter of the present invention;

[0032] Fig. 9 It is a schematic structural diagram of another inverter of the present invention;

[0033] Fig.10 Shown is a circuit operation timing principle diagram of the comparator of the present invention. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] See also Figure 1 As shown, the row scanning circuit of the image sensor includes a pixel array 10, and the pixel array 10 includes a plurality of pixel units 11. The pixel units 11 are arranged orthogonally in the pixel array 10, the pixel units 11 arranged in the horizontal direction form a row, each row includes M pixel units 11, and the pixel units 11 arranged in the vertical direction form a column, each column includes N pixel units 11, so the total number of pixel units 11 in the pixel array 10 is M×N. The exposure performed in the pixel array 10 starts and ends by row, that is, the pixel units 11 are exposed to all columns of the same row at the same time, so that the pixel array 10 generates a photoelectric effect, and converts the photoelectrons generated by the external light input into an electrical signal. The output end of the pixel array 10 is electrically connected to the input end of the current source load (CSL), and the electrical signal converted by the pixel units 11 in each column is input to the CSL. The output of the CSL is electrically connected to the input of a programmable gain amplifier (PGA), and the output of the PGA is electrically connected to an analog-to-digital converter (ADC). After the electrical signal is amplified by the PGA, it is processed by the ADC and converted into digital signal data for output.

[0036] See also Figure 1As shown, the row scanning circuit of the image sensor also includes a row data latch 20 and a row scanning circuit 30. The input end of the row data latch 20 is electrically connected to the output end of the ADC, and the output end of the row data latch 20 is electrically connected to the input end of the row scanning circuit 30. The converted digital signal data is latched by the row data latch 20, and the digital image data corresponding to the pixel unit 11 converted is input into the row scanning circuit 30 one by one by column. The digital image data is, for example, D[0]<11:0> to D[N-1]<11:0>. After the pixel array 10 is exposed for the first time and the electrical signal conversion is processed, D[0]<11:0> is the digital image data corresponding to the conversion of the pixel unit 11 in the first row and the first column, D[1]<11:0> is the digital image data corresponding to the conversion of the pixel unit 11 in the first row and the second column, and so on to the digital image data D[N]<11:0> corresponding to the conversion of the pixel unit 11 in the first row and the Nth column. The row scanning circuit 30 includes a plurality of buffers 31, a plurality of switches 32 and a trigger 33, wherein the trigger 33 is, for example, a D trigger. The buffer 31 is electrically connected to the data bus through the switch 32, and the digital image data opens the switch 32 one by one by column to output the data to the data bus. The plurality of triggers 33 are electrically connected, and are connected to the row scanning clock signal HCLK through the clock interface CK. The input terminal D of the first trigger 33 is connected to the row scanning trigger signal HTRIG, and the output terminal Q is electrically connected to the input terminal D of the second trigger 33, thereby electrically connecting the input terminals and output terminals of the plurality of triggers 33, so that the trigger signal HTRIG controls the trigger 33 to output a continuous selection signal. The continuous selection signal, for example, HSEL <0> ~HSEL <n-1>Among them, HSEL <0> HSEL is the continuous selection signal output by the trigger corresponding to the first column pixel unit 110. <1> is the continuous selection signal HSEL output by the trigger corresponding to the pixel unit 11 in the second column, and so on, the continuous selection signal HSEL output by the trigger corresponding to the pixel unit 11 in the Nth column <n-1>By controlling multiple switches 32 one by one through continuous selection signals, the digital image data in the row data latch 20 is connected to the data bus one by one through the buffer 31, so that the data is read out to the interface circuit and sent to the outside of the image sensor. However, when the bus length is large and the data transmission is fast, it is easy to cause a sharp increase in parasitics and loads, causing errors in the data transmission process.

[0037] See also Figure 2 As shown, the present invention provides a row data scanning readout circuit of an image sensor, and the row data scanning readout circuit of the image sensor includes a pixel array 100, and the pixel array 100 includes a plurality of pixel units 110. The pixel units 110 are arranged orthogonally in the pixel array 100, and the pixel units 110 arranged in the horizontal direction constitute a row, each row includes M pixel units 110, and the pixel units 110 arranged in the vertical direction constitute a column, each column includes N pixel units 110, so the total number of pixel units 110 of the pixel array 100 is M×N. When external light irradiates the pixel array 100, a photoelectric effect occurs in the pixel array 100, and the pixel units 110 complete exposure and convert the accumulated photoelectrons into electrical signals. Among them, the exposure performed in the pixel array 100 starts and ends by row, that is, the pixel units 110 are exposed to all columns of the same row at the same time. Specifically, the N columns of pixel units 110 in the first row are exposed in sequence, and the corresponding photoelectrons are converted into electrical signals for output, and the final data readout is completed. At this time, the pixel units 110 in the second row and N columns are exposed in sequence, the corresponding photoelectrons are converted into electrical signals for output, and the final data readout is completed. This process is repeated in this way until the pixel units 110 in the Mth row and N columns are exposed in sequence, the corresponding photoelectrons are converted into electrical signals for output, and the final data readout is completed.

[0038] See also Figure 2 As shown, the present invention provides a row data scanning readout circuit of an image sensor, and the row data scanning readout circuit of the image sensor also includes an electrical signal conversion module 200, the input end of the electrical signal conversion module 200 is electrically connected to the output end of the pixel array 100, and the electrical signal generated by the pixel array 100 in columns is input to the electrical signal conversion module 200. The electrical signal conversion module 200 includes a CSL, a PGA, and an ADC. The output end of the pixel array 100 is electrically connected to the input end of the CSL, and the electrical signal converted by each column of pixel units 110 is input to the CSL, that is, the electrical signal converted by N columns of pixel units 110 is input to the CSL. The output end of the CSL is electrically connected to the input end of the PGA, and the output end of the PGA is electrically connected to the input end of the ADC. After the electrical signal is amplified by the PGA, it is processed by the ADC to convert the electrical signal into a digital signal, that is, the digital signal data is finally output through the ADC.

[0039] See also Figure 2 As shown, the present invention provides a row data scanning readout circuit of an image sensor, and the row data scanning readout circuit of the image sensor also includes a row data latch 300, and the input end of the row data latch 300 is electrically connected to the output end of the electrical signal conversion module 200, that is, the input end of the row data latch 300 is electrically connected to the ADC. The digital signal data converted by the ADC is latched by the row data latch 300, that is, the digital signal data corresponding to the N-column pixel unit 110. Among them, after the first row of pixel units 110 are exposed for the first time, the generated electrical signal is converted by the electrical signal conversion module 200 to generate digital signal data, and the digital signal data corresponding to the conversion of the first row of pixel units 110 is input to the row data latch 300. In this embodiment, the ADC is 12 bits, so the data latched by the row data latch 300 is 12 bits. Specifically, the data latched by the row data latch 300 is the digital signal data D[0]<11:0>~D[N-1]<11:0>. Among them, after the first exposure and electrical signal conversion processing of the pixel array 100, D[0]<11:0> is the 12-bit digital signal data correspondingly converted and generated by the pixel units 110 of the first row and the first column, D[1]<11:0> is the 12-bit digital signal data correspondingly converted and generated by the pixel units 110 of the first row and the second column, and so on to the 12-bit digital signal data D[N-1]<11:0> correspondingly converted and generated by the pixel units 110 of the first row and the Nth column. At the same time, after the exposure of the first row of pixel units 110 and the completion of the final data readout, the data latched by the row data latch 300 is the 12-bit digital signal data correspondingly converted by the pixel units 110 of the other N-1 rows.

[0040] See also Figure 2 As shown, the present invention provides a row data scanning readout circuit of an image sensor, and the row data scanning readout circuit of the image sensor also includes a row scanning readout module 400, the input end of the row scanning readout module 400 is electrically connected to the output end of the row data latch 300, and the output end of the row scanning readout module 400 is electrically connected to the interface circuit, and the scanned data is output to the outside of the image sensor. The row scanning readout module 400 includes a plurality of readout units 401, and the plurality of readout units 401 are electrically connected to the data bus. The input end of the readout unit 401 is electrically connected to the output end of the data latch 300. Since the width of the data bus is related to the ADC resolution, in this embodiment, the ADC is 12 bits, and the row data latch 300 latches and outputs 12 bits of digital signal data. Then, the corresponding row scanning readout module 400 has a 12-bit readout unit 401 connected to the 12-bit digital signal data, and each bit of digital signal data latched and output by each column of pixel units 110 through the row latch 300 has a corresponding readout unit 401 connected to read.

[0041] See also Figure 2 As shown, the present invention provides a row data scanning readout circuit of an image sensor, and the row data scanning readout circuit of the image sensor further includes a data processing module 500, and the output end of the readout unit 401 is electrically connected to the input end of the data processing module 500 through a data bus. The data processing module 500 includes a comparator 501 and a data processing and restoring unit 502, the positive input end of the comparator 501 is electrically connected to the data bus, the negative input end of the comparator 501 inputs a reference voltage VREF, and the data bus voltage and the reference voltage VREF are compared by the comparator 501 to realize data reading. The input end of the data processing and restoring unit 502 is electrically connected to the output end of the comparator 501, and is simultaneously connected to the row scanning clock signal HCLKB, and the output data of the comparator 501 is restored by the data processing and restoring unit 502.

[0042] See also Figure 2 As shown, the present invention provides a row data scanning readout circuit of an image sensor, the row scanning readout module 400 also includes a signal generating module 402, the input end of the signal generating module 402 is connected to the row scanning trigger signal HTRIG and the row scanning clock signal HCLK, and the output end of the signal generating module 402 is electrically connected to the input end of the readout unit 401, and the row scanning selection signal HSEL and the pre-charge reset signal PREC are generated by the signal generating module 402 to control the data reading of the readout unit 401, thereby controlling the accurate output of the data.

[0043] See also Figure 3 As shown, the present invention provides a row data scanning readout circuit of an image sensor, and the readout unit 401 includes a first transistor N1, a second transistor N2 and a third transistor P1. In this embodiment, the first transistor N1 and the second transistor N2 are set as NMOS (Negative channel-Metal-Oxide-Semiconductor, N-type metal oxide semiconductor) transistors. The third transistor P1 is set as a (positive channel Metal Oxide Semiconductor, P-type metal oxide semiconductor) transistor. The gate of the first transistor N1 is electrically connected to the output end of the row data latch 300, that is, each bit output of each column ADC is electrically connected to the DIN end of the readout unit 401, and the conduction and cutoff of the first transistor N1 are controlled by the output of the row data latch 300. The source of the first transistor N1 is grounded, and the drain of the first transistor N1 is electrically connected to the source of the second transistor N2. The gate of the second transistor N2 is electrically connected to the row scan selection signal output terminal of the signal generation module 402, that is, the row scan selection signal HSEL is connected, and the conduction and cutoff of the second transistor N2 are controlled by the row scan selection signal HSEL. The drain of the second transistor N2 is electrically connected to the data bus. The gate of the third transistor P1 is electrically connected to the precharge reset signal output terminal of the signal generation module 402, that is, the precharge reset signal PREC is connected, and the conduction and cutoff of the third transistor P1 are controlled by the precharge reset signal PREC. The source of the third transistor P1 is connected to the power supply voltage VDD, and the drain of the third transistor P1 is electrically connected to the data bus. It should be understood that, since there are multiple read-out units 401, the row scan read-out module 400 includes multiple first transistors N1, second transistors N2 and third transistors P1, and the data reading of the read-out unit 401 is controlled by controlling the conduction and cutoff of the transistor.

[0044] See also Figure 2 and Figure 3 As shown, the present invention provides a row data scanning readout circuit of an image sensor, and each readout unit 401 is connected to the same precharge reset signal PREC, and the precharge reset signal PREC will turn on the third transistor P1 in the readout unit 401 and reset the data bus voltage to the power supply voltage VDD when each row scan clock signal HCLK cycle is at a low level. Specifically, the row scan selection signal HSEL selects each column readout unit 401 in turn, and when the row scan selection signal HSEL is valid, that is, the row scan selection signal HSEL is at a high level, the second transistor N2 of the corresponding column readout unit 401 is turned on. If the DIN input is 1, that is, the input is a high level, the first transistor N1 is turned on, and the data bus voltage is gradually pulled down. If the DIN input is 0, that is, the input is a low level, the first transistor N1 is turned off, and the data bus voltage remains unchanged at the power supply voltage VDD. Among them, when the DIN input is high level and the data bus voltage is gradually pulled down, and when the data bus voltage is less than the reference voltage VREF, the comparator 501 flips the output PULSE to a high level less than half an HCLK cycle. When DIN inputs a low level and keeps the power supply voltage VDD unchanged, and when the data bus voltage is greater than the reference voltage VREF, the comparator 501 does not flip and outputs a low level. Finally, the output of the comparator 501 is restored by the data processing circuit unit 502 to complete the accurate reading of the data. In this embodiment, when the row scanning clock signal HCLK is at a low level and the data bus is reset, the comparator 501 is reset synchronously with the data bus.

[0045] See also Figure 4 As shown, the present invention provides a row data scanning readout circuit of an image sensor, the signal generating module 402 includes a plurality of triggers DFF, and the plurality of triggers DFF are electrically connected, that is, the signal generating module 402 adopts a DFF chain, and the front stage output is connected to the rear stage input. Figure 4 As shown, in this embodiment, the input terminal D of the first flip-flop DFF0 is connected to the row scan trigger signal HTRIG, the clock interface terminal is connected to the row scan clock signal HCLK, the output terminal Q is electrically connected to the input terminal D of the second flip-flop DFF1 and the input terminal of the first AND gate 4031, and the output terminal Q of the first flip-flop DFF0 outputs Q1. The input terminal D of the second flip-flop DFF1 is connected to Q1, the clock interface terminal is connected to the row scan clock signal HCLKB, the output terminal Q is electrically connected to the input terminal D of the third flip-flop DFF2 and the input terminal of the first AND gate 4031, and the output terminal Q of the second flip-flop DFF1 outputs Q2. The input terminal D of the third flip-flop DFF2 is connected to Q2, the clock interface terminal is connected to the row scan clock signal HCLK, the output terminal Q is electrically connected to the input terminal D of the fourth flip-flop DFF4 and the input terminal of the second AND gate 4032, and the output terminal Q of the third flip-flop DFF2 outputs Q3. The input terminal D of the fourth trigger DFF3 is connected to Q3, the clock interface terminal is connected to the row scan trigger signal HCLK, the output terminal is electrically connected to the input terminal of the second AND gate 4032 and the input terminal D of the next level trigger, and the output terminal Q of the fourth trigger DFF3 outputs Q4. By analogy, the electrical connection and data transmission between multiple triggers DFF are realized. Among them, the row scan clock signals input by two adjacent triggers DFF are inverted, and the pre-charge reset signal PREC uses one of the row scan clock signals, that is, the inverted row scan clock signal HCLK is the row scan clock signal HCLKB, and the pre-charge reset signal PREC uses the row scan clock signal HCLKB. Specifically, the pre-charge reset signal PREC is, for example, PREC <0> ~PREC <n-1>The output ends of two adjacent flip-flops DFF are electrically connected to the input ends of the same AND gate, and the row scan selection signal HSEL is output through the AND gate. Specifically, Q1 and Q2 are input to the first AND gate 4031, and the row scan selection signal HSEL is output through the first AND gate 4031. <0> Q3 and Q4 are input into the second AND gate 4032, and the row scan selection signal HSEL is output through the second AND gate 4032. <1> By analogy, multiple row scan selection signals HSEL are generated, for example, HSEL <0> ~HSEL <n-1>.

[0046] See also Figure 5 As shown, the present invention provides a row data scanning readout circuit of an image sensor, which generates a row scanning selection signal HCLKB and a precharge reset signal PREC through a signal generation module 402, thereby controlling the readout unit 401 to read data. In this embodiment, the time interval between generating adjacent scanning selection signals HSEL is half a cycle, such as Figure 5 As shown, when the row scan trigger signal HTRIG jumps to a low level, and the row scan clock signal HCLK and the row scan trigger signal HCLKB successively jump to a high level, Q1 and Q2 are output, and at this time, HSEL is output through the first AND gate 4021. <0> After half a cycle, the row scan clock signal HCLK and the row scan trigger signal HCLKB jump to high level again, Q3 and Q4 are output, and HSEL is output through the second AND gate 4022. <1> And so on, until the output HSEL <n-1>Multiple row scan selection signals HSEL select each column readout unit 401 in turn, that is, the row scan selection signal HSEL <0> ~HSEL <n-1>The readout unit 401 is controlled to read data through the row scan selection signal HSEL.

[0047] See also Figure 6 As shown, the present invention provides a row data scanning readout circuit of an image sensor. When the row scanning clock signal HCLK is at a high level, that is, the precharge reset signal PREC is at a low level, the third transistor P1 is turned on, and the data bus is reset to the power supply voltage VDD. The scanning selection signal HSEL selects each column readout unit 401 in turn, that is, HSEL <0> ~HSEL <n-1>Specifically, in the current cycle, the row scan selection signal HSEL of the first column readout unit 401 is input <0> It jumps to a high level, and the second transistor N2 is turned on. At this time, the pre-charge reset signal PREC is at a high level, and the third transistor P1 is turned off. DIN inputs a high level, the first transistor N1 is turned on, and the data bus (DATA BUS) voltage is gradually pulled down. When the data bus voltage is less than the reference voltage VREF, the output terminal CMP_OUT of the comparator 501 flips the output PULSE to a high level, and the D0 output is 1. Next, the row scan clock signal HCLK jumps to a high level, and when the pre-charge reset signal PREC is at a low level, the third transistor P1 is turned on, the data bus and the comparator 501 are reset, and the data bus voltage is restored to, for example, 1.2V, and CMP_OUT is reset to 0. In the next cycle, the row scan selection signal HSEL of the second column read-out unit 401 is input. <1> It jumps to a high level, and the second transistor N2 is turned on. At this time, the pre-charge reset signal PREC is at a high level, and the third transistor P1 is turned off. DIN inputs a low level, the first transistor N1 is turned off, and the data bus (DATA BUS) voltage remains unchanged after reset. The output terminal CMP_OUT of the comparator 501 does not flip and outputs a low level, and the output of D1 is 0. Then, the row scan clock signal HCLK jumps to a low level. When the pre-charge reset signal PREC is at a low level, the third transistor P1 is turned on, and the data bus and the comparator 501 are reset again. Continue to the next cycle, and input the row scan selection signal HSEL of the third column read-out unit 401 <2> Jumps to a high level, and the second transistor N2 is turned on. At this time, the precharge reset signal PREC is at a high level, and the third transistor P1 is turned off. DIN inputs a high level, the first transistor N1 is turned on, and the data bus (DATABUS) voltage is gradually pulled down. When the data bus voltage is less than the reference voltage VREF, the output terminal CMP_OUT of the comparator 501 flips the output PULSE to a high level, and the output of D2 is 1. Then, the row scan clock signal HCLK jumps to a low level, and when the precharge reset signal PREC is at a low level, the third transistor P1 is turned on, the data bus and the comparator 501 are reset, and the data bus voltage is restored to, for example, 1.2V, and CMP_OUT is reset to 0. By analogy, different row scan selection signals HSEL are input through the readout unit 401 to read data, and the voltage difference between the data bus voltage and the reference voltage VREF is compared through the comparator 501 to accurately read the 0 and 1 on the data bus, that is, accurately read the ADC output data. At the same time, the output terminal CMP_OUT of the comparator 501 is inverted and output PULSE is restored by the data processing and restoring unit 502, that is, restored to data with the same frequency as the row scanning clock signal HCLK and a data length equal to a row scanning clock signal HCLK period.

[0048] See also Figure 7 As shown, the present invention provides a row data scanning readout circuit of an image sensor, and the comparator 501 includes a sampling capacitor C1, a sampling switch CK1 and a sampling capacitor reset switch CK2. One end of the sampling switch CK1 is electrically connected to the data bus, that is, the input signal voltage VIN, and the other end is electrically connected to the lower plate of the sampling capacitor C1, that is, the sampling capacitor C1 is electrically connected to the data bus through the sampling switch CK1. One end of the sampling capacitor reset switch CK2 is connected to the reference voltage VREF, and the other end is electrically connected to the lower plate of the sampling capacitor C1, that is, the sampling capacitor C1 inputs the reference voltage VREF through the sampling capacitor reset switch CK2.

[0049] See also Figure 7 As shown, the present invention provides a row data scanning readout circuit of an image sensor, and the comparator 501 also includes a first inverter I1, a second inverter I2, a third inverter I3 and a capacitor C2 between two-stage inverters. In this embodiment, the first inverter I1 and the second inverter I2 are, for example, inverters under the AVDD / AVSS voltage domain and with controlled maximum current. The third inverter I3 is, for example, an inverter under the DVDD / DVSS power domain. The input end of the first inverter I1 is electrically connected to the upper plate of the sampling capacitor C1, and the first inverter I1 is connected in parallel to the first comparator reset switch S1. The lower plate of the capacitor C2 between the two-stage inverters is electrically connected to the output end of the first inverter I1, and the upper plate of the capacitor C2 between the two-stage inverters is electrically connected to the input end of the second inverter I2. The output end of the second inverter I2 is electrically connected to the input end of the third inverter I3, and the second inverter I2 is connected in parallel to the second comparator reset switch S2. The output terminal of the third inverter I3 is electrically connected to the input terminal of the data processing and restoring unit 502 , and finally outputs PULSE to the data processing and restoring unit 502 through the comparator 501 .

[0050] See also Figure 8 As shown, the present invention provides a row data scanning readout circuit of an image sensor, the first inverter I1 and the second inverter I2 have the same basic circuit structure, as shown in FIG. Figure 8 As shown, taking the first inverter I1 as an example, the first inverter I1 includes a transistor NM1, a transistor PM1 and a transistor PM2. In this embodiment, the transistor NM1 is configured as an NMOS transistor, for example, and the transistor PM1 and the transistor PM2 are configured as PMOS transistors, for example. The gates of the transistors NM1 and PM1 are electrically connected to the input signal terminal IN, the drains of the transistors NM1 and PM1 are electrically connected to the output signal terminal OUT, the source of the transistor NM1 is connected to the voltage power supply AVSS, and the source of the transistor PM1 is electrically connected to the drain of the transistor PM2. The gate of the transistor PM2 is electrically connected to the bias circuit BIAS, and the source of the transistor PM2 is connected to the voltage power supply AVDD.

[0051] See also Fig. 9 As shown, the present invention provides a row data scanning readout circuit of an image sensor, wherein the third inverter I3 includes a transistor NM2 and a transistor PM3. The gates of the transistor NM2 and the transistor PM3 are electrically connected to the input signal terminal IN, the drains of the transistor NM2 and the transistor PM3 are electrically connected to the output signal terminal OUT, the source of the transistor NM2 is connected to the voltage power supply DVSS, and the source of the transistor PM3 is connected to the voltage power supply DVDD.

[0052] See also Figure 7 and Fig.10 As shown, the present invention provides a row data scanning readout circuit of an image sensor, and the comparator 501 circuit is reset synchronously with the data bus. When the comparator 501 circuit is reset, the sampling capacitor reset switch CK2 is turned on, and the lower plate of the sampling capacitor C1 is connected to the reference voltage VREF. The first comparator reset switch S1 and the second comparator reset switch S2 are turned on, the first comparator reset switch S1 turns on the first inverter I1, and the second comparator reset switch S2 turns on the second inverter I2, and the input and output of the first inverter I1 and the second inverter I2 are connected and reset. At this time, the voltage of the upper plate of the sampling capacitor C1 and the lower plate of the capacitor C2 in the middle of the two-stage inverter are both VRSET. Among them, the upper plate of the sampling capacitor C1 is Figure 7 At point A shown in the figure, the lower plate of capacitor C2 between the two-stage inverter is Figure 7 The voltages at point B, i.e., point A and point B, are both VRSET. At the same time, the voltages at the upper plate of the capacitor C2 between the two-stage inverter and the input terminal of the third inverter I3 are also VRSET. Figure 7 At point C shown in FIG. 1 , the input terminal of the third inverter I3 is Figure 7 The voltages at point D, that is, points C and D, are both VRSET. In this embodiment, VRSET is the voltage when the first inverter I1 and the second inverter I2 are reset, and the voltage VRSET is input to the third inverter I3, so that the output of the third inverter I3 is low level.

[0053] See also Figure 7 and Fig.10 As shown, the present invention provides a row data scanning and reading circuit for an image sensor. After the comparator 501 circuit is reset, first, after disconnecting the first comparator reset switch S1, then the sampling capacitor reset switch CK2 is disconnected, so as to ensure that the charge stored on the upper plate of the sampling capacitor C1 remains unchanged. Among them, the charge Q1 stored on the upper plate of the sampling capacitor C1 can be obtained by the following formula: Q1 = (VREF - VRSET) × C1. Then, the second comparator reset switch S2 remains conducting until after the sampling switch CK1 conducts, and then the second comparator reset switch S2 is disconnected, so as to ensure that the output of the third inverter I3 is low before the sampling capacitor C1 samples. At this time, the comparator 501 is connected to the input signal voltage VIN, that is, the input data bus voltage, and samples the input signal voltage VIN through the sampling capacitor C1. Among them, the charge Q2 stored on the upper plate of the sampling capacitor C1 can be obtained by the following formula: Q2 = (VIN - V A ) × C1, where V A is the voltage at point A on the upper plate of the sampling capacitor C1 at this time. Since the charge stored on the upper plate of the sampling capacitor C1 remains unchanged, that is, (VIN - V A ) × C1 = (VREF - VRSET) × C1. Specifically, since the first inverter I1 and the second inverter I2 are two-stage inverters, their gain is very large. When VIN > VREF, V A > VRSET, the voltages at points B and C decrease, and the voltage at point D rises rapidly, causing the third inverter I3 to flip and output low level, that is, the output PULSE is still low level. When VIN < VREF, V A < VRSET, the voltages at points B and C rise, and the voltage at point D decreases rapidly, causing the third inverter I3 to flip and output high level, that is, the output PULSE is high level. It can be seen from this that when the input DIN is high level and the data bus is pulled low, a high pulse will be generated at the output PULSE. The generated high pulse is input into the digital processing and restoration unit 502, and restored into data that is synchronized with the clock and has the same period as the single data width row scan clock signal HCLK. In this embodiment, the comparator 501 adopts the method of offset storage, effectively reducing the offset voltage at the input end of the traditional comparator, thereby reducing the influence of the offset voltage on the output of the comparator 501, and further reducing the probability of data errors.

[0054] In summary, the row data scanning readout circuit of an image sensor provided by the present invention includes a row scanning readout module 400, and the input end of the row scanning readout module 400 is electrically connected to the output end of the row latch 300, so as to read the digital signal data. Among them, the row scanning readout module 400 includes a plurality of readout units 401, and the readout unit 401 sequentially reads the digital signal data output by the row data latch 300 of the corresponding column. The row scanning readout module 400 includes a signal generation module 402, and the precharge reset signal PREC and the row scanning selection signal HSEL are generated by the signal generation module 402, and the generated signals are sequentially input into the readout unit 401 of the corresponding column, so as to control the readout unit 401 to read the data, and then output the data bus voltage. Finally, the voltage difference between the data bus voltage and the reference voltage is compared by the comparator 501, and the accurate output of the read data is completed. In this embodiment, by arranging a comparator 501 outside the pixel array 100, by comparing the data bus voltage with the reference voltage, the data can be accurately read without the data waveform on the bus reaching the swing of the power supply and the ground and having a good rise and fall time. At the same time, the circuit structure is simple, and when transmitting over a large array and a long distance, the vertical height of the array can be greatly reduced, thereby reducing the chip area and power consumption.

[0055] In the description of this specification, the description with reference to the terms "this embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0056] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A row data scanning readout circuit of an image sensor, characterized in that: include: A pixel array, comprising a plurality of pixel units, and the pixel array outputs an electrical signal; An electrical signal conversion module, wherein an input end of the electrical signal conversion module is electrically connected to an output end of the pixel unit, and the electrical signal conversion module outputs digital signal data; A row data latch, wherein an input end of the row data latch is electrically connected to an output end of the electrical signal conversion module; A row scanning readout module, comprising a plurality of readout units, wherein the input end of the readout unit is electrically connected to the output end of the row data latch; as well as A data processing module, wherein an input end of the data processing module is electrically connected to an output end of the readout unit through a data bus, the data processing module comprises a comparator, a positive input end of the comparator is electrically connected to the data bus, a reference voltage is input to a negative input end of the comparator, and a voltage difference between a data bus voltage and the reference voltage is compared by the comparator; And the comparator comprises: A sampling capacitor, wherein the lower plate of the sampling capacitor is electrically connected to the data bus through a sampling switch, and the lower plate of the sampling capacitor is also input with the reference voltage through a sampling capacitor reset switch; A first inverter, wherein an input terminal of the first inverter is electrically connected to an upper plate of the sampling capacitor, and the first inverter is connected in parallel to a first comparator reset switch; A capacitor between two-stage inverters, wherein a lower plate of the capacitor between two-stage inverters is electrically connected to an output end of the first inverter; A second inverter, wherein an input terminal of the second inverter is electrically connected to an upper plate of a capacitor between the two-stage inverters, and the second inverter is connected in parallel to a second comparator reset switch; A third inverter, wherein an input terminal of the third inverter is electrically connected to an output terminal of the second inverter.

2. The row data scanning readout circuit of an image sensor according to claim 1, characterized in that: The row scanning readout module further includes a signal generating module, an output end of the signal generating module is electrically connected to an input end of the readout unit, and the signal generating module outputs a row scanning selection signal and a pre-charge reset signal.

3. The row data scanning readout circuit of an image sensor according to claim 2, characterized in that: The readout unit includes a first transistor, a gate of the first transistor is electrically connected to an output end of the row data latch, and a source of the first transistor is grounded.

4. The row data scanning readout circuit of an image sensor according to claim 3, characterized in that: The readout unit also includes a second transistor, the gate of the second transistor is electrically connected to the row scan selection signal output end of the signal generating module, the source of the second transistor is electrically connected to the drain of the first transistor, and the drain of the second transistor is electrically connected to the data bus.

5. The row data scanning readout circuit of an image sensor according to claim 2, characterized in that: The readout unit also includes a third transistor, a gate of the third transistor is electrically connected to the precharge reset signal output terminal of the signal generating module, a source of the third transistor is connected to the power supply voltage, and a drain of the third transistor is electrically connected to the data bus.

6. The row data scanning readout circuit of an image sensor according to claim 1, characterized in that: The data processing module further includes a data processing restoration unit, and an input end of the data processing restoration unit is electrically connected to an output end of the third inverter.

7. The row data scanning and reading circuit of an image sensor according to claim 2, characterized in that: The signal generating module includes a plurality of triggers, and the output ends of the triggers are electrically connected to the input ends of the AND gates.

8. An image sensor, characterized in that: A row data scanning readout circuit comprising the image sensor as claimed in claim 1.

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