Circuit and method for judging frequency mislocking of a mixer phase-locked loop signal in a loop

Abstract

The present invention discloses a circuit and method for judging the frequency mislocking of a mixer PLL (Phase-Locked Loop) in a loop, belonging to the technical field of microwave frequency synthesizers. The circuit includes a first power divider, a mixer PLL in the loop, and a mislocking determination circuit. The REF signal is equally divided into two paths by the first power divider and respectively connected to the mixer PLL in the loop and the mislocking determination circuit as reference signals. The present invention realizes the effective determination of mislocked signals, provides a basis for timely triggering re-locking after mislocking, avoids the problem that the output signal is incorrect due to the inability to effectively detect after mislocking, and improves the reliability of the mixer PLL in the loop.

Description

Technical Field

[0001] The present invention relates to the technical field of microwave frequency synthesizers, and more specifically, to a circuit and method for determining whether a frequency of an intra-loop mixing phase-locked loop signal is locked incorrectly. Background Art

[0002] Phase-locked loop signal lock determination technology is widely used in phase-locked frequency synthesis technology. Its function is to determine whether the VCO output signal in the phase-locked loop circuit is locked to the reference signal. In conventional phase-locked loop circuits, the lock determination circuit is often integrated into the phase detector. The typical principle is shown in Figure 1 As shown in the figure, its working principle is to set the reference frequency division ratio and the RF feedback signal frequency division ratio according to the frequency to be locked, and set the appropriate time detection window. When the phase-locked loop is locked, the reference frequency division signal and the RF feedback frequency division signal will fall within the detection window according to the fixed phase difference (time difference). When they fall within the detection window 2048 times in a row, the locking circuit determines that the loop is locked and outputs a high level. Otherwise, it outputs a low level. When this lock indication circuit is used in a single-loop phase-locked loop circuit, it can accurately determine whether the final VCO output signal is correctly locked. However, in the following examples, Figure 2 In the loop mixer phase-locked circuit shown, if a single lock determination circuit integrated in the phase detector circuit is used, there is a possibility of false lock determination when the lock detection circuit detects lock. Summary of the Invention

[0003] The purpose of the present invention is to overcome the shortcomings of the existing technology and provide a circuit and method for judging whether the frequency of an intra-loop mixing phase-locked loop signal is incorrectly locked, thereby achieving effective judgment of signal mislock, providing a basis for timely triggering relocking after mislock, avoiding the problem of being unable to effectively detect after mislock, resulting in continuous errors in the output signal, and improving the reliability of the intra-loop mixing phase-locked loop.

[0004] The object of the present invention is achieved through the following solutions:

[0005] A circuit for judging whether the frequency of an internal mixer phase-locked loop signal is locked incorrectly comprises a first power divider, an internal mixer phase-locked loop and a wrong lock judgment circuit. ref (t) splitting the equal-phase power into two outputs through a first power divider, and respectively connecting them to an in-loop mixer phase-locked loop and a fault lock determination circuit as reference signals;

[0006] The loop mixing phase-locked loop includes a phase detector, a loop filter, a VCO, a second power divider and a mixer, and the VCO output signal θ VCO (t) The phase power is divided into three outputs by the second power divider, which are used as the phase-locked output, the return mixing signal of the mixing phase-locked loop in the loop, and the input signal of the variable divider in the wrong lock judgment circuit; one of the three outputs is θVCO (t) is mixed with the inserted signal θ1(t), filtered, and then sent to the phase discriminator;

[0007] The mislock determination circuit includes a variable frequency divider and a mislock discriminator. The variable frequency divider divides the VCO output signal output by power splitting and then outputs it to the mislock discriminator.

[0008] Furthermore, define the output signal obtained by the in-loop mixing phase-locked loop as θ VCO (t) = θ rf (t) + θ1(t), and the control division value of the variable frequency divider is 2;

[0009] In the in-loop mixing phase-locked loop, set the R division value in the loop filter and phase discriminator to R1, the N division value to N1, and other phase discriminator register parameters to lock the in-loop mixing phase-locked loop, and the phase discriminator lock indication outputs a high level;

[0010] In the mislock determination circuit, set the R division value in the mislock determination circuit to R1 and the N division value to N2. When the in-loop mixing phase-locked loop is locked, the following two situations will occur:

[0011] a) When the VCO locking frequency is correct, that is, θ VCO (t) = θ rf (t) + θ1(t), according to formula (1), after setting the value of N2, the signal frequencies at the two input ends of the lock detection in the mislock discrimination will be the same and homologous and coherent. At this time, after reasonably setting the detection time window, the lock discrimination circuit will output a high level, indicating that the in-loop mixing phase-locked loop is correctly locked;

[0012] b) When the VCO locking frequency is incorrect, that is, θ VCO (t) = θ1(t) - θ rf (t), according to formula (1), after setting the value of N2, the signal frequencies at the two input ends of the lock detection in the mislock discrimination are different. At this time, after reasonably setting the detection time window, they will not continuously appear within the detection time window, and the lock discrimination circuit will output a low level, indicating that the in-loop mixing phase-locked loop is mislocked;

[0013]

[0014] Among them, θ div (t) is the output signal of the variable frequency divider;

[0015] Define the lock indication level of the in-loop mixing phase-locked loop as bit b1 and the lock indication level in the mislock determination circuit as bit b0. When b1b0 = 11, it indicates that the output frequency of the in-loop mixing phase-locked loop is correctly locked; when b1b0 = 10, it indicates that the output frequency of the in-loop mixing phase-locked loop is mislocked; in other cases, it is not locked.

[0016] Further, the phase detector includes an R divider, a phase detection circuit, a CP circuit, an N divider, and a lock detection circuit. The R divider divides the signal entering the REF terminal and then sends it to the phase detection circuit and the lock detection circuit. The N divider divides the signal entering the RF terminal and then sends it to the phase detection circuit and the lock detection circuit. The phase detection circuit and the CP circuit convert the phase difference information of the two input signals into a current value for output.

[0017] Further, the mixer mixes a VCO signal θ VCO (t) output by power splitting with the inserted signal θ1(t) through down-conversion and then sends it to the RF terminal of the phase detector; the frequency of the inserted signal θ1(t) is determined based on the VCO output frequency and the frequency θ rf (t) after mixing, and the phase noise level of the inserted signal input for mixing is better than that of the feedback signal.

[0018] Further, the loop filter includes an active or passive loop filter.

[0019] Further, the VCO outputs a sine wave signal with a corresponding frequency according to a given tuning voltage value.

[0020] Further, the variable divider includes a 1 / 2 / 4 / 8 variable divider, which directly passes, divides by 1 / 2, divides by 1 / 4, or divides by 1 / 8 the VCO signal output by power splitting according to the VCO output signal frequency and the operating frequency band of the N divider of the false lock discriminator for output.

[0021] Further, the false lock discriminator includes an N divider, an R divider, and a lock detection circuit. It divides the signal input to the RF terminal of the false lock discriminator by N, divides the signal input to the REF terminal of the false lock discriminator by R, then sends them to the lock detection circuit, fixes the lock discrimination time window, records the number of times the time difference between the two is continuously less than the set time window, and can determine that it is locked when it reaches 2048 times.

[0022] A method for judging false locking of the signal frequency of a mixer-based phase-locked loop in a loop, based on the circuit for judging false locking of the signal frequency of a mixer-based phase-locked loop in a loop as described above, includes the steps of:

[0023] S1, setting a target frequency θ VCO (t), inserting a mixing signal frequency θ1(t), and the phase noise level of the inserted signal is better than that of the feedback signal;

[0024] S2, controlling each register of the phase detector in the mixer-based phase-locked circuit in the loop, setting its phase detection frequency, using the digital mode for lock detection, setting the detection window time, and adjusting the circuit to achieve locking;

[0025] S3. Control the two registers of the phase discriminator in the error locking discrimination circuit, set its phase discrimination frequency, turn on the internal pre-stage 2-frequency division, use the digital mode for locking detection, set the detection window time, and control the VCO to be 2-frequency division;

[0026] S4. When the locking detection bit b1 of the first phase discriminator in the in-loop mixing and phase-locking circuit is b1 = 1, judge the following two situations according to the state of the locking detection bit b0 of the second phase discriminator in the error locking discrimination circuit:

[0027] 1) When the locking detection bit b0 of the second phase discriminator in the error locking discrimination circuit is b0 = 1 and the port voltage ≥ 2.5V, it is judged that the in-loop mixing and phase-locking circuit is correctly locked;

[0028] 2) When the locking detection bit b0 of the second phase discriminator in the error locking discrimination circuit is b0 = 0 and the port voltage ≤ 0.8V, it is judged that the in-loop mixing and phase-locking circuit is erroneously locked.

[0029] Further, in setting the phase discrimination frequency in step S2, set the R division ratio = 2 and the N division ratio = 40. In setting the phase discrimination frequency in step S3, set the R division ratio = 2 and the N division ratio = 70.

[0030] The beneficial effects of the present invention include:

[0031] (1) The circuit is simple and reliable: The error locking discrimination circuit in the present invention, based on the original in-loop mixing and phase-locking circuit, only needs to use three parts of the power splitter, variable frequency divider, and locking detection circuit to achieve the error locking determination function. The entire circuit structure is simple, and there is no need for complex circuit debugging, calculation, etc., which is simple and reliable.

[0032] (2) The error locking determination is accurate and effective: The error locking discrimination circuit in the present invention realizes the error locking determination by controlling the division ratio, locking detection window time, and 2048 times of counting. The error locking determination standard is the same as the single-phase-locking loop standard (falling within the window continuously for 2048 times), ensuring accuracy and effectiveness.

[0033] (3) The circuit has low cost, low power consumption, and small volume and is easy to integrate and use: For the error locking discrimination circuit in the present invention, there are mature and available monolithic integrated circuits. Its power consumption does not exceed 100mw, and the cost, volume, and power consumption evaluation are all convenient for integration into the in-loop mixing and phase-locking loop circuit to realize timely following the main circuit for error locking determination.

[0034] (4) Wide working frequency range: The working frequency range of the error locking discrimination circuit in the present invention is mainly limited by the working range of the frequency divider. The frequency divider integrated inside the same phase discriminator in the original in-loop mixing and phase-locking circuit is used in the circuit, and an external frequency divider is added. The working frequency range can reach 26GHz, which can meet the requirements of most error locking determination circuits.

[0035] (5) The false lock determination signal is easy to collect, improving the real-time self-checking ability of the system: In the false lock discrimination circuit of the present invention, the output false lock determination signal is a voltage signal of 2.7 to 3.3 V. When applied in the system, the system status acquisition board or the upper-level circuit can directly receive this false lock determination signal and can detect in real time whether the circuit is falsely locked based on this signal, greatly improving the system's fault self-checking ability.

[0036] In summary, the technical solution of the present invention combines a continuously variable frequency division ratio (integer and fractional frequency division) frequency divider and a time window counter. By reasonably setting the frequency division ratio, the number of times that the VCO frequency division signal and the reference frequency division signal both fall within the window time is continuously counted, so as to realize the discrimination of whether the locked signal in the mixing phase-locked loop belongs to a false lock signal, effectively determine the false lock signal, provide a basis for triggering re-locking in time after false locking, avoid the problem of incorrect output signals caused by ineffective detection after false locking, and improve the reliability of the mixing phase-locked loop in the loop. Description of the Drawings

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0038] Figure 1 It is a single-loop phase-locked loop and its locking indication determination principle block diagram;

[0039] Figure 2 It is a mixing phase-locked loop in the loop and a single locking indication determination principle block diagram;

[0040] Figure 3 It is the relationship between the feedback signal and the phase-locked output signal of the mixing phase-locked loop in the loop;

[0041] Figure 4 It is the block diagram of the mixing phase-locked loop and the circuit false locking determination circuit in the embodiment of the present invention;

[0042] Figure 5 It is the active loop filter in the embodiment of the present invention;

[0043] Figure 6 It is the overall circuit diagram in the embodiment of the present invention. Detailed Embodiments

[0044] All the features disclosed in all the embodiments in this specification, or all the steps in the methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or extended and / or replaced in any way.

[0045] In view of the technical problems in the background, the inventors of the present invention further analyzed and believed that there was a lock error judgment. The specific reasons are shown in Figure 3 As shown, combined Figure 2 、 Figure 3 It can be seen that the mixing phase-locked loop in the loop has the following characteristics: θ1(t), R division, N division and θ VCO (t) After the relevant parameters are determined, the output signal θ is finally locked VCO (t) only wants to be one signal, but in reality, there are two possible θ VCO (t) = signal ([θ rf (t)-θ1(t)] or [θ1(t)-θ rf (t)]), these two signals are mixed and reflected as the same signal at the RF end of the phase detector θ rf (t). In this case, if only the internal lock judgment circuit of the phase detector is used, then according to the above judgment rules, both will be locked by the judgment signal, and the signal we want will be θ VCO (t) = θ rf (t)-θ1(t), but in practice the circuit may be locked at θ VCO (t) = θ1(t) - θ rf (t), and the circuit still determines that it is locked correctly, which leads to the lock error judgment situation mentioned above.

[0046] Currently, in applications of in-loop mixer phase-locked circuits, if the aforementioned false lock occurs, the lock detection circuit of the in-loop mixer phase-locked circuit itself cannot identify it. Whether the circuit has false lock can only be determined by the following means:

[0047] 1) Connect the locked signal to a dedicated instrument (spectrum analyzer or signal frequency acquisition equipment) to read the frequency of the locked signal, and combine the actual read frequency value with the Figure 3 The formula determines whether the signal is locked incorrectly or correctly. This method is manual and requires specialized instruments. It is complex and inefficient and is only suitable for circuit debugging.

[0048] 2) If the frequency of the locked signal output by the in-loop mixer phase-locked circuit is low (typically below 1 GHz), an AD acquisition circuit can be added to the application to collect the locked signal frequency and determine whether the signal is mislocked. This solution requires the addition of dedicated AD acquisition and processing circuits, which increases the circuit size, efficiency, and cost, and also limits the applicable frequency band.

[0049] 3) When the signal frequency locked and output by the in-loop mixing phase-locked circuit is relatively high (usually above 1 GHz), a frequency conversion circuit is usually required to first convert the high-frequency signal to a low-frequency band (usually below 1 GHz), and then use the AD acquisition and processing calculation circuit in item 2 to determine whether the signal is mislocked. This solution is more complex and requires adding a frequency conversion circuit, AD acquisition, digital processing circuit, etc. The efficiency, volume, and cost of the determination circuit far exceed those of the in-loop mixing phase-locked circuit and do not have engineering practicability.

[0050] Based on the above, in actual engineering applications, there is an urgent need for a simpler, more convenient, and practical auxiliary circuit to correctly determine whether the in-loop mixing phase-locked circuit is correctly locked (identify mislocking), so as to provide guarantee for the correct and reliable locking of the circuit.

[0051] To solve this technical problem, in the technical solution concept of the present invention, a continuously variable frequency divider ratio (integer and fractional frequency division) frequency divider and a time window counter are combined. By splitting and dividing the VCO signal and the reference signal after the in-loop mixing phase-locked loop is locked, and continuously counting the number of times the two divided signals fall within the window time, it is determined whether the signal after the in-loop mixing phase-locked loop is correctly locked, solving the problem that the signal cannot be effectively detected after mislocking, and having characteristics such as a reliable mislocking discrimination mechanism, simple circuit structure, and easy integration and implementation.

[0052] In a further implementation, the technical solution of the present invention provides a circuit for judging the frequency mislocking of the in-loop mixing phase-locked loop signal, as Figure 4 shown, Figure 4 The solid arrows in represent the signal flow. For Figure 4 each component feature in, the following description is given.

[0053] The phase detector has the following characteristics: 1) internally integrated with an R frequency divider, a phase detection circuit, a CP circuit, an N frequency divider, and a locking detection circuit; 2) the R frequency divider divides the signal entering the REF terminal and then enters the phase detection circuit and the locking discrimination circuit; 3) the N frequency divider divides the signal entering the RF terminal and then enters the phase detection circuit and the locking discrimination circuit; 4) the phase detection and CP circuit convert the phase difference information of the two input signals into a current value for output.

[0054] The power splitter has the following characteristics: equally distributes the input signal according to the number of output paths.

[0055] Mixing has the following characteristics: 1) mixes the lower sideband of a VCO signal θ VCO (t) output by power splitting with the inserted signal θ1(t) and then enters the RF terminal; 2) the frequency of the inserted signal θl(t) is based on the VCO output frequency and the mixed frequency θ rf(t) Determine; 3) Usually, it is required that the phase noise level of the inserted signal for input mixing is better than that of the feedback signal; 4) A filter may be required at the mixer output.

[0056] The loop filter has the following characteristics: 1) It can be an active or passive loop filter, which is specifically determined according to the tuning voltage required by the VCO and the highest voltage of the phase detector CP; 2) The circuit parameter values of the loop filter need to be calculated and determined according to the technical specifications of the entire phase-locked loop.

[0057] The VCO has the following characteristics: 1) It can output a sine wave signal with a corresponding frequency according to the given tuning voltage value; 2) The phase noise of the VCO output signal needs to meet the design index requirements.

[0058] The 1 / 2 / 4 / 8 variable frequency divider has the following characteristics: 1) It can directly pass through, divide by 1 / 2, 1 / 4, or 1 / 8 the VCO signal output by power splitting according to the frequency of the VCO output signal and the operating frequency band of the N frequency divider of the false lock discriminator; 2) A filter may be required at the output end of the frequency divider according to requirements.

[0059] The false lock discriminator has the following characteristics: 1) It has an N frequency divider, an R frequency divider, and a lock discrimination circuit inside; 2) It can be implemented using part of the circuit in the main integrated phase detector; 3) The signal at the input RF terminal is divided by N, and the signal at the input REF terminal is divided by R and then enters the lock discrimination circuit. The lock discrimination time window is fixed, and the number of times the time difference between the two is continuously less than the set time window is recorded. When it reaches 2048 times, it can be determined to be locked.

[0060] Combined with Figure 3 , the circuit working process of discriminating the false lock of the mixer phase-locked loop signal in the discrimination loop is described as follows.

[0061] Define the output signal obtained by the in-loop mixer phase-locked loop as θ VCO (t) = θ rf (t) + θ1(t), and the control division value of the variable frequency divider is 2.

[0062] Process 1: The REF signal θ ref (t) is equally divided into two paths with the same phase and output, and are respectively connected to the in-loop mixer phase-locked loop and the false lock determination circuit as reference signals.

[0063] Process 2: The VCO output signal θ VCO (t) is equally divided into three paths with the same phase and output, and are respectively used as the phase-locked output, the return mixing signal of the in-loop mixer phase-locked loop, and the input signal of the variable frequency divider in the false lock determination circuit.

[0064] Process 3: One of the paths θ VCO(t) is mixed with and filtered from the inserted signal θ1(t), and then sent to the phase discriminator. Set the R division value to R1, the N division value to N1, and other phase discriminator register parameters in the loop filter and phase discriminator, so that the in-loop mixer PLL is locked, and the phase discriminator lock indication outputs a high level (the circuit is locked).

[0065] Process 4: Set the R division value in the false lock determination circuit to R1 and the N division value to N2 (the value calculation is shown in Formula 1). When the in-loop mixer PLL is locked, the following two situations will occur:

[0066] a) When the VCO locking frequency is correct, that is, θ VCO (t) = θ rf (t) + θ1(t), according to Formula 1, after setting the value of N2, the signal frequencies at the two input terminals of the lock determination in the false lock discrimination will be the same and have the same source and phase coherence. At this time, after reasonably setting the detection time window, the lock determination circuit will output a high level, indicating that the in-loop mixer PLL is correctly locked.

[0067] b) When the VCO locking frequency is incorrect, that is, θ VCO (t) = θ1(t) - θ rf (t), according to Formula 1, after setting the value of N2, the signal frequencies at the two input terminals of the lock determination in the false lock discrimination are different. At this time, after reasonably setting the detection time window, they will not continuously appear within the time window, and the lock determination circuit will output a low level, indicating that the in-loop mixer PLL is falsely locked.

[0068]

[0069] Process 5: Obtain the lock indication level of the in-loop mixer PLL (defined as bit b1) and the lock indication level in the false lock determination circuit (defined as bit b0). When b1b0 = 11, it indicates that the output frequency of the in-loop mixer PLL is correctly locked; when b1b0 = 10, it indicates that the output frequency of the in-loop mixer PLL is falsely locked; in other cases, it is not locked.

[0070] Two points need to be explained:

[0071] 1. In most PLL devices on the market at present, the R and N dividers and the lock detection circuit have been integrated. The lock detection in the above in-loop mixing and false lock determination circuits directly uses this function integrated inside the PLL device.

[0072] 2. A 1 / 2 / 4 / 8 variable divider is added to the false lock discrimination circuit considering that if the VCO output frequency is greater than the operating frequency band of the N division in the false lock discrimination circuit, the VCO output frequency can be divided first to reduce the signal frequency to the N division operating frequency band. The specific division ratio can be determined according to the VCO output frequency and the N division operating frequency band.

[0073] Based on the technical solution of the present invention on the basis of the traditional in-loop mixing phase-locked loop circuit, by using the reference frequency of the original in-loop mixing phase-locked loop and the VCO output frequency (each is divided into one path for output), and cooperating with the externally added frequency division circuit and the locking discrimination circuit, the determination of the mislocking of the in-loop mixing phase-locked signal is realized, and it has the following beneficial effects:

[0074] 1) The circuit is simple and reliable: The mislocking discrimination circuit in the present invention, on the basis of the original in-loop mixing phase-locked circuit, only needs to use three parts of the power divider, variable frequency divider and locking detection circuit to realize the mislocking determination function. The whole circuit structure is simple, and there is no need for complex circuit debugging, calculation, etc., which is simple and reliable.

[0075] 2) The mislocking determination is accurate and effective: The mislocking discrimination circuit in the present invention realizes the mislocking determination by controlling the frequency division ratio, the locking detection window time and 2048 times of counting. The mislocking determination standard is the same as the single-phase-locked loop standard (falling within the window continuously for 2048 times), ensuring accuracy and effectiveness.

[0076] 3) The circuit has low cost, low power consumption and small volume, and is easy to be integrated and used: For the mislocking discrimination circuit in the present invention, there are mature and available monolithic integrated circuits. Its power consumption does not exceed 100mw, and the cost, volume and power consumption evaluation are all convenient to be integrated into the in-loop mixing phase-locked loop circuit to realize the mislocking determination following the main circuit in a timely manner.

[0077] 4) Wide working frequency range: The working frequency range of the mislocking discrimination circuit in the present invention is mainly limited by the working range of the frequency divider. The frequency divider integrated inside the same phase discriminator in the original in-loop mixing phase-locked circuit is used in the circuit, and an external frequency divider is added. The working frequency range can reach 26GHz, which can meet the requirements of most mislocking determination circuits.

[0078] 5) The mislocking determination signal is easy to collect, improving the real-time self-checking ability of the system: The mislocking determination signal output by the mislocking discrimination circuit in the present invention is a voltage signal of 2.7~3.3V. When applied in the system, the system status acquisition board or the upper-level circuit can directly receive this mislocking determination signal, and can detect whether the circuit is mislocked in real time according to this signal, greatly improving the system fault self-checking ability.

[0079] Based on the method for discriminating the mislocking of the in-loop mixing type phase-locked loop signal described in the technical solution of the embodiment of the present invention, the circuit design is carried out. The peripheral configuration circuit of the device can be built according to the device manual and the reference circuit provided by the manufacturer, which will not be elaborated here. The following mainly describes four aspects: the selection of main devices, key signals and their connections with the devices, the working process, and the test results.

[0080] 1. Device selection

[0081] a) The phase detector selects HMC704LP4E, which integrates circuits such as R divider, phase detector, lock detection, N divider, and charge pump CP. The N divider has the function of fractional division. By setting the division values of R and N, the signals entering the two are divided, and the phase difference information is discriminated in the phase detector, and then converted into a current output through CP. When the phase difference between the two is stable, it means that the output signal frequencies of the two dividers are the same. At this time, the time difference between the two divided signals will continuously fall within the time window set in the lock detection circuit. When it meets 2048 times continuously, a high level will be output, and it is determined that the VCO is correctly locked on the reference signal.

[0082] b) The VCO selects HMC6380LC4B, with an output frequency of 8 - 16 GHz and a tuning voltage of 0 - 23 V.

[0083] c) The loop filter adopts an active form, and the operational amplifier uses OPA211AIDRGR.

[0084] d) The mixer adopts GNM3104.

[0085] e) The 1 / 2 / 4 / 8 variable divider adopts HMC862ALP3E, with an operating frequency band of 0.1 - 15 GHz.

[0086] f) The false lock discrimination uses the R divider, N divider, and part of their lock detection functional circuits integrated in HMC704LP3E.

[0087] 2. Key signals and connections with devices

[0088] a) The reference signal θ ref (t) adopts a 100 MHz signal generated by a temperature-controlled crystal oscillator. After being divided into two paths by a power divider 1, they are respectively connected to the XREFP (pin 19) of two HMC704LP4E1.

[0089] b) The phase detection output signal A is led out from the CP (pin 16) of HMC704LP4E(2) and connected to the loop filter. After being integrated by the loop filter, the output tuning control voltage B is connected to the Vtune (pin 4) of HMC6380LC4B. See Figure 6 as shown.

[0090] c) The RFOUT (pin 15) of HMC6380LC4B outputs the θ VCO (t) signal. After being divided into three equal paths by a power divider 2, one path is connected to the LO port of GNM3104 (bare chip), the inserted mixing signal θ1(t) is connected to the RF port, and the signal output from the IF port is low-pass filtered to generate θ rf (t) and connected to the VCOIP (pin 6) of HMC704LP4E(1).

[0091] d) Another path of the output of the power divider 2, θ VCO (t) signal is connected to the RFIN (pin 2) of HMC862ALP3E. The divided-frequency signal output from its RFOUT (pin 11) is low-pass filtered to be signal and connected to the VCOIP (pin 6) of HMC704LP4E(2)

[0092] For the overall built circuit, the peripheral circuits irrelevant to the core idea of the technical solution of the present invention are omitted. See Figure 6 。

[0093] 3. Working process

[0094] The working process of the implementation example is described as follows. By default, the control of each device is carried out according to the control method given in the device manual.

[0095] a) Set the target frequency θ VCO (t) = 14 GHz, insert the mixing signal frequency θ1(t) = 12 GHz, and the phase noise level of the inserted signal is better than that of the feedback signal.

[0096] b) Control each register in HMC704LP4E(1) in the in-loop mixing and phase-locked loop circuit, set its phase detection frequency to 50 MHz, that is, R division = 2, N division = 40, use the digital mode for lock detection, set the detection window time to 12.8 ns, and adjust the circuit to achieve locking.

[0097] c) Control each register in HMC704LP4E(2) in the false lock discrimination circuit, set its phase detection frequency to 50 MHz, turn on the internal pre-stage 2 division, that is, R division = 2, N division = 70, use the digital mode for lock detection, set the detection window time to 11 ns, and control HMC862ALP3E to be 2 division.

[0098] d) When the lock detection bit b1 = 1 (port voltage ≥ 2.5 V) of HMC704LP4E(1) in the in-loop mixing and phase-locked loop circuit, the following discrimination can be made according to the lock detection bit b0 state of HMC704LP4E(2) in the false lock discrimination circuit:

[0099] 1) When the lock detection bit b0 = 1 (port voltage ≥ 2.5 V) of HMC704LP4E(2) in the false lock discrimination circuit, it can be determined that the in-loop mixing and phase-locked loop circuit is correctly locked, that is, θ VCO (t) = 14 GHz;

[0100] 2) When the lock detection bit b0 = 0 (port voltage ≤ 0.8 V) of HMC704LP4E(2) in the false lock discrimination circuit, it can be determined that the in-loop mixing and phase-locked loop circuit is falsely locked, that is, θVCO θ(t) = 10 GHz.

[0101] 4. Test Results

[0102] Through the experimental verification of the above examples, when the in-loop mixer PLL is correctly locked, i.e., θ VCO (t) = 14 GHz; using a multimeter to test the voltage values of the two lock detection bits b1 and b0 are both 2.7 V, i.e., b1b0 = 11; when the in-loop mixer PLL is mislocked, i.e., θ VCO (t) = 10 GHz; using a multimeter to test the two lock detection bits b1 and b0, the voltage value of b1 is 2.7 V, and the voltage value of b0 is 0.2 V, i.e., b1b0 = 10; the above tests show that a method for discriminating mislocking of in-loop mixer PLL signals in the technical solution of the present invention is feasible and has significant beneficial effects.

[0103] It should be noted that within the protection scope defined in the claims of the present invention, the following embodiments can all be combined and / or extended, replaced in any logical manner from the above specific implementation manners, such as the disclosed technical principles, disclosed technical features or implicitly disclosed technical features, etc.

[0104] Embodiment 1

[0105] A circuit for judging incorrect locking of the frequency of an in-loop mixer PLL signal, including a first power splitter, an in-loop mixer PLL, and a mislock determination circuit, splitting the REF signal θ ref (t) into two equal-phase outputs through the first power splitter, and respectively connecting them to the in-loop mixer PLL and the mislock determination circuit as reference signals;

[0106] The in-loop mixer PLL includes a phase detector, a loop filter, a VCO, a second power splitter, and a mixer, splitting the VCO output signal θ VCO (t) into three equal-phase outputs through the second power splitter, respectively serving as the phase-locked output, the return mixer signal of the in-loop mixer PLL, and the input signal of the variable frequency divider in the mislock determination circuit; one of the θ VCO (t) is mixed with the inserted signal θ1(t), filtered, and then sent to the phase detector;

[0107] The mislock determination circuit includes a variable frequency divider and a mislock discriminator, and the variable frequency divider performs frequency division processing on the power-divided VCO output signal and then outputs it to the mislock discriminator.

[0108] Embodiment 2

[0109] Based on Embodiment 1, define the output signal obtained by the in-loop mixer PLL as θ VCO (t) = θ rf(t) + θ1(t), the control division ratio value of the variable frequency divider is 2;

[0110] In the in-loop mixing phase-locked loop, set the R division ratio value in the loop filter and phase detector to R1, the N division ratio value to N1, and other phase detector register parameters to lock the in-loop mixing phase-locked loop, and the phase detector lock indication outputs a high level;

[0111] In the false lock determination circuit, set the R division ratio value in the false lock determination circuit to R1 and the N division ratio value to N2. When the in-loop mixing phase-locked loop is locked, the following two situations will occur:

[0112] a) When the VCO locked frequency is correct, that is, θ VCO (t) = θ rf (t) + θ1(t), according to formula (1), after setting the N2 value, the signal frequencies at the two input terminals of the lock detection in the false lock discrimination will be the same and have the same source and phase coherence. At this time, after reasonably setting the detection time window, the lock discrimination circuit will output a high level, indicating that the in-loop mixing phase-locked loop is correctly locked;

[0113] b) When the VCO locked frequency is incorrect, that is, θ VCO (t) = θ1(t) - θ rf (t), according to formula (1), after setting the N2 value, the signal frequencies at the two input terminals of the lock detection in the false lock discrimination are different. At this time, even if the lock detection time window is reasonably set, they will not continuously appear within the lock detection time window, and the lock discrimination circuit will output a low level, indicating that the in-loop mixing phase-locked loop is falsely locked;

[0114]

[0115] Among them, θ div (t) is the output signal of the variable frequency divider;

[0116] Define the lock indication level of the in-loop mixing phase-locked loop as bit b1 and the lock indication level in the false lock discrimination circuit as bit b0. When b1b0 = 11, it indicates that the output frequency of the in-loop mixing phase-locked loop is correctly locked; when b1b0 = 10, it indicates that the output frequency of the in-loop mixing phase-locked loop is falsely locked; in other cases, it is not locked.

[0117] Embodiment 3

[0118] Based on Embodiment 1, the phase detector includes an R frequency divider, a phase discrimination circuit, a CP circuit, an N frequency divider, and a lock detection circuit. The R frequency divider divides the signal entering the REF terminal and then enters the phase discrimination circuit and the lock detection circuit. The N frequency divider divides the signal entering the RF terminal and then enters the phase discrimination circuit and the lock detection circuit. The phase discrimination circuit and the CP circuit convert the phase difference information of the two input signals into a current value for output.

[0119] Embodiment 4

[0120] Based on Embodiment 1, one path of VCO signal θ VCO (t) output by power splitting is down-converted with the inserted signal θ1(t) and then enters the RF end of the phase detector; the frequency of the inserted signal θ1(t) is determined according to the output frequency of the VCO and the frequency θ rf (t) after mixing, and the phase noise level of the inserted signal input for mixing is better than that of the feedback signal.

[0121] Embodiment 5

[0122] Based on Embodiment 1, the loop filter includes an active or passive loop filter.

[0123] Embodiment 6

[0124] Based on Embodiment 1, the VCO outputs a sine wave signal with a corresponding frequency according to a given tuning voltage value.

[0125] Embodiment 7

[0126] Based on Embodiment 1, the variable frequency divider includes a 1 / 2 / 4 / 8 variable frequency divider, and divides the VCO signal output by power splitting directly, by 1 / 2, 1 / 4 or 1 / 8 according to the output signal frequency of the VCO and the operating frequency band of the N frequency divider of the false lock discriminator.

[0127] Embodiment 8

[0128] Based on Embodiment 1, the false lock discriminator includes an N frequency divider, an R frequency divider, and a lock detection circuit, divides the signal input to the RF end of the false lock discriminator by N and divides the signal input to the REF end of the false lock discriminator by R and then enters the lock detection circuit, fixes the lock discrimination time window, records the number of times that the time difference between the two is continuously less than the set time window, and can be determined to be locked when it reaches 2048 times.

[0129] Embodiment 9

[0130] A method for judging the false lock of the signal frequency in the loop mixer phase-locked loop, based on the circuit for judging the false lock of the signal frequency in the loop mixer phase-locked loop as described in any one of Embodiments 1 to 9, includes the steps of:

[0131] S1, set the target frequency θ VCO (t), insert the frequency of the mixing signal θ1(t), and the phase noise level of the inserted signal is better than that of the feedback signal;

[0132] S2, control each register of the phase detector in the loop mixer phase-locked circuit, set its phase detection frequency, use the digital mode for lock detection, set the detection window time, and adjust the circuit to achieve locking;

[0133] S3. Control the two registers of the phase discriminator in the error locking discrimination circuit, set its phase discrimination frequency, turn on the internal pre-stage 2-frequency division, use the digital mode for locking detection, set the detection window time, and control the VCO to be 2-frequency division;

[0134] S4. When the locking detection bit b1 of the phase discriminator 1 in the in-loop mixing and phase-locking circuit is b1 = 1, judge the following two situations according to the state of the locking detection bit b0 of the phase discriminator 2 in the error locking discrimination circuit:

[0135] 1) When the locking detection bit b0 of the phase discriminator 2 in the error locking discrimination circuit is b0 = 1 and the port voltage ≥ 2.5V, it is judged that the in-loop mixing and phase-locking circuit is correctly locked;

[0136] 2) When the locking detection bit b0 of the phase discriminator 2 in the error locking discrimination circuit is b0 = 0 and the port voltage ≤ 0.8V, it is judged that the in-loop mixing and phase-locking circuit is erroneously locked.

[0137] Embodiment 10

[0138] On the basis of Embodiment 1, in setting the phase discrimination frequency in step S2, set R frequency division = 2, N frequency division = 40, and in setting the phase discrimination frequency in step S3, set R frequency division = 2, N frequency division = 70.

[0139] The units involved in the embodiments described in the present invention can be implemented in software or in hardware, and the described units can also be set in the processor. Among them, the names of these units do not constitute a limitation to the unit itself in some cases.

[0140] According to one aspect of the embodiments of the present invention, a computer program product or a computer program is provided. The computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the methods provided in the above various optional implementation manners.

[0141] As another aspect, the embodiments of the present invention also provide a computer-readable medium, which may be included in the electronic device described in the above embodiments; or may exist alone without being assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the one or more programs are executed by an electronic device, the electronic device realizes the methods described in the above embodiments.

[0142] The parts not involved in the present invention are the same as the prior art or can be implemented by the prior art.

[0143] The above technical solution is only one implementation manner of the present invention. For those skilled in the art, based on the disclosed application methods and principles of the present invention, it is very easy to make various types of improvements or deformations, not limited to the methods described in the above specific implementation manners of the present invention. Therefore, the manner described above is only preferred and does not have a restrictive meaning.

[0144] In addition to the above examples, those skilled in the art can obtain inspiration according to the above disclosure or make other embodiments by using the knowledge or technology in related fields. The features of each embodiment can be interchanged or replaced. As long as the changes and variations made by those skilled in the art do not depart from the spirit and scope of the present invention, they should all be within the protection scope of the appended claims of the present invention.

Claims

1. A circuit for judging frequency mislocking of a signal in a ring mixer phase-locked loop, characterized in that, Including a first power divider, an in-loop mixer phase-locked loop, and a false lock determination circuit, the REF signal is equally power-divided into two paths through the first power divider and is respectively connected to the in-loop mixer phase-locked loop and the false lock determination circuit as reference signals; The in-loop mixer PLL includes a phase detector, a loop filter, a VCO, a second power divider, and a mixer, and the output signal of the VCO is equally divided into three paths with equal power through the second power divider, and is respectively used as the phase-locked output, the feedback mixer signal of the in-loop mixer PLL, and the input signal of the variable frequency divider in the false lock determination circuit; one of the paths is mixed and filtered with the inserted signal and then sent to the phase detector; The mislock determination circuit includes a variable frequency divider and a mislock discriminator. The variable frequency divider divides the VCO output signal output from the power splitter and then outputs it to the mislock discriminator. The mislock discriminator includes an N frequency divider, an R frequency divider, and a lock detection circuit. The signal input to the RF terminal of the mislock discriminator is divided by N, and the signal input to the REF terminal of the mislock discriminator is divided by R and then enters the lock detection circuit. The lock discrimination time window is fixed, and the number of times when the time difference between the two is continuously less than the set time window is recorded. When it reaches 2048 times, it can be determined as locked.

2. The circuit for judging the frequency mislock of the in-loop mixing phase-locked loop signal according to claim 1, wherein Define the output signal obtained by the ring mixer phase-locked loop as , and the control division value of the variable frequency divider is 2; In the in-loop mixing phase-locked loop, a loop filter, an R division value of R1 and an N division value of N1 in the phase detector, and other phase detector register parameters are set to lock the in-loop mixing phase-locked loop, and the lock indication output of the phase detector is at a high level. In the mislock determination circuit, the R division value in the mislock determination circuit is also set to R1, and the N division value is N2. When the in-loop mixing phase-locked loop is locked, the following two situations will occur: a) When the VCO locked frequency is correct, i.e., at this time, according to formula (1), after setting the value of N2, the signal frequencies at the two input terminals of the locked detection in the false lock discrimination will be the same and have the same source and coherence. At this time, after reasonably setting the detection time window, the lock discrimination circuit will output a high level, indicating that the in-loop mixer phase-locked loop is correctly locked; b) When the VCO locking frequency is incorrect, i.e., at this time, according to formula (1), after setting the value of N2, the signal frequencies at the two input terminals of the locking detection in the mislocking discrimination are different. At this time, even if the detection time window is set reasonably, they will not continuously appear within the detection time window, and the locking discrimination circuit will output a low level, indicating that the mixer PLL in the loop is mislocked; …………(1) Among them, is the output signal of the variable frequency divider; Define the lock indication level of the in-loop mixing phase-locked loop as bit b1 and the lock indication level in the mislock discrimination circuit as bit b0. When b1b0 = 11, it means that the output frequency of the in-loop mixing phase-locked loop is correctly locked; when b1b0 = 10, it means that the output frequency of the in-loop mixing phase-locked loop is mislocked; in other cases, it is not locked.

3. The circuit for judging the wrong locking of the frequency of the in-loop mixer-locked phase-locked loop signal according to claim 1, wherein The phase detector includes an R frequency divider, a phase detection circuit, a CP circuit, an N frequency divider, and a lock detection circuit. The R frequency divider divides the signal entering the REF terminal and then enters the phase detection circuit and the lock detection circuit. The N frequency divider divides the signal entering the RF terminal and then enters the phase detection circuit and the lock detection circuit. The phase detection circuit and the CP circuit convert the phase difference information of the two input signals into a current value and output it.

4. The circuit for judging the frequency mislocking of the in-loop mixer-locked PLL signal according to claim 1, characterized in that, The mixer mixes one path of the power-divided VCO signal with the inserted signal and then down-converts the result to the RF terminal of the phase detector; the inserted signal has a frequency determined based on the VCO output frequency and the down-converted frequency and the phase noise level of the inserted signal input to the mixer is better than that of the feedback signal.

5. The circuit for judging the frequency mislocking of the in-loop mixer PLL signal according to claim 1, characterized in that, The loop filter includes an active or passive loop filter.

6. The circuit for judging the frequency mislock of the in-loop mixer PLL signal according to claim 1, wherein The VCO outputs a sine wave signal with a corresponding frequency according to the given tuning voltage value.

7. The circuit for judging the frequency mislocking of the in-loop mixer-locked phase-locked loop signal according to claim 1, wherein The variable frequency divider includes a 1 / 2 / 4 / 8 variable frequency divider. According to the VCO output signal frequency and the operating frequency band of the N frequency divider of the mislock discriminator, the VCO signal output from the power splitter is directly passed, divided by 1 / 2, 1 / 4, or 1 / 8 and output.

8. A method for judging frequency mislocking of a signal in a ring mixer phase-locked loop, characterized in that, Based on the circuit for judging the frequency mislock of the in-loop mixing phase-locked loop signal according to any one of claims 1 to 7, it includes the steps: S1, Set the target frequency , Insert the frequency of the mixing signal , Insert a signal with a phase noise level better than that of the feedback signal; S2, control each register of the phase detector in the in-loop mixing phase-locked circuit, set its phase detection frequency, use the digital mode for lock detection, set the detection window time, and adjust the circuit to achieve locking. S3, control each register of the phase detector in the mislock discrimination circuit, set its phase detection frequency, turn on the internal pre-stage 2 division, use the digital mode for lock detection, set the detection window time, and control the VCO to be divided by 2. S4, when the lock detection bit b1 of the phase detector in the in-loop mixing phase-locked circuit is 1, judge the following two situations according to the state of the lock detection bit b0 of the phase detector in the mislock discrimination circuit: 1) When the locking detection bit b0 of the phase discriminator II in the error locking discrimination circuit is 1 and the port voltage ≥ 2.5V, the mixer phase-locked circuit in the discrimination loop is correctly locked; 2) When the locking detection bit b0 of the phase discriminator II in the error locking discrimination circuit is 0 and the port voltage ≤ 0.8V, the mixer phase-locked circuit in the discrimination loop is erroneously locked.

9. The method for judging the frequency mislocking of the in-loop mixer PLL signal according to claim 8, characterized in that, In setting the phase discrimination frequency in step S2, set the R division = 2 and the N division = 40. In setting the phase discrimination frequency in step S3, set the R division = 2 and the N division = 70.

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