A flow control method, device, terminal equipment and storage medium for SPI communication

Abstract

The present invention discloses a flow control method, device, terminal device and storage medium for SPI communication, the method is applied to a flow control system including SPI communication between a master device and a slave device, the communication channel between the master device and the slave device includes an SPI interface and two GPIO pins associated with the SPI interface; the method includes: data transmission between the master device and the slave device through the communication channel; when the slave device sends data to the master device, the second GPIO pin is set to a first state, and an interrupt signal is sent to the master device; after receiving the interrupt signal, the master device initiates transmission and receives data sent from the slave device; when the slave device detects that the first GPIO pin changes from a high level to a low level, it determines that the data frame transmission is completed. The present invention uses fewer GPIO pins, saves chip hardware resources, the master and slave devices can send data at any time, realizes data response and retransmission mechanism, ensures the real-time and reliability of data, and reduces the extra CPU overhead.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a flow control method, device, terminal equipment and storage medium for SPI communication. Background Art

[0002] According to the SPI communication principle, in each clock cycle, the SPI device will send and receive a bit of data (regardless of whether it is a master device or a slave device), which is equivalent to the device exchanging a bit of data. Since the clock is provided by the master device, the slave device cannot actively send data. If the slave device wants to send data at any time, the master device must use polling to continuously initiate transmission, and most of the time there is invalid data on the bus, resulting in additional CPU overhead for the master device. When the master and slave devices do not have a fixed frame length, the slave device does not know whether the data has been received. In addition, SPI has no specified flow control, no response mechanism to confirm whether the data has been received, or uses more GPIO pins to implement flow control and response, which is costly. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a flow control method, device, terminal equipment and storage medium for SPI communication, which use fewer GPIO pins, save chip hardware resources, and enable master and slave devices to send data at any time, realize data response and retransmission mechanism, ensure the real-time and reliability of data, and reduce the additional CPU overhead.

[0004] In order to achieve the above-mentioned object, an embodiment of the present invention provides a flow control method for SPI communication, which is applied to a flow control system for SPI communication, wherein the flow control system includes a master device and at least one slave device, and the communication channel between the master device and the slave device includes an SPI interface and two GPIO pins associated with the SPI interface; wherein the first GPIO pin is the input of the slave device and is connected to the CS pin in the SPI interface; the second GPIO pin is the output of the slave device and is connected to the master device, and the flow control method for SPI communication includes:

[0005] The master device and the slave device perform data transmission via the communication channel;

[0006] When the slave device sends data to the master device, the second GPIO pin is set to a first state, and an interrupt signal is sent to the master device;

[0007] After receiving the interrupt signal, the master device initiates transmission and receives data sent from the slave device;

[0008] When the slave device detects that the first GPIO pin changes from a high level to a low level, it determines that the data frame transmission is completed.

[0009] As an improvement to the above solution, when the slave device sends data to the master device, the interface transmission length of the slave device is set to a maximum frame length, and the interface transmission length of the master device is set to a minimum frame length.

[0010] As an improvement of the above solution, when the slave device detects that the first GPIO pin changes from a high level to a low level, it is determined that the data frame transmission is completed, and then the method further includes:

[0011] Determining whether the data frame returned from the master device is valid;

[0012] If valid, determine the type of the data frame returned from the master device; if it is a request frame, put the data frame returned by the master device into the receiving buffer of the slave device, generate a response frame of the request frame, and put it into the sending buffer of the slave device; if it is a response frame, set the response flag bit and transmit the next frame of data;

[0013] If it is invalid, the system directly enters the response waiting state. When a response is received, the sent data frame is removed from the sending buffer of the slave device, and the next frame of data is transmitted.

[0014] As an improvement to the above solution, when the master device initiates transmission, the sending buffer of the master device is cyclically detected;

[0015] When there are data frames to be sent in the sending buffer of the master device, the data frames to be sent are taken out with a preset frame length, and the SPI interface is called to send the data frames to be sent to the slave device.

[0016] As an improvement of the above solution, the calling of the SPI interface to send the to-be-sent data frame to the slave device further includes:

[0017] The master device receives the data frame returned from the slave device, and determines whether the returned data frame is valid;

[0018] If it is valid, the valid data frame will be processed, and after the processing is completed, it will enter the response waiting state;

[0019] If invalid, directly enter the answer waiting state;

[0020] If the response waiting timeout occurs, retransmission is initiated. If a response is received, the data frame to be sent is removed from the sending buffer of the master device, and the next frame of data is transmitted.

[0021] As an improvement of the above solution, the processing of the valid data frame specifically includes:

[0022] Determining whether the length of the valid data frame is not greater than the preset frame length;

[0023] If not, a secondary transmission is initiated to receive the remaining unreceived data;

[0024] If yes, determining the category of the valid data frame;

[0025] If the valid data frame is a request frame, the valid data frame is placed in a receiving buffer of the master device, a response frame of the request frame is generated, and the response frame is placed in a sending buffer of the master device;

[0026] If the valid data frame is a response frame, the response flag is set and the next frame of data is transmitted.

[0027] As an improvement of the above solution, the length of the valid data frame is the sum of the frame header length, the data length and the check area length.

[0028] The embodiment of the present invention further provides a flow control device for SPI communication, which is applied to a flow control system for SPI communication. The flow control system includes a master device and at least one slave device. The communication channel between the master device and the slave device includes an SPI interface and two GPIO pins associated with the SPI interface. The first GPIO pin is an input of the slave device and is connected to a CS pin in the SPI interface. The second GPIO pin is an output of the slave device and is connected to the master device. The flow control device for SPI communication includes:

[0029] A transmission module, used for transmitting data between the master device and the slave device through the communication channel;

[0030] an interrupt module, configured to set the second GPIO pin to a first state and send an interrupt signal to the master device when the slave device sends data to the master device;

[0031] A receiving module, used for the master device to initiate transmission after receiving the interrupt signal, and receive data sent from the slave device;

[0032] The detection module is used to determine that the data frame transmission is completed when the slave device detects that the first GPIO pin changes from a high level to a low level.

[0033] An embodiment of the present invention further provides a terminal device, comprising a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor implements any of the above-mentioned flow control methods for SPI communication when executing the computer program.

[0034] An embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium includes a stored computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute any one of the above-mentioned SPI communication flow control methods.

[0035] Compared with the prior art, the beneficial effects of a flow control method, device, terminal device and storage medium for SPI communication provided by the embodiment of the present invention are: by adding two GPIO pins associated with the SPI interface to the communication channel between the master device and the slave device, wherein the first GPIO pin is the input of the slave device and is connected to the CS pin in the SPI interface; the second GPIO pin is the output of the slave device and is connected to the master device. Data is transmitted between the master device and the slave device through the communication channel; when the slave device sends data to the master device, the second GPIO pin is set to the first state and an interrupt signal is sent to the master device; after receiving the interrupt signal, the master device initiates transmission and receives data sent from the slave device; when the slave device detects that the first GPIO pin changes from a high level to a low level, it determines that the data frame transmission is completed. The embodiment of the present invention uses fewer GPIO pins, saves chip hardware resources, and the master and slave devices can send data at any time, realizing the data response and retransmission mechanism, ensuring the real-time and reliability of the data, and reducing the extra CPU overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a flow chart of a preferred embodiment of a flow control method for SPI communication provided by the present invention;

[0037] Figure 2 It is a structural schematic diagram of a preferred embodiment of a flow control system for SPI communication provided by the present invention;

[0038] Figure 3 It is a schematic diagram of a flow chart of initiating transmission from a device in a flow control method of SPI communication provided by the present invention;

[0039] Figure 4 It is a flow chart of a flow control method for SPI communication provided by the present invention after a master device receives a transmission request from a slave device;

[0040] Figure 5 It is a schematic diagram of a flow chart of a master device initiating transmission in a flow control method of SPI communication provided by the present invention;

[0041] Figure 6 It is a schematic diagram of a flow chart of a master device processing a valid data frame in a flow control method of SPI communication provided by the present invention;

[0042] Figure 7It is a structural schematic diagram of a valid data frame in a flow control method for SPI communication provided by the present invention;

[0043] Figure 8 It is a structural schematic diagram of a preferred embodiment of a flow control device for SPI communication provided by the present invention;

[0044] Fig. 9 It is a structural schematic diagram of a preferred embodiment of a terminal device provided by the present invention. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] See also Figure 1 , Figure 1 It is a flow chart of a preferred embodiment of a flow control method for SPI communication provided by the present invention. The flow control method for SPI communication is applied to a flow control system for SPI communication, the flow control system includes a master device and at least one slave device, the communication channel between the master device and the slave device includes an SPI interface and two GPIO pins associated with the SPI interface; wherein the first GPIO pin is the input of the slave device and is connected to the CS pin in the SPI interface; the second GPIO pin is the output of the slave device and is connected to the master device, and the flow control method for SPI communication includes:

[0047] S1, the master device and the slave device perform data transmission via the communication channel;

[0048] S2, when the slave device sends data to the master device, setting the second GPIO pin to a first state and sending an interrupt signal to the master device;

[0049] S3, the master device initiates transmission after receiving the interrupt signal and receives data sent from the slave device;

[0050] S4, when the slave device detects that the first GPIO pin changes from a high level to a low level, it determines that the data frame transmission is completed.

[0051] For details, please refer to Figure 2 , Figure 2The present invention provides a schematic diagram of a preferred embodiment of a flow control system for SPI communication. The flow control system for SPI communication in the embodiment of the present invention includes a master device and at least one slave device, and the communication channel between the master device and the slave device includes an SPI interface and two GPIO pins associated with the SPI interface. Among them, the first GPIO pin is the input of the slave device and is connected to the CS pin in the SPI interface. The second GPIO pin is the output of the slave device and is connected to the master device. The SPI interface includes MOSI, MISO, SCLK and CS signal lines. Among them, the SCLK, MOSI and CS signals are all generated by the master device, and SCLK is a clock signal for synchronizing data. MOSI is the master device output and the slave device input signal, and the master device transmits data to the slave device through this signal line. CS is a chip select signal for selecting a slave device, and the low level is valid. The MISO signal is generated by the slave device, and the master device reads the data of the slave device through the signal line. The MOSI and MISO signals are only valid when CS is at a low level, and MOSI and MISO transmit one bit of data in each clock cycle of SCLK. In the embodiment of the present invention, data is transmitted between the master device and the slave device through the communication channel. When the slave device actively sends data to the master device, the second GPIO pin is set to the first state and an interrupt signal is sent to the master device. The first state refers to GPIO2 being set from a high level (the default state is a high level) to a low level and then to a high level, because the master device uses a falling edge to trigger the interrupt. After receiving the interrupt signal, the master device initiates transmission and receives the data sent from the slave device. If the master device does not initiate transmission, the slave device will be blocked. When the slave device detects that the first GPIO pin changes from a high level to a low level, it determines that the data frame transmission is completed.

[0052] It should be noted that in SPI communication, the SPI master device sends data to the SPI slave device through the SCLK line at a frequency supported by the slave device, which means that the slave device cannot actively send data to the master device. The master device can only poll the slave device or the slave device can actively inform the master device of the arrival of data through an IO port. Therefore, the embodiment of the present invention adds two GPIO pins associated with the SPI interface to the communication channel between the master device and the slave device.

[0053] The embodiment of the present invention uses fewer GPIO pins to realize the flow control of SPI communication. The master device uses one GPIO pin and the slave device uses two GPIO pins. The hardware structure is simple and the chip hardware resources are saved. The slave device uses the maximum frame length for transmission, and the master device determines whether to perform secondary transmission by detecting the data length in the frame header. Therefore, the master and slave devices do not need to use a fixed frame length to send and receive data. The transmission frame length is determined by the actual data length required to be transmitted each time, thereby avoiding additional clock overhead. The slave device uses a GPIO interrupt to notify the master device to start transmission. The slave device can actively send data at any time, and the master device does not need to receive data cyclically, thereby reducing the CPU resource occupancy. The master and slave devices can send and receive data at any time and process the received data when sending, thereby realizing full-duplex transmission of valid data and greatly improving the communication rate of SPI. Both the master and slave devices have implemented a software response retransmission mechanism to ensure the correctness of each data transmission and reception.

[0054] In another preferred embodiment, when the slave device sends data to the master device, the interface transmission length of the slave device is set to the maximum frame length, and the interface transmission length of the master device is set to the minimum frame length.

[0055] Specifically, since the master device may initiate multiple calls and the slave device does not know how long each transmission will be, it is necessary to set the interface transmission length of the slave device to the maximum frame length and the interface transmission length of the master device to the minimum frame length.

[0056] In another preferred embodiment, when the slave device detects that the first GPIO pin changes from a high level to a low level, it is determined that the data frame transmission is completed, and then the following steps are further included:

[0057] Determining whether the data frame returned from the master device is valid;

[0058] If valid, determine the type of the data frame returned from the master device; if it is a request frame, put the data frame returned by the master device into the receiving buffer of the slave device, generate a response frame of the request frame, and put it into the sending buffer of the slave device; if it is a response frame, set the response flag bit and transmit the next frame of data;

[0059] If it is invalid, the system directly enters the response waiting state. When a response is received, the sent data frame is removed from the sending buffer of the slave device, and the next frame of data is transmitted.

[0060] For details, please refer to Figure 3 and Figure 4 , Figure 3 It is a flow chart of initiating transmission from a device in a flow control method of SPI communication provided by the present invention. Figure 4The present invention provides a flow chart of a flow control method of SPI communication provided by the present invention after the master device receives a transmission request from the slave device. When the slave device actively sends data to the master device, the data frame to be sent is taken out from the sending buffer of the slave device, the second GPIO pin is set to the first state, and an interrupt signal is sent to the master device to notify the master device to initiate transmission. After receiving the interrupt signal, the master device initiates transmission and receives data sent from the slave device. In the receiving state, when the slave device detects that the first GPIO pin changes from a high level to a low level, it is determined that the data frame transmission is completed, the receiving state is exited, and the received data is processed. It is determined whether the data frame returned from the master device is valid. If valid, the category of the data frame returned from the master device is determined. If it is a request frame, the data frame returned by the master device is placed in the receiving buffer of the slave device, and a response frame of the request frame is generated and placed in the sending buffer of the slave device. If it is a response frame, the response flag is set and the next frame of data is transmitted. If invalid, the response wait is directly entered, and the sent data frame is removed from the sending buffer of the slave device when the response is received, and the next frame of data is transmitted.

[0061] It should be noted that, unlike the master device processing the received valid data frame, the slave device does not need to perform secondary transmission, and can determine whether the entire data frame transmission is completed through the status of GPIO1.

[0062] The embodiment of the present invention uses fewer GPIO pins, saves chip hardware resources, and the master and slave devices can send data at any time, realizing a data response and retransmission mechanism, thereby ensuring the real-time and reliability of the data and reducing the extra CPU overhead.

[0063] In yet another preferred embodiment, when the master device initiates transmission, a sending buffer of the master device is cyclically detected;

[0064] When there are data frames to be sent in the sending buffer of the master device, the data frames to be sent are taken out with a preset frame length, and the SPI interface is called to send the data frames to be sent to the slave device.

[0065] For details, please refer to Figure 5 , Figure 5 The present invention provides a flow chart of a master device initiating transmission in a flow control method of SPI communication. When the master device initiates transmission, the sending task continuously loops to detect the sending buffer of the master device. When the sending buffer of the master device has a data frame to be sent, the data frame to be sent is taken out with a preset frame length sLen, and the SPI interface is called to send the data frame to be sent to the slave device.

[0066] In another preferred embodiment, the calling of the SPI interface to send the to-be-sent data frame to the slave device further comprises:

[0067] The master device receives the data frame returned from the slave device, and determines whether the returned data frame is valid;

[0068] If it is valid, the valid data frame will be processed, and after the processing is completed, it will enter the response waiting state;

[0069] If invalid, it will directly enter the answer waiting state;

[0070] If the response waiting timeout occurs, retransmission is initiated. If a response is received, the data frame to be sent is removed from the sending buffer of the master device, and the next frame of data is transmitted.

[0071] For details, please refer to Figure 6 , Figure 6 It is a flow chart of a master device processing a valid data frame in a flow control method of SPI communication provided by the present invention. When there is a data frame to be sent in the sending buffer of the master device, the data frame to be sent is taken out with a preset frame length, and after calling the SPI interface to send the data frame to be sent to the slave device, the master device receives the data frame returned from the slave device and determines whether the returned data frame is valid. If the data frame returned from the slave device is valid, the valid data frame is processed, and after the processing is completed, the response waiting is entered. If the data frame returned from the slave device is invalid, the response waiting is directly entered. If the response waiting timeouts, a retransmission is initiated, and when a response is received, the data frame to be sent is removed from the sending buffer of the master device, and the next frame of data is transmitted.

[0072] In another preferred embodiment, the processing of the valid data frame specifically includes:

[0073] Determining whether the length of the valid data frame is not greater than the preset frame length;

[0074] If not, a secondary transmission is initiated to receive the remaining unreceived data;

[0075] If yes, determining the category of the valid data frame;

[0076] If the valid data frame is a request frame, the valid data frame is placed in a receiving buffer of the master device, a response frame of the request frame is generated, and the response frame is placed in a sending buffer of the master device;

[0077] If the valid data frame is a response frame, the response flag is set and the next frame of data is transmitted.

[0078] Specifically, when the master device processes the valid data frame, it obtains the length rLen of the frame data from the frame header of the received data, and determines whether the length rLen of the valid data frame is not greater than the preset frame length sLen. If the length rLen of the valid data frame is greater than the preset frame length sLen, it means that there are still data frames sent by the slave device that have not been received, and it is necessary to call the SPI interface again to initiate a secondary transmission to complete the reception of the remaining data. If the length rLen of the valid data frame is not greater than the preset frame length sLen, it means that the data frames sent by the slave device have been fully received in this call, and the category of the valid data frame is further determined by the frame header information. If the valid data frame is a request frame, the valid data frame is placed in the receiving buffer of the master device, and a response frame of the request frame is generated and placed in the sending buffer of the master device. If the valid data frame is a response frame, it indicates that the master device has received a response to the last request frame, and the next frame of data can be transmitted.

[0079] As a preferred solution, the length of the valid data frame is the sum of the frame header length, the data length and the check area length.

[0080] For details, please refer to Figure 7 , Figure 7 It is a structural schematic diagram of a valid data frame in a flow control method of SPI communication provided by the present invention. In an embodiment of the present invention, a valid data frame includes a frame header, data and a check area. Among them, the frame header includes a flag, a sequence number and a total length. The flag identifies the data class of this frame, which can be a request frame sent by the master device to the slave device, a request frame sent by the slave device to the master device, a response frame sent by the master device to the slave device, and a response frame sent by the slave device to the master device. Sequence number, each request frame sent has a unique sequence number, and the corresponding response frame is consistent with its sequence number. Total length = frame header length + data length + check area length.

[0081] Correspondingly, the present invention also provides a flow control device for SPI communication, which can implement all processes of the flow control method for SPI communication in the above embodiment.

[0082] See also Figure 8 , Figure 8 It is a structural schematic diagram of a preferred embodiment of a flow control device for SPI communication provided by the present invention. The flow control device for SPI communication is applied to a flow control system for SPI communication, the flow control system includes a master device and at least one slave device, the communication channel between the master device and the slave device includes an SPI interface and two GPIO pins associated with the SPI interface; wherein the first GPIO pin is the input of the slave device and is connected to the CS pin in the SPI interface; the second GPIO pin is the output of the slave device and is connected to the master device, and the flow control device for SPI communication includes:

[0083] Transmission module 801, used for data transmission between the master device and the slave device through the communication channel;

[0084] An interrupt module 802, configured to set the second GPIO pin to a first state and send an interrupt signal to the master device when the slave device sends data to the master device;

[0085] A receiving module 803, configured for the master device to initiate transmission after receiving the interrupt signal and receive data sent from the slave device;

[0086] The detection module 804 is configured to determine that the data frame transmission is completed when the slave device detects that the first GPIO pin changes from a high level to a low level.

[0087] Preferably, when the slave device sends data to the master device, the interface transmission length of the slave device is set to a maximum frame length, and the interface transmission length of the master device is set to a minimum frame length.

[0088] Preferably, when the slave device detects that the first GPIO pin changes from a high level to a low level, it is determined that the data frame transmission is completed, and then the method further includes:

[0089] Determining whether the data frame returned from the master device is valid;

[0090] If valid, determine the type of the data frame returned from the master device; if it is a request frame, put the data frame returned by the master device into the receiving buffer of the slave device, generate a response frame of the request frame, and put it into the sending buffer of the slave device; if it is a response frame, set the response flag bit and transmit the next frame of data;

[0091] If it is invalid, the system directly enters the response waiting state. When a response is received, the sent data frame is removed from the sending buffer of the slave device, and the next frame of data is transmitted.

[0092] Preferably, when the master device initiates transmission, a sending buffer of the master device is cyclically detected;

[0093] When there are data frames to be sent in the sending buffer of the master device, the data frames to be sent are taken out with a preset frame length, and the SPI interface is called to send the data frames to be sent to the slave device.

[0094] Preferably, the calling of the SPI interface to send the to-be-sent data frame to the slave device further comprises:

[0095] The master device receives the data frame returned from the slave device, and determines whether the returned data frame is valid;

[0096] If it is valid, the valid data frame will be processed, and after the processing is completed, it will enter the response waiting state;

[0097] If invalid, it will directly enter the answer waiting state;

[0098] If the response waiting timeout occurs, retransmission is initiated. If a response is received, the data frame to be sent is removed from the sending buffer of the master device, and the next frame of data is transmitted.

[0099] Preferably, the processing of the valid data frame specifically includes:

[0100] Determining whether the length of the valid data frame is not greater than the preset frame length;

[0101] If not, a secondary transmission is initiated to receive the remaining unreceived data;

[0102] If yes, determining the category of the valid data frame;

[0103] If the valid data frame is a request frame, the valid data frame is placed in a receiving buffer of the master device, a response frame of the request frame is generated, and the response frame is placed in a sending buffer of the master device;

[0104] If the valid data frame is a response frame, the response flag is set and the next frame of data is transmitted.

[0105] Preferably, the length of the valid data frame is the sum of the frame header length, the data length and the check area length.

[0106] In the specific implementation, the working principle, control process and technical effect achieved by the flow control device for SPI communication provided in the embodiment of the present invention are the same as those of the flow control method for SPI communication in the above embodiment, and will not be repeated here.

[0107] See also Fig. 9 , Fig. 9 1 is a schematic diagram of a preferred embodiment of a terminal device provided by the present invention. The terminal device includes a processor 901, a memory 902, and a computer program stored in the memory 902 and configured to be executed by the processor 901. When the processor 901 executes the computer program, the flow control method of SPI communication described in any of the above embodiments is implemented.

[0108] Preferably, the computer program can be divided into one or more modules / units (such as computer program 1, computer program 2, ...), and the one or more modules / units are stored in the memory 902 and executed by the processor 901 to complete the present invention. The one or more modules / units can be a series of computer program instruction segments that can complete specific functions, and the instruction segments are used to describe the execution process of the computer program in the terminal device.

[0109] The processor 901 can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor, or the processor 901 can be any conventional processor. The processor 901 is the control center of the terminal device, and various parts of the terminal device are connected using various interfaces and lines.

[0110] The memory 902 mainly includes a program storage area and a data storage area, wherein the program storage area can store an operating system, an application required for at least one function, etc., and the data storage area can store related data, etc. In addition, the memory 902 can be a high-speed random access memory, or a non-volatile memory, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, and a flash card (Flash Card), etc., or the memory 902 can also be other volatile solid-state storage devices.

[0111] It should be noted that the above terminal device may include, but is not limited to, a processor and a memory. Those skilled in the art will understand that Fig. 9 The structural diagram is only an example of the above-mentioned terminal device and does not constitute a limitation of the above-mentioned terminal device. It may include more or less components than shown in the figure, or combine certain components, or different components.

[0112] An embodiment of the present invention further provides a computer-readable storage medium, which includes a stored computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute the SPI communication flow control method described in any of the above embodiments.

[0113] The embodiment of the present invention provides a flow control method, device, terminal device and storage medium for SPI communication, by adding two GPIO pins associated with the SPI interface to the communication channel between the master device and the slave device, wherein the first GPIO pin is the input of the slave device and is connected to the CS pin in the SPI interface; the second GPIO pin is the output of the slave device and is connected to the master device. Data is transmitted between the master device and the slave device through the communication channel; when the slave device sends data to the master device, the second GPIO pin is set to the first state and an interrupt signal is sent to the master device; after receiving the interrupt signal, the master device initiates transmission and receives data sent from the slave device; when the slave device detects that the first GPIO pin changes from a high level to a low level, it determines that the data frame transmission is completed. The embodiment of the present invention uses fewer GPIO pins, saves chip hardware resources, and the master and slave devices can send data at any time to implement data response and retransmission mechanisms, ensure the real-time and reliability of data, and reduce the extra CPU overhead.

[0114] It should be noted that the system embodiment described above is merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, in the drawings of the system embodiment provided by the present invention, the connection relationship between the modules indicates that there is a communication connection between them, which may be specifically implemented as one or more communication buses or signal lines. A person of ordinary skill in the art may understand and implement it without paying any creative effort.

[0115] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A flow control method for SPI communication, characterized in that: A flow control system applied to SPI communication, the flow control system comprising a master device and at least one slave device, the communication channel between the master device and the slave device comprising an SPI interface and two GPIO pins associated with the SPI interface; wherein the first GPIO pin is the input of the slave device and is connected to the CS pin in the SPI interface; the second GPIO pin is the output of the slave device and is connected to the master device, and the flow control method of the SPI communication comprises: The master device and the slave device perform data transmission via the communication channel; When the slave device sends data to the master device, the second GPIO pin is set to a first state, and an interrupt signal is sent to the master device; wherein the first state refers to the second GPIO pin being set from a high level to a low level and then to a high level; After receiving the interrupt signal, the master device initiates transmission and receives data sent from the slave device; When the slave device detects that the first GPIO pin changes from a high level to a low level, determining that the data frame transmission is completed; When the slave device detects that the first GPIO pin changes from a high level to a low level, it is determined that the data frame transmission is completed, and then the method further includes: Determining whether the data frame returned from the master device is valid; If valid, determine the type of the data frame returned from the master device; if it is a request frame, put the data frame returned by the master device into the receiving buffer of the slave device, generate a response frame of the request frame, and put it into the sending buffer of the slave device; if it is a response frame, set the response flag bit and transmit the next frame of data; If it is invalid, the system directly enters the response waiting state. When a response is received, the sent data frame is removed from the sending buffer of the slave device, and the next frame of data is transmitted.

2. The flow control method for SPI communication as claimed in claim 1, characterized in that: When the slave device sends data to the master device, the interface transmission length of the slave device is set to the maximum frame length, and the interface transmission length of the master device is set to the minimum frame length.

3. The flow control method for SPI communication as claimed in claim 2, characterized in that: When the master device initiates transmission, cyclically detecting the sending buffer of the master device; When there are data frames to be sent in the sending buffer of the master device, the data frames to be sent are taken out with a preset frame length, and the SPI interface is called to send the data frames to be sent to the slave device.

4. The flow control method for SPI communication as claimed in claim 3, characterized in that: The calling of the SPI interface to send the to-be-sent data frame to the slave device further comprises: The master device receives the data frame returned from the slave device, and determines whether the returned data frame is valid; If it is valid, the valid data frame will be processed, and after the processing is completed, it will enter the response waiting state; If invalid, directly enter the answer waiting state; If the response waiting timeout occurs, retransmission is initiated. If a response is received, the data frame to be sent is removed from the sending buffer of the master device, and the next frame of data is transmitted.

5. The flow control method for SPI communication as claimed in claim 4, characterized in that: The processing of the valid data frame specifically includes: Determining whether the length of the valid data frame is not greater than the preset frame length; If not, a secondary transmission is initiated to receive the remaining unreceived data; If yes, determining the category of the valid data frame; If the valid data frame is a request frame, the valid data frame is placed in a receiving buffer of the master device, a response frame of the request frame is generated, and the response frame is placed in a sending buffer of the master device; If the valid data frame is a response frame, the response flag is set and the next frame of data is transmitted.

6. The flow control method for SPI communication as claimed in claim 5, characterized in that: The length of the valid data frame is the sum of the frame header length, the data length and the check area length.

7. A flow control device for SPI communication, characterized in that: A flow control system applied to SPI communication, the flow control system comprising a master device and at least one slave device, the communication channel between the master device and the slave device comprising an SPI interface and two GPIO pins associated with the SPI interface; wherein the first GPIO pin is the input of the slave device and is connected to the CS pin in the SPI interface; the second GPIO pin is the output of the slave device and is connected to the master device, and the flow control device of the SPI communication comprises: A transmission module, used for transmitting data between the master device and the slave device through the communication channel; An interrupt module, configured to set the second GPIO pin to a first state and send an interrupt signal to the master device when the slave device sends data to the master device; wherein the first state refers to the second GPIO pin being set from a high level to a low level and then to a high level; A receiving module, used for the master device to initiate transmission after receiving the interrupt signal, and receive data sent from the slave device; A detection module, configured to determine that data frame transmission is completed when the slave device detects that the first GPIO pin changes from a high level to a low level; When the slave device detects that the first GPIO pin changes from a high level to a low level, it is determined that the data frame transmission is completed, and then the method further includes: Determining whether the data frame returned from the master device is valid; If valid, determine the type of the data frame returned from the master device; if it is a request frame, put the data frame returned by the master device into the receiving buffer of the slave device, generate a response frame of the request frame, and put it into the sending buffer of the slave device; if it is a response frame, set the response flag bit and transmit the next frame of data; If it is invalid, the system directly enters the response waiting state. When a response is received, the sent data frame is removed from the sending buffer of the slave device, and the next frame of data is transmitted.

8. A terminal device, characterized in that: It comprises a processor and a memory, wherein a computer program is stored in the memory, and the computer program is configured to be executed by the processor, and when the processor executes the computer program, the flow control method for SPI communication as claimed in any one of claims 1 to 6 is implemented.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein when the device where the computer-readable storage medium is located executes the computer program, the flow control method for SPI communication according to any one of claims 1 to 6 is implemented.

Images