A shortwave BPM timing receiving method and device capable of automatically adjusting the second pulse locking period

Abstract

The present invention provides a short-wave BPM timing receiving device capable of automatically adjusting the second pulse locking cycle, comprising an FPGA unit, a main control unit, a storage unit, an A / D conversion unit and a constant temperature crystal oscillator. The present invention adopts FPGA to realize digital BPM short-wave timing time processing and reception, adopts automatic adjustment of the locking cycle technology to continuously judge and lock the output of the received extracted BPM pulse signal, reduces the situation in which the pulse cannot be judged or there is a judgment error due to the unstable reception quality of the timing signal during the BPM short-wave timing reception process, can be used as an effective supplementary means for satellite timing, and has the function of providing user time information and second pulse signals in real time within the coverage area of ​​the short-wave timing system.

Description

Technical Field

[0001] The present invention relates to the technical field of wireless BPM shortwave time service, and specifically but not limited to, relates to a shortwave BPM time service receiving method and device capable of automatically adjusting a second pulse locking period. Background Art

[0002] Shortwave timing is a timing method that uses shortwave radio signals to broadcast standard time and standard frequency signals. It is still used by many countries due to its wide coverage, simple transmission equipment, low price and convenience. The call sign of the shortwave transmitter of the National Time Service Center of the Chinese Academy of Sciences is BPM. It uses 2.5MHz, 5MHz, 10MHz and 15MHz standard frequencies to broadcast alternately. The frequency selection will change with the season, but at any moment there are more than two frequencies working to ensure 24-hour continuous broadcasting, broadcasting timing information to the whole country and surrounding areas, which is an important timing method.

[0003] Traditional synchronization systems mostly use the Beidou timing system built by China or the GPS system dominated by the United States as wireless timing sources. However, due to the limited coverage of the current Beidou system or the security issues of GPS navigation signals, the timing system will have no timing source, thus affecting the use of the timing system. Shortwave timing can effectively supplement the wireless timing means of the timing system and improve the synchronization guarantee capability of the timing system.

[0004] In view of this, it is necessary to provide a new structure or method to solve at least part of the above problems. Summary of the invention

[0005] In view of one or more problems in the prior art, the present invention proposes a shortwave BPM timing receiving device which can automatically adjust the second pulse locking period, adopts FPGA to realize digital BPM shortwave timing time processing and reception, adopts automatic adjustment of locking period technology to continuously judge and lock the output of the received extracted BPM pulse signal, reduces the situation in which the pulse cannot be judged or there is a judgment error due to the unstable reception quality of the timing signal during the BPM shortwave timing reception process, and can be used as an effective supplement to satellite timing, and has the function of providing user time information and second pulse signals in real time within the coverage area of ​​the shortwave timing system.

[0006] The technical solution to achieve the purpose of the present invention is:

[0007] A short-wave BPM timing receiving device capable of automatically adjusting the second pulse locking cycle comprises an FPGA unit, a main control unit, a storage unit, an A / D conversion unit and a constant temperature crystal oscillator, wherein the storage unit is coupled to the FPGA unit, the analog-to-digital conversion unit is coupled to the control signal end of the FPGA unit, the output end of the constant temperature crystal oscillator is coupled to the clock input end of the FPGA unit, the output end of the FPGA unit is coupled to the main control unit and a time system, the input end of the main control unit is coupled to a button and a display screen, and the output end of the main control unit is coupled to the time system; wherein:

[0008] The analog-to-digital conversion unit is used to receive the wireless BPM shortwave analog signal and convert it into a BPM digital signal with a width of 8 bits;

[0009] FPGA unit, used to convert 8-bit BPM digital signal into pulse-per-second signal;

[0010] A main control unit, used to set time information, display time information and system status, and output time information according to the locked second pulse;

[0011] Storage unit, used for program burning and storage of FPGA unit;

[0012] The constant temperature crystal oscillator is used to provide a standard clock frequency for the FPGA unit.

[0013] Furthermore, in the short-wave BPM timing receiving device capable of automatically adjusting the pulse-per-second locking period of the present invention, the FPGA unit includes an analog-to-digital conversion control unit, a FIR filter unit and a pulse-per-second locking unit.

[0014] An analog-to-digital conversion control unit, used for reading a BPM digital signal with a width of 8 bits in a time sequence, converting it into a 16-bit digital signal in a data input sequence, and writing it into a dual-clock FIFO memory, that is, the 8-bit data read first is in the high order, and the 8-bit data read later is in the low order, and the width of the dual-clock FIFO memory is 16 bits and the depth is 8 bytes;

[0015] The FIR filter unit is used to read the 16-bit digital signal from the dual-clock FIFO memory and filter it to extract the valid data from the BPM shortwave timing signal;

[0016] The pulse-per-second locking unit is used to extract and lock the pulse-per-second of the filtered valid data.

[0017] Furthermore, in the short-wave BPM timing receiving device capable of automatically adjusting the pulse-per-second locking period of the present invention, the main control unit, the FPGA unit and the timing system are all connected by asynchronous serial ports.

[0018] A shortwave BPM timing receiving method capable of automatically adjusting the second pulse locking period, comprising:

[0019] S1, the analog-to-digital conversion unit receives the BPM shortwave analog signal and converts it into a digital signal with a width of 8 bits;

[0020] S2, the analog-to-digital conversion control unit reads the 8-bit digital signal in time sequence and converts it into a 16-bit digital signal in the order of signal input, and the FIR filter unit filters the 16-bit digital signal;

[0021] S3, using the filtered data to determine the rising and falling edges of the pulse, and to lock the second pulse, output the second pulse and minute signal to the main control unit for time information and status information processing, and provide the second pulse to the time system;

[0022] S4, the main control unit receives the second pulse and minute signal, sets the year, month, day, hour, minute, and second information through buttons, and performs minute and second calibration, as well as second timing, carry, run-second calculations based on the second pulse and minute signal, while displaying the second pulse lock status through LED;

[0023] S5. The main control unit outputs time information, second pulse information and current operating status to the time system according to the locked second pulse and the set time information.

[0024] Further, the shortwave BPM timing receiving method capable of automatically adjusting the pulse-per-second locking period of the present invention, the specific steps of S3 include:

[0025] S3-1, use n groups of data to determine the rising and falling edges of the pulse. Whenever a new group of data fir_data_out is input, each group of data moves forward by one group of data, that is:

[0026] fir_data_reg_0<=fir_data_out;

[0027] fir_data_reg_1<=fir_data_reg_0;

[0028] fir_data_reg_2<=fir_data_reg_1;

[0029] …

[0030] fir_data_reg_n<=fir_data_reg_n-1;

[0031] S3-2, determine the rising and falling edges of the pulse:

[0032] (1) If the following three conditions are met, it is judged as a pulse rising edge, S3-3:

[0033] Condition 1:

[0034] fir_data_reg_0>fir_data_reg_1>fir_data_reg_2>…>fir_data_reg_n-1;

[0035] Condition 2: fir_data_reg_0, fir_data_reg_1, and fir_data_reg_2 must all be greater than the minimum judgment value sine_lower_value of the pulse rising edge;

[0036] Condition 3: fir_data_reg_0>={fir_data_reg_6[fir_data_width-2:0], 1'b0}; sine_lower_value is 200, fir_data_width is 16;

[0037] (2) If the following three conditions are met, it is judged as a pulse falling edge, S3-4:

[0038] Condition 1:

[0039] fir_data_reg_0 <fir_data_reg_1<…<fir_data_reg_n-1;

[0040] Condition 2: fir_data_reg_0, fir_data_reg_1, and fir_data_reg_2 must all be less than the maximum judgment value sine_high_value in the falling edge of the pulse;

[0041] Condition 3: fir_data_reg_0<{1'b0, fir_data_reg_6[fir_data_width-1:1]}; sine_high_value is 600, fir_data_width is 16;

[0042] S3-3, if it is judged to be a pulse rising edge, the rising edge confirmation signal is valid, and the pulse timer is started to start counting, and the clock is 10MHz;

[0043] S3-4. If it is judged to be a pulse falling edge, the falling edge confirmation signal is valid, the clock is 10MHz, and within the valid period of the falling edge confirmation signal, the UTC second pulse, UT1 second pulse, and PPM integer pulse are judged by the value of the pulse timer to obtain the pulse valid signal and output it to the main control unit and the timing system. The pulse valid signal includes the valid UTC second pulse signal pps_utc, the valid UT1 second pulse signal pps_ut1 and the valid integer pulse signal ppm_out.

[0044] Further, the shortwave BPM timing receiving method capable of automatically adjusting the second pulse locking period of the present invention, the specific steps of determining the UTC second pulse, the UT1 second pulse, and the PPM full minute pulse in S3-4 include:

[0045] If utc_pps_left_time<=count<=utc_pps_right_time, the current pulse is the UTC second pulse, utc_pps_left_time=36'd65000, utc_pps_right_time=36'd135000;

[0046] If ut1_pps_left_time<=count<=ut1_pps_right_time, the current pulse is the UT1 second pulse, ut1_pps_left_time=36'd900000, ut1_pps_right_time=36'd1100000;

[0047] If ppm_left_time<=count<=ppm_right_time, the current pulse is a PPM integral pulse, ppm_left_time=36'd2700000, ppm_right_time=36'd3300000.

[0048] Furthermore, in the shortwave BPM timing receiving method capable of automatically adjusting the second pulse locking period of the present invention, before outputting the valid UTC second pulse signal pps_utc, a continuity judgment and locking is performed on it to ensure that the output second pulse is reliable and effective, specifically including:

[0049] Start counting count1 from the starting edge of the bpm_pps pulse and wait for the arrival of the next bpm_pps pulse. Use the count value count1 between the two pulses to determine whether the interval between second pulses meets the requirement.

[0050] If the count value between two consecutive bpm_pps second pulses meets the count value range, it is determined that the second pulse is locked successfully once, and the number of consecutive successful locks is t_success times, then the BPM timing second pulse bpm_pps is locked successfully, and the pps_lock signal is output, and the high level is valid; if the count value between two consecutive bpm_pps second pulses does not meet the count value range, it is determined that the second pulse lock fails once. During the second pulse lock period, if the number of lock failures t_fail is greater than N, the number of successful locks is t_success value minus 1;

[0051] After the bpm_pps second pulse is locked, the bpm_pps second pulse and bpm_ppm sub-signal are output. The bpm_pps second pulse signal includes 5 channels, 1 of which is output to the main control together with the bpm_ppm sub-signal pulse, and the other 4 are provided to the timing system. At the same time, the pps_cnt counter is started as a backup for the output second pulse.

[0052] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0053] The present invention proposes a BPM shortwave timing receiving method and device capable of automatically adjusting a second pulse locking period. The device receives the BPM shortwave timing second pulse in a digital manner, and adopts FIR filter design, the second pulse locking period can be automatically adjusted, and the serial port transceiver and other technologies to provide a standard second pulse for a timing system. The technology capable of automatically adjusting the second pulse locking period can solve the problem of shortwave timing second pulse locking time under the condition of unstable wireless BPM shortwave signal, and dynamically shorten the second pulse locking time. The method can be used as an effective supplementary means for satellite timing and wired timing, and has the function of providing user time information and second pulse signals in real time within the coverage area of ​​the shortwave timing system. The device can be embedded in a timing complete machine or expanded separately into an independent BPM shortwave timing receiving device. Through actual engineering research and application, it has been verified that the method has the advantages of accurate second pulse judgment, automatic adjustment of the locking period, strong working stability, easy expansion, etc., and can be applied to wireless communication, electronic reconnaissance, digital instrumentation, navigation, transportation, electricity and other fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The accompanying drawings are used to provide a further understanding of the present invention and are used together with the description to explain the embodiments of the present invention, but do not constitute a limitation of the present invention. In the accompanying drawings:

[0055] Figure 1 The overall structural diagram of the short-wave BPM timing receiving device capable of automatically adjusting the second pulse locking period of the present invention is shown.

[0056] Figure 2 The flowchart of the short-wave BPM timing receiving method capable of automatically adjusting the second pulse locking period of the present invention is shown.

[0057] Figure 3 The FPGA unit signal processing diagram of the short-wave BPM timing receiving device capable of automatically adjusting the second pulse locking period of the present invention is shown.

[0058] Figure 4 The present invention shows a flow chart of automatically adjusting the locking period of pps_utc in the shortwave BPM timing receiving method capable of automatically adjusting the locking period of pulse per second. DETAILED DESCRIPTION

[0059] In order to further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, rather than limiting the claims of the present invention.

[0060] The description in this section is only for typical embodiments, and the present invention is not limited to the scope of the embodiments. The combination of different embodiments, the mutual replacement of some technical features in different embodiments, and the mutual replacement of the same or similar prior art means with some technical features in the embodiments are also within the scope of the description and protection of the present invention.

[0061] According to one aspect of the present invention, a short-wave BPM timing receiving device capable of automatically adjusting the second pulse locking period is characterized in that it includes an FPGA unit, a main control unit, a storage unit, an A / D conversion unit and a constant temperature crystal oscillator, the storage unit is coupled to the FPGA unit, the analog-to-digital conversion unit is coupled to the control signal end of the FPGA unit, the output end of the constant temperature crystal oscillator is coupled to the clock input end of the FPGA unit, the output end of the FPGA unit is coupled to the main control unit and the time system, the input end of the main control unit is coupled to the button and the display screen, the output end of the main control unit is coupled to the time system, and the main control unit, the FPGA unit and the time system are all connected using asynchronous serial ports. Among them:

[0062] The analog-to-digital conversion unit is used to receive the wireless BPM shortwave analog signal and convert it into a BPM digital signal with a width of 8 bits.

[0063] The FPGA unit is used to convert the 8-bit BPM digital signal into a pulse-per-second signal. The FPGA unit includes an analog-to-digital conversion control unit, a FIR filter unit, and a pulse-per-second locking unit.

[0064] An analog-to-digital conversion control unit, used for reading a BPM digital signal with a width of 8 bits in a time sequence, converting it into a 16-bit digital signal in a data input sequence, and writing it into a dual-clock FIFO memory, that is, the 8-bit data read first is in the high order, and the 8-bit data read later is in the low order, and the width of the dual-clock FIFO memory is 16 bits and the depth is 8 bytes;

[0065] The FIR filter unit is used to read the 16-bit digital signal from the dual-clock FIFO memory and filter it to extract the valid data from the BPM shortwave timing signal;

[0066] The pulse-per-second locking unit is used to extract and lock the pulse-per-second of the filtered valid data.

[0067] The main control unit is used to set time information, display time information and system status, and output time information according to the locked second pulse.

[0068] The storage unit is used for program burning and storage of the FPGA unit.

[0069] The constant temperature crystal oscillator is used to provide a standard clock frequency for the FPGA unit.

[0070] According to another aspect of the present invention, a shortwave BPM timing receiving method capable of automatically adjusting a pulse-per-second locking period comprises:

[0071] S1. The analog-to-digital conversion unit receives the BPM shortwave analog signal and converts it into a digital signal with a width of 8 bits.

[0072] S2. The analog-to-digital conversion control unit reads the 8-bit digital signal in time sequence and converts it into a 16-bit digital signal in the order of signal input. The FIR filter unit filters the 16-bit digital signal.

[0073] S3. Use the filtered data to determine the rising and falling edges of the pulse, and lock the second pulse. Output the second pulse and minute signal to the main control unit for time information and status information processing, and provide the second pulse to the timing system.

[0074] S3-1, use n groups of data to determine the rising and falling edges of the pulse. Whenever a new group of data fir_data_out is input, each group of data moves forward by one group of data, that is:

[0075] fir_data_reg_0<=fir_data_out;

[0076] fir_data_reg_1<=fir_data_reg_0;

[0077] fir_data_reg_2<=fir_data_reg_1;

[0078] …

[0079] fir_data_reg_n<=fir_data_reg_n-1;

[0080] S3-2, determine the rising and falling edges of the pulse:

[0081] (1) If the following three conditions are met, it is judged as a pulse rising edge, S3-3:

[0082] Condition 1:

[0083] fir_data_reg_0>fir_data_reg_1>fir_data_reg_2>…>fir_data_reg_n-1;

[0084] Condition 2: fir_data_reg_0, fir_data_reg_1, and fir_data_reg_2 must all be greater than the minimum judgment value sine_lower_value of the pulse rising edge;

[0085] Condition 3: fir_data_reg_0>={fir_data_reg_6[fir_data_width-2:0], 1'b0}; sine_lower_value is 200, fir_data_width is 16;

[0086] (2) If the following three conditions are met, it is judged as a pulse falling edge, S3-4:

[0087] Condition 1:

[0088] fir_data_reg_0 <fir_data_reg_1<…<fir_data_reg_n-1;

[0089] Condition 2: fir_data_reg_0, fir_data_reg_1, and fir_data_reg_2 must all be less than the maximum judgment value sine_high_value in the falling edge of the pulse;

[0090] Condition 3: fir_data_reg_0<{1'b0, fir_data_reg_6[fir_data_width-1:1]}; sine_high_value is 600, fir_data_width is 16;

[0091] S3-3, if it is judged to be a pulse rising edge, the rising edge confirmation signal is valid, and the pulse timer is started to start counting, and the clock is 10MHz;

[0092] S3-4, if it is judged to be a falling edge of the pulse, the falling edge confirmation signal is valid, the clock is 10MHz, and within the valid period of the falling edge confirmation signal, the UTC second pulse, UT1 second pulse, and PPM full minute pulse are judged by the value of the pulse timer, and the pulse valid signal is obtained and output to the main control unit and the timing system. The pulse valid signal includes a valid UTC second pulse signal pps_utc, a valid UT1 second pulse signal pps_ut1, and a valid full minute pulse signal ppm_out. Among them, the specific steps of judging the UTC second pulse, UT1 second pulse, and PPM full minute pulse include:

[0093] If utc_pps_left_time<=count<=utc_pps_right_time, the current pulse is the UTC second pulse, utc_pps_left_time=36'd65000, utc_pps_right_time=36'd135000;

[0094] If ut1_pps_left_time<=count<=ut1_pps_right_time, the current pulse is the UT1 second pulse, ut1_pps_left_time=36'd900000, ut1_pps_right_time=36'd1100000;

[0095] If ppm_left_time<=count<=ppm_right_time, the current pulse is a PPM integral pulse, ppm_left_time=36'd2700000, ppm_right_time=36'd3300000.

[0096] Before outputting a valid UTC second pulse signal pps_utc, a continuity check and lock is performed to ensure that the output second pulse is reliable and effective, including:

[0097] Start counting count1 from the starting edge of the bpm_pps pulse and wait for the arrival of the next bpm_pps pulse. Use the count value count1 between the two pulses to determine whether the interval between second pulses meets the requirement.

[0098] If the count value between two consecutive bpm_pps second pulses meets the count value range, it is determined that the second pulse is locked successfully once, and the number of consecutive successful locks is t_success times, then the BPM timing second pulse bpm_pps is locked successfully, and the pps_lock signal is output, and the high level is valid; if the count value between two consecutive bpm_pps second pulses does not meet the count value range, it is determined that the second pulse lock fails once. During the second pulse lock period, if the number of lock failures t_fail is greater than N, the number of successful locks is t_success value minus 1;

[0099] After the bpm_pps second pulse is locked, the bpm_pps second pulse and bpm_ppm sub-signal are output. The bpm_pps second pulse signal includes 5 channels, 1 of which is output to the main control together with the bpm_ppm sub-signal pulse, and the other 4 are provided to the timing system. At the same time, the pps_cnt counter is started as a backup for the output second pulse.

[0100] S4. The main control unit receives the second pulse and minute signal, sets the year, month, day, hour, minute and second information through buttons, and performs minute and second calibration, as well as second timing, carry, run-second calculations based on the second pulse and minute signal. At the same time, the second pulse lock status is displayed through the LED.

[0101] S5. The main control unit outputs time information, second pulse information and current operating status to the time system according to the locked second pulse and the set time information.

[0102] Example 1

[0103] The present invention proposes a BPM shortwave timing receiving device capable of automatically adjusting the second pulse locking period. The device adopts a programmable device FPGA to realize digital BPM shortwave timing second pulse reception and automatically adjust the second pulse locking period. In the hardware circuit design, an ADS8507 ADC chip is selected to convert the wireless BPM shortwave analog signal into an 8-bit digital signal; an EP3C25Q240 FPGA chip is selected to receive and process the 8-bit BPM digital signal to provide a second pulse signal for the timing system; an STM32F103ZET6 main control chip is selected to set time information and display time information through buttons and provide time information for the timing equipment according to the locked second pulse; an M25P64 Flash chip is used for burning and storing FPGA programs; a constant temperature crystal oscillator is used to provide a 10MHz standard clock frequency for the FPGA. The specific structure is as follows: Figure 1 shown.

[0104] Among them, the programmable device FPGA unit mainly uses the IP core in the development tool Quartus II to design the FIR filter. The FIR filter is used to perform FIR filtering on the 16-bit digital signal converted from the ADS8507 analog-to-digital converter, and then compare and judge the filtered data to extract the bpm_pps second pulse and lock the output; the main control unit is mainly used to set the time through buttons, display the time information and system status through LEDs, and output the time information according to the second pulse locked by the FPGA unit. The BPM timing reception process is as follows Figure 2 shown.

[0105] The FPGA unit includes an analog-to-digital conversion control unit, a FIR filter unit, and a pulse-per-second locking unit. Figure 3As shown. The analog BPM shortwave signal is converted into a digital signal with a width of 8 bits after passing through the ADS8507 chip. The ADC control unit initializes the ADS8507 according to the timing requirements of the ADS8507 chip, reads the 8-bit data according to the timing, and converts it into 16-bit fir_in[15:00] data according to the data input order, that is, the 8-bit data read first is in the high position, and the 8-bit data read later is in the low position. A dual-clock FIFO memory with a width of 16 bits and a depth of 8 bytes is designed using the IP core of the EP3C25Q240 development tool QUARTUS II. The fir_in[15:00] data is written into the FIFO, the write clock is 10MHz, and the clock for reading the FIFO and inputting it into the FIR filter unit is 1MHz. The write enable wrreg and write enable rdreg are used to control the data reading and writing of the FIFO.

[0106] The FIR filter unit filters the data fir_in[15:00] read from the FIFO in the ADC control unit, extracts the valid data fir_data_out[15:00] in the BPM shortwave timing signal, and controls the data to be effectively sent to the pulse-per-second lock unit for pulse-per-second extraction and locking through the fir_data_valid enable signal. This unit mainly uses the IP core of the EP3C25Q240 development tool QUARTUS II to design a bandpass window filter. The window design type is Hanning window, the window type is Hanning window, the sampling frequency Fs=8000Hz, and the starting frequencies are F C1 =999Hz, F C2 =1001Hz, filter order is 64, clock frequency is 10MHz.

[0107] The pulse-per-second lock unit is the main innovative design part of the present invention. The unit extracts pulse-per-second from the received fir_data_out[15:00] data according to the value of each input filtered data. In this design, the rising and falling edges of the pulse are judged according to 8 groups of data, that is, 8 groups of fir_data_out[15:00] are used for judgment. Whenever a new group of fir_data_out[15:00] data is input, the 8 groups of data are moved forward by one group of data, as shown below:

[0108] fir_data_reg_0<=fir_data_out;

[0109] fir_data_reg_1<=fir_data_reg_0;

[0110] fir_data_reg_2<=fir_data_reg_1;

[0111] fir_data_reg_3<=fir_data_reg_2;

[0112] fir_data_reg_4<=fir_data_reg_3;

[0113] fir_data_reg_5<=fir_data_reg_4;

[0114] fir_data_reg_6<=fir_data_reg_5;

[0115] fir_data_reg_7<=fir_data_reg_6;

[0116] fir_data_reg_8<=fir_data_reg_7.

[0117] In the process of judging the rising edge of the pulse, condition 1 must be met:

[0118] fir_data_reg_0>fir_data_reg_1>fir_data_reg_2>fir_data_reg_3>fir_data_reg_4>fir_data_reg_5>fir_data_reg_6>fir_data_reg_7.

[0119] To further ensure the correctness of the pulse rising edge data, conditions 2 and 3 are added.

[0120] Condition 2: fir_data_reg_0, fir_data_reg_1, and fir_data_reg_2 must all be greater than the minimum judgment value sine_lower_value of the pulse rising edge.

[0121] Condition 3: fir_data_reg_0>={fir_data_reg_6[fir_data_width-2:0], 1'b0}; sine_lower_value is 200, and fir_data_width is 16.

[0122] When the three conditions of the judgment pulse are met, the rising edge confirmation signal sin_check is valid, and the pulse timer count is started to count, and the clock is 10MHz.

[0123] Similarly, in the process of judging the falling edge of the pulse, the following conditions are satisfied:

[0124] Condition 1:

[0125] fir_data_reg_0 <fir_data_reg_1<fir_data_reg_2<fir_data_reg_3<fir_data_reg_4<fir_data_reg_5<fir_data_reg_6<fir_data_reg_7。

[0126] Condition 2: fir_data_reg_0, fir_data_reg_1, and fir_data_reg_2 must all be smaller than the maximum judgment value sine_high_value on the falling edge of the pulse.

[0127] Condition 3: fir_data_reg_0<{1'b0, fir_data_reg_6[fir_data_width-1:1]}; sine_high_value is 600 and fir_data_width is 16.

[0128] When the three conditions of the judgment pulse are met, the falling edge confirmation signal sin_uncheck is valid and the clock is 10MHz.

[0129] During the effective period of the falling edge confirmation signal sin_uncheck, the pulse representative signal UTC second pulse, UT1 second pulse, and PPM full minute are judged by the value of the pulse timer count:

[0130] If utc_pps_left_time<=count<=utc_pps_right_time, the current pulse is the UTC second pulse, utc_pps_left_time=36'd65000, utc_pps_right_time=36'd135000;

[0131] If ut1_pps_left_time<=count<=ut1_pps_right_time, the current pulse is the UT1 second pulse, ut1_pps_left_time=36'd900000, ut1_pps_right_time=36'd1100000;

[0132] If ppm_left_time<=count<=ppm_right_time, the current pulse is a PPM integral pulse, ppm_left_time=36'd2700000, ppm_right_time=36'd3300000.

[0133] According to the judged pulse signal type, the corresponding pulse valid signals pps_utc, pps_ut1 and ppm_out are output respectively. In the present invention, the main control is provided with the parsed UTC second pulse pps_utc and integer pulse ppm_out. Due to the characteristics of the BPM shortwave timing signal, the quality of the wireless signal may be unstable, resulting in the inability to judge the processing pulse or a judgment error. It is necessary to perform continuity judgment and lock the UTC second pulse pps_utc before outputting it to ensure that the output second pulse is reliable and effective.

[0134] like Figure 4 The figure shows the process of automatically adjusting the locking period of pps_utc.

[0135] Start counting count1 from the starting edge of the bpm_pps pulse, and wait for the arrival of the next bpm_pps pulse. Use the count value count1 between the two pulses to determine whether the interval between the second pulses meets the requirements. If the count value between two consecutive bpm_pps second pulses meets the count value range, it is determined that the second pulse is locked successfully once. If the number of consecutive successful locks is t_sucess times, it is determined that the BPM timing second pulse bpm_pps is locked successfully, and the pps_lock signal is output, which is valid at a high level. If the count value between two consecutive bpm_pps second pulses does not meet the count value range, it is determined that the second pulse lock fails once. During the second pulse lock period, if the number of lock failures t_fail is greater than N, the number of successful locks is t_success minus 1, so as to adjust the number of lock cycles and increase the success rate of second pulse lock.

[0136] In the specific implementation, considering the possible errors in the actual timing transmission and processing, the range of the count value is the whole second plus or minus 5ms, per_second_left = 36'd9950000, per_second_right = 36'd10050000, that is, the count value count1 between two bpm second pulses meets the requirements of 9950000 to 10050000, and the number of successful locks t_success is 6, that is, the count value between two consecutive bpm_pps meets the count value requirements for 6 consecutive times, then the bpm_pps second pulse is locked successfully, and the pps_lock valid signal is output, and the high level is valid. In the process of second pulse locking, if the number of lock failures t_fail is greater than 7, the number of successful locks is t_success, which is reduced to 5. By analogy, the minimum value of t_success is 3, that is, the count values ​​of three consecutive bpm_pps need to meet the requirements of the count value range.

[0137] After completing the bpm_pps second pulse locking, the bpm_pps second pulse and bpm_ppm sub-signal are output. There are 5 bpm_pps second pulse signals, 1 of which is output to the main control together with the bpm_ppm sub-signal pulse, and the other 4 are provided to the timing system. The pulse width of the bpm_pps second pulse and bpm_ppm sub-signal can be appropriately adjusted according to the requirements of the timing system. In this design, both are 133us.

[0138] At the same time, the pps_cnt counter is started as a backup for the output second pulse. When the bpm_pps second pulse is locked and the pps_lock valid signal is high, if the BPM timing signal is unstable and bpm_pps is lost, the second pulse output backup can be performed according to the count value of pps_cnt to ensure the continuity of the timing output.

[0139] After receiving the second pulse bpm_pps and minute pulse bpm_ppm, the main control unit determines that the BPM timing receiving bpm_pps has been locked, and displays the system BPM second pulse lock status on the LED; then, the year, month, day, hour, minute, and second information are set as the starting information of the system output time information through the buttons, and then the minute and second time calibration and second timing, carry, and leap second calculations are performed according to the bpm_pps and minute pulse bpm_ppm. The asynchronous serial port outputs the time information to the timing system and displays the time on the local LED in coordination with the second pulse bpm_pps. Taking into account the asynchronous serial port rate and the time information protocol format, the time information is sent 50ms after the bpm_pps start pulse.

[0140] At the same time, the main control unit can query and modify parameters such as sine_lower_value, sine_high_value, utc_pps_left_time, utc_pps_right_time, ut1_pps_left_time, ut1_pps_right_time, ppm_left_time, ppm_right_time, per_second_left, per_second_right, t_success, and t_fail in the programmable device FPGA unit through the asynchronous serial port by pressing buttons. By modifying the number of locking cycles t_success or other judgment values, the timing reception accuracy and locking time can be adjusted to meet the requirements for locking accuracy and locking time in different environments or usage scenarios.

[0141] The description and application of the present invention here are illustrative, and it is not intended to limit the scope of the present invention to the above-mentioned embodiments. The effects or advantages involved in the specification may not be reflected in the actual experimental examples due to the uncertainty of specific condition parameters or other factors, and the effects or advantages are not used to limit the scope of the invention. The deformation and change of the embodiments disclosed here are possible, and the replacement of the embodiments and the various equivalent parts are well known to those of ordinary skill in the art. It should be clear to those skilled in the art that the present invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials and parts without departing from the spirit or essential features of the present invention. Other deformations and changes can be made to the embodiments disclosed here without departing from the scope and spirit of the present invention.

Claims

1. A shortwave BPM timing receiver capable of automatically adjusting the pulse-per-second locking period, characterized in that: It includes an FPGA unit, a main control unit, a storage unit, an A / D conversion unit and a constant temperature crystal oscillator, the storage unit is coupled to the FPGA unit, the analog-to-digital conversion unit is coupled to the control signal end of the FPGA unit, the output end of the constant temperature crystal oscillator is coupled to the clock input end of the FPGA unit, the output end of the FPGA unit is coupled to the main control unit and the time system, the input end of the main control unit is coupled to the button and the display screen, and the output end of the main control unit is coupled to the time system; wherein: The analog-to-digital conversion unit is used to receive the wireless BPM shortwave analog signal and convert it into a BPM digital signal with a width of 8 bits; FPGA unit is used to convert the 8-bit BPM digital signal into a pulse-per-second signal; the FPGA unit includes an analog-to-digital conversion control unit, a FIR filter unit and a pulse-per-second locking unit. An analog-to-digital conversion control unit, used for reading a BPM digital signal with a width of 8 bits in a time sequence, converting it into a 16-bit digital signal in a data input sequence, and writing it into a dual-clock FIFO memory, that is, the 8-bit data read first is in the high order, and the 8-bit data read later is in the low order, and the width of the dual-clock FIFO memory is 16 bits and the depth is 8 bytes; The FIR filter unit is used to read the 16-bit digital signal from the dual-clock FIFO memory and filter it to extract the valid data from the BPM shortwave timing signal; A pulse-per-second locking unit is used to extract and lock the pulse-per-second of the filtered valid data; A main control unit, used to set time information, display time information and system status, and output time information according to the locked second pulse; Storage unit, used for program burning and storage of FPGA unit; The constant temperature crystal oscillator is used to provide a standard clock frequency for the FPGA unit.

2. The shortwave BPM timing receiving device capable of automatically adjusting the second pulse locking period according to claim 1 is characterized in that: The main control unit, FPGA unit and timing system are all connected via asynchronous serial ports.

3. A receiving method of a shortwave BPM timing receiving device capable of automatically adjusting the second pulse locking period according to any one of claims 1-2, characterized in that: include: S1, the analog-to-digital conversion unit receives the BPM shortwave analog signal and converts it into a digital signal with a width of 8 bits; S2, the analog-to-digital conversion control unit reads the 8-bit digital signal in time sequence and converts it into a 16-bit digital signal in the order of signal input, and the FIR filter unit filters the 16-bit digital signal; S3, using the filtered data to determine the rising and falling edges of the pulse, and to lock the second pulse, output the second pulse and minute signal to the main control unit for time information and status information processing, and provide the second pulse to the time system; S4, the main control unit receives the second pulse and minute signal, sets the year, month, day, hour, minute and second information through the buttons, and performs minute and second calibration, as well as second timing, carry and run-second calculation according to the second pulse and minute signal, and displays the second pulse lock status through the LED; S5. The main control unit outputs time information, second pulse information and current operating status to the time system according to the locked second pulse and the set time information.

4. The shortwave BPM timing receiving method capable of automatically adjusting the second pulse locking period according to claim 3 is characterized in that: The specific steps of S3 include: S3-1, use n groups of data to determine the rising and falling edges of the pulse. Whenever a new group of data fir_data_out is input, each group of data moves forward by one group of data, that is: fir_data_reg_0<=fir_data_out; fir_data_reg_1<=fir_data_reg_0; fir_data_reg_2<=fir_data_reg_1; … fir_data_reg_n<=fir_data_reg_n-1; S3-2, determine the rising and falling edges of the pulse: (1) If the following three conditions are met, it is judged as a pulse rising edge, S3-3: Condition 1: fir_data_reg_0>fir_data_reg_1>fir_data_reg_2>…>fir_data_reg_n-1; Condition 2: fir_data_reg_0, fir_data_reg_1, and fir_data_reg_2 must all be greater than the minimum judgment value sine_lower_value of the pulse rising edge; Condition 3: fir_data_reg_0>={fir_data_reg_6[fir_data_width-2:0], 1'b0}; sine_lower_value is 200, fir_data_width is 16; (2) If the following three conditions are met, it is judged as a pulse falling edge, S3-4: Condition 1: fir_data_reg_0 <fir_data_reg_1<…<fir_data_reg_n-1; Condition 2: fir_data_reg_0, fir_data_reg_1, and fir_data_reg_2 must all be less than the maximum judgment value sine_high_value in the falling edge of the pulse; Condition 3: fir_data_reg_0<{1'b0, fir_data_reg_6[fir_data_width-1:1]}; sine_high_value is 600, fir_data_width is 16; S3-3, if it is judged to be a pulse rising edge, the rising edge confirmation signal is valid, and the pulse timer is started to start counting, and the clock is 10MHz; S3-4. If it is judged to be a pulse falling edge, the falling edge confirmation signal is valid, the clock is 10MHz, and within the valid period of the falling edge confirmation signal, the UTC second pulse, UT1 second pulse, and PPM integer pulse are judged by the value of the pulse timer to obtain the pulse valid signal and output it to the main control unit and the timing system. The pulse valid signal includes the valid UTC second pulse signal pps_utc, the valid UT1 second pulse signal pps_ut1 and the valid integer pulse signal ppm_out.

5. The shortwave BPM timing receiving method capable of automatically adjusting the pulse-per-second locking period according to claim 4 is characterized in that: The specific steps of determining the UTC second pulse, UT1 second pulse, and PPM full minute pulse in S3-4 include: If utc_pps_left_time<=count<=utc_pps_right_time, the current pulse is the UTC second pulse, utc_pps_left_time=36'd65000, utc_pps_right_time=36'd135000; If ut1_pps_left_time<=count<=ut1_pps_right_time, the current pulse is the UT1 second pulse, ut1_pps_left_time=36'd900000, ut1_pps_right_time=36'd1100000; If ppm_left_time<=count<=ppm_right_time, the current pulse is a PPM integral pulse, ppm_left_time=36'd2700000, ppm_right_time=36'd3300000.

6. The shortwave BPM timing receiving method capable of automatically adjusting the pulse-per-second locking period according to claim 4, characterized in that: In S3-4, before outputting the valid UTC second pulse signal pps_utc, a continuity check and lock is performed on it to ensure that the output second pulse is reliable and effective, specifically including: Start counting count1 from the starting edge of the bpm_pps pulse and wait for the arrival of the next bpm_pps pulse. Use the count value count1 between the two pulses to determine whether the interval between second pulses meets the requirement. If the count value between two consecutive bpm_pps second pulses meets the count value range, it is determined that the second pulse is locked successfully once, and the number of consecutive successful locks is t_success times, then the BPM timing second pulse bpm_pps is locked successfully, and the pps_lock signal is output, and the high level is valid; if the count value between two consecutive bpm_pps second pulses does not meet the count value range, it is determined that the second pulse lock fails once. During the second pulse lock period, if the number of lock failures t_fail is greater than N, the number of successful locks is t_success value minus 1; After the bpm_pps second pulse is locked, the bpm_pps second pulse and bpm_ppm sub-signal are output. The bpm_pps second pulse signal includes 5 channels, 1 of which is output to the main control together with the bpm_ppm sub-signal pulse, and the other 4 are provided to the timing system. At the same time, the pps_cnt counter is started as a backup for the output second pulse.

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