PCIe signal test fixture for U.2 connector

Abstract

The present invention relates to the field of signal testing technology, and discloses a PCIe signal test fixture of a U.2 connector, comprising a fixture board, a U.2 interface and a plurality of connectors. The U.2 interface is arranged at one end of the fixture board, and is used to be connected to the U.2 connector interface of a board to be tested. A plurality of connectors are distributed on the fixture board at intervals, and the connector is used to be connected to an oscilloscope, and the signals on the board to be tested can be led out to a plurality of connectors via the U.2 interface. The PCIe signal test fixture can realize PCIe signal testing of the U.2 connector interface, and solves the problem that the existing standard test fixture cannot test the high-speed PCIe signal of the U.2 connector. By leading the PCIe signal to be tested to a plurality of connectors through the U.2 interface, it can be ensured that the oscilloscope is in good contact with the test point, so that the measured signal data can accurately and truly reflect the signal quality at the U.2 connector interface, and ensure the signal integrity of the server system.

Description

Technical Field

[0001] The present invention relates to the technical field of signal testing, and in particular to a PCIe signal testing fixture for a U.2 connector. Background Art

[0002] The U.2 interface, also known as the SFF-8639 interface, is an interface specification launched by the SSD Form Factor Work Group. The U.2 interface has many advantages, such as strong compatibility, low cost, and security. It is compatible with single-port SATA, dual-port SATA Express, dual-port SAS, MultiLink SAS, and up to four-port PCIe devices, and is widely used. The female head of the U.2 interface is welded on the server motherboard or high-speed backplane, and the male head is welded on the interface of the hard disk.

[0003] In the prior art, during the signal integrity test of the server system, the PCIe signal is usually tested using a standard PCIe test fixture. However, for the high-speed PCIe signal (such as PCIe5.0 signal) of the U.2 connector on the motherboard or hard disk backplane, the space at the U.2 interface is limited, and there are no suitable jacks around the U.2 connector for probes and other tools to insert for point testing, resulting in the inability of the existing standard PCIe test fixture to test the high-speed PCIe signal of the U.2 connector. If vias or pads are designed at the outlet of the U.2 connector, the signal quality is easily affected, and the test accuracy and precision cannot be guaranteed, making it difficult to test the high-speed PCIe signal of the U.2 connector.

[0004] Therefore, there is an urgent need for a PCIe signal test fixture for a U.2 connector to solve the above problems. Summary of the invention

[0005] Based on the above problems, the purpose of the present invention is to provide a PCIe signal test fixture for a U.2 connector, which can smoothly test the high-speed PCIe signal at the U.2 connector and ensure the signal test quality.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] Provided is a PCIe signal test fixture for a U.2 connector, including:

[0008] jig board;

[0009] A U.2 interface, the U.2 interface is provided at one end of the fixture board, and the U.2 interface is configured to be connected to a U.2 connector interface of a board to be tested;

[0010] Multiple connectors are spaced apart on the fixture board, and the multiple connectors are electrically connected to the U.2 interface. The connectors are configured to be connected to an oscilloscope, and the PCIe signal to be tested on the board to be tested can be led out to the multiple connectors via the U.2 interface.

[0011] As a preferred solution of the PCIe signal test fixture of the U.2 connector of the present invention, the plurality of connectors include:

[0012] A plurality of first SMP connectors, the plurality of first SMP connectors are distributed in an array on the fixture board, and the first SMP connectors are used to lead out high-speed PCIe signals on the board to be tested;

[0013] The second SMP connector is used to lead out a clock signal on the board to be tested.

[0014] The arrangement of multiple first SMP connectors and second SMP connectors realizes a detachable connection between the fixture board and the oscilloscope, so as to acquire high-speed PCIe signals and clock signals at the U.2 connector interface of the board under test through the oscilloscope to complete signal testing. At the same time, the SMP connector is more convenient to install and disassemble, which can improve the test efficiency. The SMP connector is relatively small in size and occupies less space on the fixture board, which is conducive to reducing the size of the fixture board.

[0015] As a preferred solution of the PCIe signal test fixture of the U.2 connector of the present invention, the U.2 interface is provided with a first row of pins and a second row of pins distributed at intervals, the first row of pins is close to the board to be tested, the first row of pins includes first pins corresponding to a plurality of the first SMP connectors one by one, each of the first pins is provided with a first via, and the first SMP connector is electrically connected to the U.2 interface through the corresponding first via. By providing the first via on the plurality of first pins in the first row of pins, the problem that the space on the fixture board is limited and holes cannot be opened can be solved, and the PCIe signal at the U.2 connector interface of the board to be tested can be led to the first SMP connector position on the fixture board via the first row of pins of the U.2 interface, solving the problem that the existing standard test fixture cannot test the high-speed PCIe signal at the U.2 connector interface.

[0016] As a preferred solution of the PCIe signal test fixture of the U.2 connector of the present invention, the PCIe signal test fixture of the U.2 connector also includes a plurality of first transmission lines, the fixture board includes a plurality of stacked layers stacked in sequence, the plurality of first transmission lines are all located between two of the stacked layers inside the fixture board, one end of the first transmission line is connected to the corresponding first pin through the first via, and the other end is connected to the corresponding first SMP connector. That is, the above-mentioned first via is punched into the inner layer of the fixture board so that the first transmission line is passed through two stacked layers inside the fixture board. This design method can avoid interference between the first transmission line and the second row of pins, and can ensure that the plurality of first pins of the first row of pins are electrically connected to the plurality of first SMP connectors, so as to realize the PCIe signal at the U.2 connector interface of the board to be tested being led out to the first SMP connector.

[0017] As a preferred solution of the PCIe signal test fixture of the U.2 connector of the present invention, the plurality of the first transmission lines include:

[0018] n groups of Tx differential lines, the lengths of the n groups of Tx differential lines are equal, each group of Tx differential lines includes a first input line and a second input line, the length difference between the first input line and the second input line is d1, d1<1 mil;

[0019] There are n groups of Rx differential lines, the lengths of the n groups of Rx differential lines are equal, each group of Rx differential lines includes a first output line and a second output line, the length difference between the first output line and the second output line is d2, and d2<1 mil.

[0020] By making n groups of Tx differential lines equal in length and n groups of Rx differential lines equal in length, it is possible to ensure that the transmission line lengths from the first pins of the first row of pins to the first SMP connectors corresponding thereto are equal, thereby ensuring that the transmission link losses of n pairs of Tx differential signals are consistent, and the transmission link losses of n pairs of Rx differential signals are consistent, thereby ensuring the accuracy of the signal test results. By designing the length difference between the first input line and the second input line to be less than 1 mil, and the length difference between the first output line and the second output line to be less than 1 mil, it is possible to further ensure that the transmission losses of each pair of Tx differential signals and Rx differential signals are consistent, thereby improving the accuracy of signal testing.

[0021] As a preferred solution of the PCIe signal test fixture of the U.2 connector of the present invention, the fixture board includes eight stacked layers stacked in sequence, and the plurality of the first transmission lines are located on the sixth stack of the fixture board, and the fifth and seventh stacks of the fixture board are both GND planes. Designing the fifth and seventh stacks as GND planes as reference planes for the sixth stack can provide a shorter return path for the signal on the first transmission line, thereby reducing the impact of impedance discontinuity on the transmission signal.

[0022] As a preferred solution of the PCIe signal test fixture of the U.2 connector of the present invention, the PCIe signal test fixture of the U.2 connector also includes a second transmission line, the second transmission line is located at the bottom layer of the fixture board, the first row of pins also includes a second pin corresponding to the second SMP connector, the second pin is provided with a second via, one end of the second transmission line is electrically connected to the U.2 interface through the second via, and the other end is connected to the second SMP connector. The cooperation of the second transmission line and the second via can lead the clock signal at the U.2 connector interface of the board to be tested to the second SMP connector on the fixture board, thereby providing a reference for the test of the PCIe signal and ensuring the integrity of the server system signal test.

[0023] As a preferred solution of the PCIe signal test fixture of the U.2 connector of the present invention, the first via and the second via are both processed by the POFV process, the Stub is removed by the back drilling process at the first via on the fixture board, and a GND return hole spaced apart from the first via is provided at the first via on the fixture board. The redundant Stubs of the first via are removed by the back drilling process, which can ensure the continuity of the first via, reduce the residual piles, optimize the impedance, and improve the transmission quality of the high-speed differential signal. Providing a GND return hole near the first via can reduce electric field radiation and suppress signal crosstalk. At the same time, the GND return hole can also provide a minimum inductance return path for the first via, thereby improving the signal transmission quality.

[0024] As a preferred solution of the PCIe signal test fixture of the U.2 connector of the present invention, the PCIe signal test fixture of the U.2 connector also includes a first calibration circuit and a second calibration circuit arranged on the fixture board, the length of the second calibration circuit is twice the length of the first calibration circuit, and both ends of the first calibration circuit and both ends of the second calibration circuit are connected to a third SMP connector, and the third SMP connector is configured to be connected to a vector network analyzer (VNA). By setting the first calibration circuit and the second calibration circuit on the fixture board, the link loss data of the transmission line on the current fixture board can be obtained to obtain the link loss data on the first transmission line, so that the PCIe signal to be tested at the U.2 connector interface of the board to be tested can be tested more accurately, thereby improving the accuracy of signal testing.

[0025] As a preferred solution of the PCIe signal test fixture of the U.2 connector of the present invention, the fixture board is made of PCB high-speed board. Using PCB high-speed board to make the fixture board can reduce the overall attenuation of the test fixture and meet the PCIe5.0 design requirements.

[0026] The beneficial effects of the present invention are:

[0027] The PCIe signal test fixture of the U.2 connector provided by the present invention, when testing the high-speed PCIe signal (such as PCIe5.0 signal) of the U.2 connector on the board to be tested, the fixture board is plugged into the U.2 connector interface on the board to be tested through the U.2 interface. At this time, the PCIe signal on the board to be tested can be led to multiple connectors via the U.2 interface on the fixture board, and the waveform data of the PCIe signal to be tested can be obtained by connecting the oscilloscope to the corresponding connector. In other words, the PCIe signal test fixture can realize the PCIe signal test of U.2 connector interfaces of different specifications, solving the problem that the existing PCIe Association standard test fixture cannot test the high-speed PCIe signal of the U.2 connector. In addition, the PCIe signal to be tested is led out to multiple connectors on the fixture board through the U.2 interface, which can ensure that the oscilloscope is in good contact with the test point, so that the measured signal data can accurately and truly reflect the signal quality at the U.2 connector of the board to be tested. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the contents of the embodiments of the present invention and these drawings without paying any creative work.

[0029] Figure 1It is a schematic diagram of the connection between the PCIe signal test fixture of the U.2 connector and the board to be tested provided by a specific embodiment of the present invention;

[0030] Figure 2 It is a plan view of a PCIe signal test fixture for a U.2 connector provided in a specific embodiment of the present invention;

[0031] Figure 3 It is a three-dimensional structural schematic diagram (front view) of a PCIe signal test fixture for a U.2 connector provided in a specific embodiment of the present invention;

[0032] Figure 4 3D schematic diagram of the PCIe signal test fixture of the U.2 connector provided in a specific embodiment of the present invention (back side);

[0033] Figure 5 is a first partial schematic diagram of a U.2 interface and a fixture board provided in a specific embodiment of the present invention;

[0034] Figure 6 It is a second partial schematic diagram of the U.2 interface and the fixture board provided by the specific embodiment of the present invention (the front side after hiding the medium);

[0035] Figure 7 yes Figure 6 A partial enlarged view of point B in the middle;

[0036] Figure 8 It is a third partial schematic diagram of the U.2 interface and the fixture board provided in a specific embodiment of the present invention (the back side after hiding the medium);

[0037] Fig. 9 yes Figure 8 A partial enlarged view of point C in the middle;

[0038] Fig.10 is a fourth partial schematic diagram of a U.2 interface and a fixture board provided in a specific embodiment of the present invention (the seventh stack is hidden);

[0039] Fig.11 is a fifth partial schematic diagram of a U.2 interface and a fixture board provided in a specific embodiment of the present invention (the seventh stack is hidden);

[0040] Fig.12 yes Figure 4 A partial enlarged view of the middle A;

[0041] Fig.13 It is a partial top view of a PCIe signal test fixture for a U.2 connector provided in a specific embodiment of the present invention.

[0042] In the figure:

[0043] 1- jig board; 2- U.2 interface; 3- first SMP connector; 4- second SMP connector; 5- first transmission line; 6- second transmission line; 7- first calibration line; 8- second calibration line; 9- third SMP connector;

[0044] 11- fifth stack; 12- seventh stack;

[0045] 21-first row of pins; 22-second row of pins;

[0046] 211-first pin; 212-second via hole; 213-GND return hole;

[0047] 2111-first via hole;

[0048] 100-test board; 101-U.2 connector interface. DETAILED DESCRIPTION

[0049] In order to make the technical problems solved by the present invention, the technical solutions adopted and the technical effects achieved clearer, the technical solutions of the embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0050] In the description of the present invention, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance. Among them, the terms "first position" and "second position" are two different positions.

[0051] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0052] like Figures 1 to 4As shown, this embodiment provides a PCIe signal test fixture for a U.2 connector, which is used to test the PCIe signal at the U.2 connector interface 101 on the board to be tested 100, and can detect the signal integrity of the server system. The PCIe signal test fixture for the U.2 connector includes a fixture board 1, a U.2 interface 2, and multiple connectors.

[0053] Among them, see Figure 1 , Figure 2 and Figure 3 , the U.2 interface 2 is provided at one end of the fixture board 1, and the U.2 interface 2 is configured to be connected to the U.2 connector interface 101 of the board to be tested 100. Multiple connectors are spaced apart on the fixture board 1, and the multiple connectors are electrically connected to the U.2 interface 2, and the connector is configured to be connected to an oscilloscope, and the PCIe signal to be tested on the board to be tested 100 can be led out to multiple connectors via the U.2 interface 2.

[0054] The PCIe signal test fixture of the U.2 connector provided in this embodiment, when testing the high-speed PCIe signal (such as PCIe5.0 signal) of the U.2 connector on the board 100 to be tested, plug the fixture board 1 with the U.2 connector interface 101 on the board 100 to be tested through the U.2 interface 2. At this time, the PCIe signal on the motherboard or backplane to be tested can be led to multiple connectors via the U.2 interface 2 on the fixture board 1, and the waveform data of the PCIe signal to be tested can be obtained by connecting the oscilloscope to the corresponding connector. In other words, the PCIe signal test fixture can realize the PCIe signal test of U.2 connector interfaces 101 of different specifications, which solves the problem that the existing PCIe Association standard test fixture cannot test the high-speed PCIe signal of the U.2 connector. Furthermore, by leading the PCIe signal to be tested to multiple connectors on the fixture board 1 through the U.2 interface 2, it can be ensured that the oscilloscope is in good contact with the test point, so that the measured signal data can accurately and truly reflect the signal quality at the U.2 connector interface 101 of the board to be tested 100.

[0055] In this embodiment, the board to be tested 100 may be a CPU mainboard or a hard disk backplane.

[0056] Further, see Figure 1 The fixture board 1 has a power-on indicator light. When the fixture board 1 is connected to the board to be tested 100, the power-on indicator light is on, indicating that the connection is good.

[0057] Optionally, see Figure 2 , Figure 3 and Figure 4, the multiple connectors include multiple first SMP connectors 3 and second SMP connectors 4, the multiple first SMP connectors 3 are distributed in an array on the fixture board 1, the first SMP connectors 3 are used to lead out the high-speed PCIe signal on the board to be tested 100, and the second SMP connectors 4 are used to lead out the clock signal on the board to be tested 100. In this embodiment, taking the test of PCIe5.0 signal as an example, the high-speed PCIe signal led out is the PCIe5.0 signal, and the clock signal led out is the 100M REFPCIe CLK signal. During the test, the clock signal and each PCIe5.0 data signal to be tested are connected to the oscilloscope together.

[0058] The present embodiment uses an SMP connector, which is more conducive to installing and disassembling the connection between the oscilloscope and the fixture board 1 during the test process, thereby improving the test efficiency. In addition, the SMP connector is relatively small in size and occupies less space on the fixture board 1, which is conducive to reducing the size of the fixture board 1.

[0059] Of course, in other embodiments, the connector may also be an SMA connector.

[0060] Preferably, the U.2 interface 2 on the fixture board 1 is a U.2X4 gold finger, which can be plugged with the corresponding U.2 connector interface 101 on the board to be tested 100. According to the test specification recommended by PCI-SIG, when the test bandwidth is X4, Lane0 and Lane3 need to be brought out. Therefore, Figure 2 As shown, on the fixture board 1, the four pairs of differential signals of Lane0, Lane1, Lane2 and Lane3 are all led out to the sixteen first SMP connectors 3 of the fixture board 1, and each pair of differential signals includes two pairs of first SMP connectors 3 of Tx and Rx. Figure 3 and Figure 4 In the figure, there are eight first SMP connectors 3 on the front side of the fixture board 1, and eight first SMP connectors 3 on the back side of the fixture board 1, which are first SMP connectors 3 for four pairs of Tx differential signals and first SMP connectors 3 for four pairs of Rx differential signals.

[0061] The PCIe signal test fixture of the U.2 connector provided in this embodiment can meet a variety of test requirements, such as PCIe transmission signal compatibility test of the board under test 100, PCIe signal bit error rate BERT test of the board under test 100, PCIe signal Margin test of the board under test 100, etc. In addition, according to the PCIe specification, using a signal generator or a second SMP connector 4 connected to the PCIe Rx end can achieve switching between Gen1, Gen2, Gen3, Gen4 and Gen5 rates, and can fully cover the signal quality at the U.2 connector of the board under test 100, thereby effectively ensuring the signal integrity of the computing hardware system motherboard or hard disk backplane.

[0062] Optionally, see Figure 5 , Figure 6 and Figure 7 The U.2 interface 2 is provided with a first row of pins 21 and a second row of pins 22 that are spaced apart from each other. The first row of pins 21 is close to the board to be tested 100. The first row of pins 21 includes first pins 211 that correspond to a plurality of first SMP connectors 3 one by one. Each first pin 211 is provided with a first via 2111. The first SMP connector 3 is electrically connected to the U.2 interface 2 through the corresponding first via 2111. That is, the first via 2111 is provided on the first pin 211 of the U.2 interface 2.

[0063] like Figure 6 and Figure 7 As shown, the first row of pins 21 in the U.2 interface 2 are PCIe signal pins, which are located near the edge of the fixture board 1 (right side). Since the spacing between the first row of pins 21 and the second row of pins 22 is very small, it is impossible to open a hole between the two rows of pins on the fixture board 1. Therefore, by setting the first vias 2111 on the multiple first pins 211 of the first row of pins 21, it is possible to solve the problem that the space on the fixture board 1 is limited and the holes cannot be opened, and the PCIe signal at the U.2 connector interface 101 of the board to be tested 100 can be led to the first SMP connector 3 position (left side) on the fixture board 1 through the first row of pins 21 of the U.2 interface 2, which solves the problem that the existing standard test fixture cannot test the high-speed PCIe signal at the U.2 connector interface 101 of the board to be tested 100.

[0064] Optionally, see Figure 8 , Fig. 9 and Fig.10 , the PCIe signal test fixture of the U.2 connector also includes a plurality of first transmission lines 5, the fixture board 1 includes a plurality of stacked layers stacked in sequence, the plurality of first transmission lines 5 are all located between two stacked layers inside the fixture board 1, one end of the first transmission line 5 is connected to the corresponding first pin 211 through the first via 2111, and the other end is connected to the corresponding first SMP connector 3. That is, the first via 2111 is punched into the inner layer of the fixture board 1 so that the first transmission line 5 is passed between two stacked layers inside the fixture board 1. This design method can avoid the interference between the first transmission line 5 and the second row of pins 22, and can ensure that the plurality of first pins 211 of the first row of pins 21 are electrically connected to the plurality of first SMP connectors 3, so as to realize the PCIe signal at the U.2 connector interface 101 of the board to be tested 100 is led out to the first SMP connector 3.

[0065] Furthermore, the plurality of stacked layers of the fixture plate 1 are hollowed out at the positions of the first via holes 2111 ( Figure 7 and Fig. 9An elliptical blank area around the first via hole 2111 is formed to form an Antipad, and a simulation tool is used to simulate the size of the Antipad at the hollowed-out position to determine the optimal hollowing size to improve the continuity of the first via hole 2111 and ensure the signal transmission quality.

[0066] Optionally, the plurality of first transmission lines 5 include n groups of Tx differential lines and n groups of Rx differential lines, the lengths of the n groups of Tx differential lines are equal, each group of Tx differential lines includes a first input line and a second input line, the length difference between the first input line and the second input line is d1, d1 < 1mil. The lengths of the n groups of Rx differential lines are equal, each group of Rx differential lines includes a first output line and a second output line, the length difference between the first output line and the second output line is d2, d2 < 1mil. In this embodiment, taking the U.2 interface 2 as a U.2X4 gold finger as an example, the plurality of first transmission lines 5 include four groups of Tx differential lines and four groups of Rx differential lines, the four groups of Tx differential lines are used to transmit Tx differential signals, the four groups of Rx differential lines are used to transmit Rx differential signals, the first input line and the second input line of each group of Tx differential lines are the P line and the N line of the Tx differential line, and the first output line and the second output line of each group of Rx differential lines are the P line and the N line of the Rx differential line. By making the four groups of Tx differential lines equal in length and the four groups of Rx differential lines equal in length, it is possible to ensure that the transmission line lengths from the first pins 211 of the first row of pins 21 to the corresponding first SMP connector 3 are equal, thereby ensuring that the transmission link losses of the four pairs of Tx differential signals are consistent, and the transmission link losses of the four pairs of Rx differential signals are consistent, thereby ensuring the accuracy of the signal test results. By designing the length difference between the first input line and the second input line to be less than 1 mil, and the length difference between the first output line and the second output line to be less than 1 mil, it is possible to further ensure that the transmission losses of each pair of Tx differential signals and each pair of Rx differential signals are consistent, thereby improving the accuracy of signal testing.

[0067] Furthermore, the line widths of the first input line, the second input line, the first output line, and the second output line are processed according to 85 Ohm specified by the emulated PCIe Association to ensure the transmission quality of the Tx differential signal and the Rx differential signal.

[0068] Optionally, the fixture board 1 includes eight stacked layers, the plurality of first transmission lines 5 are all located on the sixth stack of the fixture board 1, and the fifth stack 11 and the seventh stack 12 of the fixture board 1 are both GND planes. Figure 8 , Fig.10 and Fig.11 As shown, the stack where the first transmission line 5 is located is the sixth stack, and the fifth stack 11 and the seventh stack 12 are designed as GND planes as the reference planes of the sixth stack, which can provide a shorter return path for the signal on the first transmission line 5 and reduce the impact of impedance discontinuity on the transmission signal.

[0069] Optionally, see Figure 4 and Fig.12 , the PCIe signal test fixture of the U.2 connector also includes a second transmission line 6, the second transmission line 6 is located at the bottom layer of the fixture board 1, the first row of pins 21 also includes a second pin (not shown) corresponding to the second SMP connector 4, and a second via 212 is provided on the second pin. One end of the second transmission line 6 is electrically connected to the U.2 interface 2 through the second via 212, and the other end is connected to the second SMP connector 4. In this embodiment, the second transmission line 6 is a pair of differential lines, including a P line and an N line. The clock signal at the U.2 connector interface 101 of the board to be tested 100 is led out to the second SMP connector 4 on the fixture board 1 through the pair of differential lines. When performing signal testing, the reference clock signal and the data signal of each Lane are connected to the oscilloscope together to obtain the waveform data of the PCIe signal to be tested. The clock signal plays an important role in communication equipment, and its signal quality often directly affects the performance indicators of the product. Therefore, quality testing of the clock signal is essential.

[0070] Optionally, the first via 2111 and the second via 212 are both processed by the POFV process, and the Stub is removed by the back drilling process at the first via 2111 on the jig board 1, and a GND return hole 213 spaced from the first via 2111 is provided at the first via 2111 on the jig board 1. That is, the Stub of the first via 2111 only extends to the sixth stack of the jig board 1, and the redundant Stub on the first via 2111 will increase the impedance of the first transmission line 5, affecting the signal transmission quality. Therefore, the Stub of the first via 2111 in the seventh stack 12 to the eighth stack is removed by the back drilling process, which can ensure the continuity of the first via 2111 and improve the transmission quality of the high-speed differential signal. Since the signal will bring about a large impedance fluctuation when passing through the via layer during the high-speed differential line transmission, the electric field radiation can be reduced and the signal crosstalk can be suppressed by providing the GND return hole 213 near the first via 2111. At the same time, the GND return hole 213 can also provide a minimum inductance return path for the first via 2111, thereby improving signal transmission quality. In addition, by simulating the size of the Antipad through a simulation tool and designing the Antipad distance to adjust the impedance drop caused by the via, signal transmission quality can be further improved.

[0071] Furthermore, at the lower end of the first via hole 2111 (ie, the seventh stack 12 to the eighth stack), the circular pad and part of the hole wall are drilled out by a back drilling process to further reduce impedance and improve signal transmission quality.

[0072] Optionally, see Figure 3 , Figure 4 and Fig.13 , the PCIe signal test fixture of the U.2 connector also includes a first calibration line 7 and a second calibration line 8 arranged on the fixture board 1. The length of the second calibration line 8 is twice the length of the first calibration line 7. Both ends of the first calibration line 7 and both ends of the second calibration line 8 are connected to a third SMP connector 9, and the third SMP connector 9 is configured to be connected to a vector network analyzer VNA. Since the link loss of the transmission line on the fixture board 1 will change to a certain extent after being used for a period of time, the link loss data of the transmission line on the current fixture board 1 can be obtained by setting the first calibration line 7 and the second calibration line 8 on the fixture board 1. Specifically, before performing the signal test, the vector network analyzer VNA is connected to the first calibration line 7 and the second calibration line 8 through the third SMP connector 9, and then the link loss on the first calibration line 7 and the link loss on the second calibration line 8 are measured by the vector network analyzer VNA in a de-embedded manner. Since the length of the second calibration line 8 is twice the length of the first calibration line 7, the link loss on the transmission line per unit length on the fixture board 1 can be calculated, thereby obtaining the link loss data on the first transmission line 5, thereby more accurately testing the PCIe signal to be tested at the connector interface 101 of the test board 100U.2, thereby improving the signal testing accuracy.

[0073] Optionally, the fixture board 1 is made of a PCB high-speed board. Using a PCB high-speed board to make the fixture board 1 can reduce the attenuation of the entire test fixture and meet the PCIe5.0 design requirements. Preferably, the PCB high-speed board is a board of model IT968G.

[0074] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. PCIe signal test fixture for U.2 connector, characterized in that: include: Jig board (1); A U.2 interface (2), the U.2 interface (2) being arranged at one end of the fixture board (1), the U.2 interface (2) being configured to be connected to a U.2 connector interface (101) of a board to be tested (100); A plurality of first transmission lines (5), the fixture board (1) comprising eight stacked layers stacked in sequence, the plurality of first transmission lines (5) being located on the sixth stack of the fixture board (1), and the fifth stack (11) and the seventh stack (12) of the fixture board (1) being GND planes; the fifth stack and the seventh stack are designed as GND planes as reference planes for the sixth stack, so as to provide a shorter return path for the signal on the first transmission line, thereby reducing the influence of impedance discontinuity on the transmission signal; A plurality of connectors are spaced apart on the fixture board (1), the plurality of connectors are electrically connected to the U.2 interface (2), the connectors are configured to be connected to an oscilloscope, and the PCIe signal to be tested on the board to be tested (100) can be led out to the plurality of connectors via the U.2 interface (2); The plurality of connectors include a plurality of first SMP connectors (3); a first row of pins (21) and a second row of pins (22) are arranged in the U.2 interface (2); the first row of pins (21) is close to the board to be tested (100); the first row of pins (21) includes first pins (211) corresponding to the plurality of first SMP connectors (3); each of the first pins (211) is provided with a first via hole (2111); and the first SMP connector (3) is electrically connected to the U.2 interface (2) via the corresponding first via hole (2111).

2. The PCIe signal test fixture for the U.2 connector according to claim 1, characterized in that: A plurality of the first SMP connectors (3) are distributed in an array on the fixture board (1), and the first SMP connectors (3) are used to lead out high-speed PCIe signals on the board to be tested (100); The plurality of connectors further include a second SMP connector (4), wherein the second SMP connector (4) is used to lead out a clock signal on the board to be tested (100).

3. The PCIe signal test fixture for the U.2 connector according to claim 1, characterized in that: A plurality of the first transmission lines (5) are located between the two stacked layers inside the fixture board (1); one end of the first transmission line (5) is connected to the corresponding first pin (211) through the first via (2111), and the other end is connected to the corresponding first SMP connector (3).

4. The PCIe signal test fixture of the U.2 connector according to claim 3, characterized in that: The plurality of first transmission lines (5) include: n groups of Tx differential lines, the lengths of the n groups of Tx differential lines are equal, each group of Tx differential lines includes a first input line and a second input line, the length difference between the first input line and the second input line is d1, d1<1 mil; There are n groups of Rx differential lines, the lengths of the n groups of Rx differential lines are equal, each group of Rx differential lines includes a first output line and a second output line, the length difference between the first output line and the second output line is d2, and d2<1 mil.

5. The PCIe signal test fixture of the U.2 connector according to claim 2, characterized in that: The PCIe signal test fixture of the U.2 connector further comprises a second transmission line (6), wherein the second transmission line (6) is located at the bottom layer of the fixture board (1), the first row of pins (21) further comprises a second pin corresponding to the second SMP connector (4), a second via hole (212) is provided on the second pin, one end of the second transmission line (6) is electrically connected to the U.2 interface (2) through the second via hole (212), and the other end is connected to the second SMP connector (4).

6. The PCIe signal test fixture of the U.2 connector according to claim 5, characterized in that: The first via hole (2111) and the second via hole (212) are both processed by a POFV process, the stub is removed at the first via hole (2111) on the jig plate (1) by a back drilling process, and a GND return hole (213) spaced apart from the first via hole (2111) is provided at the first via hole (2111) on the jig plate (1).

7. The PCIe signal test fixture of the U.2 connector according to any one of claims 1 to 6, characterized in that: The PCIe signal test fixture for the U.2 connector further comprises a first calibration line (7) and a second calibration line (8) arranged on the fixture board (1); the length of the second calibration line (8) is twice the length of the first calibration line (7); both ends of the first calibration line (7) and both ends of the second calibration line (8) are connected to a third SMP connector (9); the third SMP connector (9) is configured to be connected to a vector network analyzer (VNA).

8. The PCIe signal test fixture of the U.2 connector according to any one of claims 1 to 6, characterized in that: The jig plate (1) is made of PCB high-speed plate.

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