Pixel driving circuit, array substrate and display device

Abstract

The embodiment of the present application provides a pixel driving circuit, an array substrate and a display device, wherein the pixel driving circuit includes: a driving module for providing a driving current for a light-emitting element; a data writing module electrically connected to a first scanning signal terminal, a data signal terminal and a first terminal of the driving module; a threshold compensation module electrically connected to a second scanning signal terminal, a control terminal of the driving module and a second terminal of the driving module; a first storage module, a first terminal of which is electrically connected to the control terminal of the driving module, and a second terminal of which is electrically connected to a first electrode of the light-emitting element; in the threshold compensation stage, the data writing module is turned on in response to a turn-on level provided by the first scanning signal terminal, and the threshold compensation module is turned on in response to a turn-on level provided by the second scanning signal terminal; in the light-emitting stage, the first storage module adjusts the potential of the control terminal of the driving module in response to a potential change of the first electrode of the light-emitting element. The embodiment of the present application can improve the Mura phenomenon and improve display uniformity.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and in particular relates to a pixel driving circuit, an array substrate and a display device. Background Art

[0002] In current display panels, due to the limitations of the crystallization process, thin film transistors (TFT) at different locations often have non-uniformity in electrical parameters such as threshold voltage and mobility. This non-uniformity will be converted into brightness and chromaticity differences among sub-pixels in the display panel and will be perceived by the human eye, which is the Mura phenomenon. Summary of the invention

[0003] The embodiments of the present application provide a pixel driving circuit, an array substrate and a display device, which can improve the Mura phenomenon of a display panel and enhance display uniformity.

[0004] In a first aspect, an embodiment of the present application provides a pixel driving circuit, which includes: a driving module for providing a driving current for a light-emitting element; a data writing module, wherein a control end of the data writing module is electrically connected to a first scanning signal end, a first end of the data writing module is electrically connected to a data signal end, and a second end of the data writing module is electrically connected to a first end of the driving module; a threshold compensation module, wherein a control end of the threshold compensation module is electrically connected to a second scanning signal end, a first end of the threshold compensation module is electrically connected to a control end of the driving module, and a second end of the threshold compensation module is electrically connected to a second end of the driving module; a first storage module, wherein a first end of the first storage module is electrically connected to a control end of the driving module, and a second end of the first storage module is electrically connected to a first electrode of the light-emitting element; in a threshold compensation stage, the data writing module is turned on in response to a turn-on level provided by the first scanning signal end, and the threshold compensation module is turned on in response to a turn-on level provided by the second scanning signal end; in a light-emitting stage, the first storage module adjusts the potential of the control end of the driving module in response to a change in the potential of the first electrode of the light-emitting element.

[0005] In the second aspect, an embodiment of the present application provides an array substrate, the array substrate comprising: a first positive power supply voltage signal line extending along a first direction; a second positive power supply voltage signal line extending along a second direction, the first direction intersecting the second direction; a plurality of pixel driving circuits, the pixel driving circuits being arranged in an array along the first direction and the second direction, the pixel driving circuits being electrically connected to the first positive power supply voltage signal line and the second positive power supply voltage signal line, respectively; the pixel driving circuit comprising: a first transistor, the gate of the first transistor being electrically connected to a first node, the first transistor being used to provide a driving current for a light-emitting element; a first storage capacitor, the first plate of the first storage capacitor being electrically connected to the first node, the second plate of the first storage capacitor being electrically connected to the first electrode of the light-emitting element via a first connecting portion.

[0006] In a third aspect, an embodiment of the present application provides a display device, which includes a pixel driving circuit as provided in the first aspect or an array substrate as provided in the second aspect.

[0007] In the pixel driving circuit, array substrate and display device of the embodiment of the present application, the first end of the first storage module is electrically connected to the control end of the driving module, and the second end of the first storage module is electrically connected to the first electrode of the light-emitting element. In the threshold compensation stage, the data writing module is turned on in response to the conduction level provided by the first scanning signal end, and the threshold compensation module is turned on in response to the conduction level provided by the second scanning signal end, so as to compensate for the threshold voltage of the driving module. In the light-emitting stage, the first storage module adjusts the potential of the control end of the driving module in response to the potential change of the first electrode of the light-emitting element. Since the second end of the driving module is connected to the first electrode of the light-emitting element in the light-emitting stage, the change trend of the potential of the control end of the driving module can be kept consistent with the change trend of the potential of the second end of the driving module through the adjustment of the first storage module, so that the threshold voltage can be maintained in the voltage difference between the potential of the control end of the driving module and the potential of the second end of the driving module, thereby eliminating the influence of the threshold voltage on the driving current, improving the Mura phenomenon of the display panel, and improving the display uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0009] Figure 1 A circuit diagram of a pixel driving circuit provided in an embodiment of the present application;

[0010] Figure 2 for Figure 1 A driving timing diagram corresponding to the pixel driving circuit shown;

[0011] Figure 3 Another circuit diagram of a pixel driving circuit provided in an embodiment of the present application;

[0012] Figure 4 A further circuit diagram of a pixel driving circuit provided in an embodiment of the present application;

[0013] Figure 5 for Figure 4 A driving timing diagram corresponding to the pixel driving circuit shown;

[0014] Figure 6 for Figure 4Another driving timing diagram corresponding to the pixel driving circuit shown;

[0015] Figure 7 A further circuit diagram of a pixel driving circuit provided in an embodiment of the present application;

[0016] Figure 8 for Figure 7 Another driving timing diagram corresponding to the pixel driving circuit shown;

[0017] Fig. 9 A further circuit diagram of a pixel driving circuit provided in an embodiment of the present application;

[0018] Fig.10 A local layout of the array substrate provided in the embodiment of the present application;

[0019] Fig.11 For along Fig.10 A schematic cross-sectional view in the A1-A2 direction;

[0020] Fig.12 Another partial layout of the array substrate provided in the embodiment of the present application;

[0021] Fig.13 For along Fig.12 A cross-sectional schematic diagram in the B1-B2 direction;

[0022] Fig.14 A schematic diagram of the structure of a first connecting portion and a light-emitting control signal line in an array substrate provided in an embodiment of the present application;

[0023] Fig.15 A schematic diagram of the structure of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0025] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0026] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0027] It should be noted that the transistors in the embodiments of the present application are described by taking N-type transistors as an example, but are not limited to N-type transistors, and can also be replaced by P-type transistors. For N-type transistors, the on-level is a high level and the off-level is a low level. That is, when the gate of the N-type transistor is at a high level, the first pole and the second pole are connected, and when the gate of the N-type transistor is at a low level, the first pole and the second pole are disconnected. For P-type transistors, the on-level is a low level and the off-level is a high level. That is, when the control terminal of the P-type transistor is at a low level, the first pole and the second pole are connected, and when the control terminal of the P-type transistor is at a high level, the first pole and the second pole are disconnected. In a specific implementation, the gate of each of the above-mentioned transistors serves as its control electrode, and, according to the signal of the gate of each transistor and its type, its first electrode can be used as the source and the second electrode as the drain, or its first electrode can be used as the drain and the second electrode as the source, without making any distinction here. In addition, the on-level and off-level in the embodiments of the present invention are both general terms, the on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / shut down the transistor.

[0028] In the embodiments of the present application, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0029] In the embodiments of the present application, the first node, the second node, the third node, the fourth node and the fifth node are only defined for the convenience of describing the circuit structure. The first node, the second node, the third node, the fourth node and the fifth node are not actual circuit units.

[0030] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0031] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate the understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0032] In current display panels, due to the limitations of the crystallization process, thin film transistors (TFT) at different locations often have non-uniformity in electrical parameters such as threshold voltage and mobility. This non-uniformity will be converted into brightness and chromaticity differences among sub-pixels in the display panel, resulting in uneven brightness display, namely the Mura phenomenon.

[0033] In order to solve the above technical problems, the embodiments of the present application provide a pixel driving circuit, an array substrate and a display device.

[0034] The technical concept of the embodiment of the present application is: in the threshold compensation stage, compensation for the threshold voltage of the driving module is achieved. Moreover, in the light-emitting stage, the potential of the control end of the driving module is adjusted in response to the potential change of the first electrode of the light-emitting element through the first storage module. Since the second end of the driving module is connected to the first electrode of the light-emitting element in the light-emitting stage, the change trend of the potential of the control end of the driving module can be kept consistent with the change trend of the potential of the second end of the driving module through the adjustment of the first storage module, so that the threshold voltage can be maintained within the voltage difference between the potential of the control end of the driving module and the potential of the second end of the driving module, thereby eliminating the influence of the threshold voltage on the driving current, improving the Mura phenomenon of the display panel, and improving the display uniformity.

[0035] The following first introduces the pixel driving circuit provided in the embodiment of the present application.

[0036] Figure 1 A circuit diagram of a pixel driving circuit provided in an embodiment of the present application. Figure 1As shown, the pixel driving circuit 10 provided in the embodiment of the present application may include a driving module 101, a data writing module 102, a threshold compensation module 103 and a first storage module 104. The driving module 101 is used to provide a driving current for the light-emitting element D. Exemplarily, the light-emitting element D includes but is not limited to an organic light-emitting diode (OLED).

[0037] The control end of the data writing module 102 is electrically connected to the first scanning signal end S1, the first end of the data writing module 102 is electrically connected to the data signal end data, and the second end of the data writing module 102 is electrically connected to the first end of the driving module 101. The control end of the threshold compensation module 103 is electrically connected to the second scanning signal end S2, the first end of the threshold compensation module 103 is electrically connected to the control end of the driving module 101, and the second end of the threshold compensation module 103 is electrically connected to the second end of the driving module 101. In some examples, the driving module 101 may include a thin film transistor, the control end of the driving module 101 may specifically be a gate of the thin film transistor, the first end of the driving module 101 may specifically be a drain of the thin film transistor, and the second end of the driving module 101 may specifically be a source of the thin film transistor. Of course, the first end of the driving module 101 may also be a source of a thin film transistor, and the second end of the driving module 101 may also be a drain of a thin film transistor, which is not limited in the embodiments of the present application.

[0038] The first end of the first storage module 104 is electrically connected to the control end of the driving module 101 , and the second end of the first storage module 104 is electrically connected to the first electrode of the light emitting element D. Exemplarily, the first electrode of the light emitting element D may be an anode of the light emitting element D.

[0039] Figure 2 for Figure 1 A driving timing diagram corresponding to the pixel driving circuit shown in FIG. Figure 1 and Figure 2 As shown, within one frame time, the driving process of the pixel driving circuit 10 at least includes a threshold compensation stage t2 and a light emitting stage t3. In the threshold compensation stage t2, the data writing module 102 is turned on in response to the conduction level provided by the first scanning signal terminal S1, and the data signal output by the data signal terminal data is written to the first end of the driving module 101. The threshold compensation module 103 is turned on in response to the conduction level provided by the second scanning signal terminal S2, connecting the control end of the driving module 101 and the second end of the driving module 101, and the data signal is transmitted to the control end of the driving module 101 through the turned-on threshold compensation module 103, completing the threshold voltage Vth compensation of the driving module 101. The first storage module 104 can maintain the potential of the control end of the driving module 101.

[0040] In the light emitting stage t3, the first storage module 104 adjusts the potential of the control end of the driving module 101 in response to the potential change of the first electrode of the light emitting element D, so that the potential change trend of the first electrode of the light emitting element D is consistent with the potential change trend of the control end of the driving module 101. Since the second end of the driving module 101 is connected to the first electrode of the light emitting element D in the light emitting stage t3, the potential change trend of the control end of the driving module 101 can be consistent with the potential change trend of the second end of the driving module 101 through the adjustment of the first storage module 104, so that the threshold voltage Vth can be maintained within the voltage difference between the potential of the control end of the driving module 101 and the potential of the second end of the driving module 101, thereby eliminating the influence of the threshold voltage Vth on the driving current of the pixel driving circuit 10, improving the Mura phenomenon of the display panel, and improving the display uniformity.

[0041] Figure 3 Another circuit diagram of a pixel driving circuit provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, according to some embodiments of the present application, optionally, the first storage module 104 may include a first storage capacitor C1. The first plate of the first storage capacitor C1 may be electrically connected to the control end of the driving module 101, and the second plate of the first storage capacitor C1 may be electrically connected to the first electrode of the light-emitting element D. It can be understood that, in addition to the function of storing charge, the first storage capacitor C1 also has a coupling function. In the light-emitting stage t3, the first storage capacitor C1 may respond to the potential change of the first electrode of the light-emitting element D, and adjust the potential of the control end of the driving module 101 through its own coupling effect, so that the potential change trend of the first electrode of the light-emitting element D is consistent with the potential change trend of the control end of the driving module 101.

[0042] In this way, by using the first storage capacitor C1 as the first storage module 104, on the one hand, the performance of the capacitor in storing charges can be utilized to maintain the potential of the control end of the driving module 101; on the other hand, the coupling performance of the capacitor can be utilized to adjust the potential of the control end of the driving module 101 during the light-emitting stage, so that the change trend of the potential of the control end of the driving module 101 can be consistent with the change trend of the potential of the second end of the driving module 101, so that the threshold voltage Vth can be maintained within the voltage difference between the potential of the control end of the driving module 101 and the potential of the second end of the driving module 101, thereby eliminating the influence of the threshold voltage Vth on the driving current of the pixel driving circuit 10, improving the Mura phenomenon of the display panel, and improving the display uniformity.

[0043] Figure 4 1 is another circuit diagram of a pixel driving circuit provided in an embodiment of the present application. Figure 4As shown, according to some embodiments of the present application, optionally, the pixel driving circuit 10 may further include a first reset module 401. The control end of the first reset module 401 may be electrically connected to the third scanning signal end S3, the first end of the first reset module 401 may be electrically connected to the first initialization signal end V1, and the second end of the first reset module 401 may be electrically connected to the control end of the driving module 101.

[0044] Figure 5 for Figure 4 A driving timing diagram corresponding to the pixel driving circuit shown in FIG. Figure 4 and Figure 5 As shown, before the threshold compensation stage t2, the driving process of the pixel driving circuit 10 may further include a first initialization stage t0. In the first initialization stage t0, the first reset module 401 may be turned on in response to the conduction level provided by the third scanning signal terminal S3, and transmit the first initialization signal of the first initialization signal terminal V1 to the control terminal of the driving module 101 to reset the control terminal of the driving module 101. In some optional examples, the driving module 101 may be an N-type thin film transistor, and the first initialization signal terminal V1 may specifically be a first positive power supply voltage signal terminal (or first positive power supply voltage signal line) VDD. The first positive power supply voltage signal terminal VDD may provide a first initialization signal of a forward voltage value, thereby resetting the control terminal of the driving module 101 using the first initialization signal of a forward voltage value.

[0045] Thus, by adding the first reset module 401 to reset the control end of the driving module 101 , it can be ensured that subsequent data signals can be successfully written to the control end of the driving module 101 , thereby ensuring normal light emission of the sub-pixels and normal display of the display panel.

[0046] Figure 6 for Figure 4 Another driving timing diagram corresponding to the pixel driving circuit shown in FIG. Figure 4 and Figure 6 As shown, according to some embodiments of the present application, optionally, a second initialization stage t1 may be included between the first initialization stage t0 and the threshold compensation stage t2. In the second initialization stage t1, the first reset module 401 is turned on in response to the on-level provided by the third scan signal terminal S3, and transmits the first initialization signal of the first initialization signal terminal V1 to the control terminal of the driving module 101 to reset the control terminal of the driving module 101.

[0047] So, in Figure 6In the illustrated embodiment, the control end of the driving module 101 is reset not only in the first initialization stage t0, but also in the second initialization stage t1, thereby increasing the duration of resetting the control end of the driving module 101, ensuring that the control end of the driving module 101 can be successfully reset, thereby ensuring that subsequent data signals can be successfully written to the control end of the driving module 101, and the normal display of the display panel.

[0048] Continue to see Figure 4 According to some embodiments of the present application, optionally, the pixel driving circuit 10 may further include a second reset module 402, the control end of the second reset module 402 is electrically connected to the fourth scan signal end S4, the first end of the second reset module 402 is electrically connected to the second initialization signal end V2, and the second end of the second reset module 402 is electrically connected to the first electrode of the light-emitting element D.

[0049] Combination Figure 4 and Figure 6 As shown, according to some embodiments of the present application, optionally, in the second initialization stage t1, the second reset module 402 may be turned on in response to the on-level provided by the fourth scan signal terminal S4, and transmit the second initialization signal of the second initialization signal terminal V2 to the first electrode of the light-emitting element D, so as to reset the first electrode of the light-emitting element D. In some examples, the fourth scan signal terminal S4 may specifically be a reference voltage signal terminal Vref, and the reference voltage signal terminal Vref may be used to provide a second initialization signal of a negative voltage value, and the first electrode of the light-emitting element D is reset by the second initialization signal of the negative voltage value.

[0050] Thus, before the light emitting stage, by adding the second resetting module 402 to reset the first electrode of the light emitting element D, the residual charge at the first electrode of the light emitting element D can be released, thereby effectively improving the afterimage phenomenon.

[0051] Continue to combine Figure 4 and Figure 6 As shown, according to some embodiments of the present application, optionally, in the threshold compensation stage t2, the second reset module 402 can be turned on in response to the turn-on level provided by the fourth scan signal terminal S4, and continuously reset the first electrode of the light-emitting element D through the second initialization signal.

[0052] Thus, on the one hand, by continuously resetting the first electrode of the light-emitting element D in the second initialization stage t1 and the threshold compensation stage t2, it is helpful to release the residual charge of the first electrode of the light-emitting element D as much as possible, and better improve the afterimage phenomenon; on the other hand, resetting the first electrode of the light-emitting element D in advance in the second initialization stage t1 can effectively avoid the potential of the first electrode of the light-emitting element D from jumping down when the data signal is written, thereby affecting the potential of the control terminal of the driving module 101, and ensuring that the control terminal of the driving module 101 can reach the target voltage value, for example, Vdata+Vth. Wherein, Vdata represents the voltage value of the data signal, and Vth represents the threshold voltage of the driving module 101.

[0053] Continue to see Figure 4 According to some embodiments of the present application, optionally, the fourth scan signal terminal S4 can reuse the second scan signal terminal S2. That is, the second reset module 402 can be turned on or off at the same time as the threshold compensation module 103.

[0054] In this way, since the fourth scan signal terminal S4 multiplexes the second scan signal terminal S2, the number of signal terminals / lines and shift registers in the display panel can be reduced, thus saving wiring space and reducing production costs.

[0055] Continue to combine Figure 4 and Figure 6 As shown, according to some embodiments of the present application, optionally, in the second initialization stage t1, the threshold compensation module 103 can be turned on in response to the turn-on level provided by the second scanning signal terminal S2, and the first initialization signal provided by the first initialization signal terminal V1 can be transmitted to the second end of the driving module 101 through the threshold compensation module 103 to reset the second end of the driving module 101.

[0056] In this way, before writing the data signal, by resetting the second end of the driving module 101, the potential of the second end of the driving module 101 can be made consistent with the potential of the control end of the driving module 101, so that when the data signal is subsequently written, the threshold voltage Vth can be successfully stored in the voltage difference between the potential of the control end of the driving module 101 and the potential of the second end of the driving module 101.

[0057] For ease of understanding, the pixel driving circuit 10 is described below with reference to some specific application embodiments.

[0058] Figure 7 1 is another circuit diagram of a pixel driving circuit provided in an embodiment of the present application. Figure 7As shown, according to some embodiments of the present application, optionally, the pixel driving circuit 10 may include a 7T1C pixel circuit. Specifically, the pixel driving circuit 10 may include a driving module 101, a data writing module 102, a threshold compensation module 103, a first storage module 104, a first reset module 401, a first light-emitting control module 701, a second light-emitting control module 702, and a second reset module 402. The driving module 101 may include a first transistor T1, the data writing module 102 may include a second transistor T2, the threshold compensation module 103 may include a third transistor T3, the first reset module 401 may include a fourth transistor T4, the first light-emitting control module 701 may include a fifth transistor T5, the second light-emitting control module 702 may include a sixth transistor T6, the second reset module 402 may include a seventh transistor T7, and the first storage module 104 may include a first storage capacitor C1.

[0059] A gate of the first transistor T1 is electrically connected to the first node N1 , a first electrode of the first transistor T1 is electrically connected to the second node N2 , and a second electrode of the first transistor T1 is electrically connected to the third node N3 .

[0060] The first electrode of the light emitting element D is electrically connected to the fourth node N4, and the second electrode of the light emitting element D is electrically connected to the second power supply voltage signal terminal PVEE. Exemplarily, the second electrode of the light emitting element D may be a cathode of the light emitting element D. The second power supply voltage signal terminal PVEE may specifically be a negative power supply voltage signal terminal, that is, a power supply voltage signal providing a negative voltage value.

[0061] A gate of the second transistor T2 is electrically connected to the first scan signal terminal S1 , a first electrode of the second transistor T2 is electrically connected to the data signal terminal data, and a second electrode of the second transistor T2 is electrically connected to the second node N2 .

[0062] The gate of the third transistor T3 is electrically connected to the second scan signal terminal S2, the first electrode of the third transistor T3 is electrically connected to the first node N1, and the second electrode of the third transistor T3 is electrically connected to the third node N3. Exemplarily, the third transistor T3 can be a dual-gate transistor, and the first gate and the second gate of the dual-gate transistor can both be electrically connected to the second scan signal terminal S2.

[0063] A gate of the fourth transistor T4 is electrically connected to the third scan signal terminal S3 , a first electrode of the fourth transistor T4 is electrically connected to the first initialization signal terminal V1 , and a second electrode of the fourth transistor T4 is electrically connected to the first node N1 .

[0064] A gate of the fifth transistor T5 is electrically connected to the light emitting control signal terminal EM, a first electrode of the fifth transistor T5 is electrically connected to the second positive power supply voltage signal terminal PVDD, and a second electrode of the fifth transistor T5 is electrically connected to the second node N2.

[0065] A gate of the sixth transistor T6 is electrically connected to the light emitting control signal terminal EM, a first electrode of the sixth transistor T6 is electrically connected to the third node N3, and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4.

[0066] A gate of the seventh transistor T7 is electrically connected to the fourth scan signal terminal S4, a first electrode of the seventh transistor T7 is electrically connected to the second initialization signal terminal V2, and a second electrode of the seventh transistor T7 is electrically connected to the fourth node N4.

[0067] The first plate of the first storage capacitor C1 is electrically connected to the first node N1 , and the second plate of the first storage capacitor C1 is electrically connected to the fourth node N2 .

[0068] In some embodiments, the second scan signal terminal S2 and the fourth scan signal terminal S4 can be multiplexed.

[0069] In some embodiments, the waveform of the scanning signal outputted from the second scanning signal terminal S2 and the waveform of the scanning signal outputted from the third scanning signal terminal S3 may be the same, and the phase difference is a preset time interval.

[0070] Figure 8 for Figure 7 Another driving timing diagram corresponding to the pixel driving circuit shown in FIG. Figure 7 and Figure 8 As shown, according to some embodiments of the present application, optionally, the driving process of the pixel driving circuit 10 may include a first initialization stage t0, a second initialization stage t1, a threshold compensation stage t2 and a light emitting stage t3. In the first initialization stage t0, the third scanning signal terminal S3 outputs a conduction level, the fourth transistor T4 is turned on, and the first initialization signal of the first initialization signal terminal V1 is transmitted to the first node N1, and the potential of the first node N1 is, for example, equal to Vdd. Wherein, Vdd represents the voltage value of the first initialization signal.

[0071] In the second initialization stage t1, the second scan signal terminal S2, the third scan signal terminal S3 and the fourth scan signal terminal S4 output the conduction level. The fourth transistor T4 is continuously turned on, and the first initialization signal of the first initialization signal terminal V1 continues to reset the first node N4. At the same time, the third transistor T3 is turned on in response to the conduction level of the second scan signal terminal S2, and the first initialization signal is transmitted to the third node N3 through the turned-on third transistor T3, and the third node N3 is reset. The potential of the first node N1 and the potential of the third node N3 are both equal to Vdd. The seventh transistor T7 is turned on in response to the conduction level of the fourth scan signal terminal S4, and the second initialization signal of the second initialization signal terminal V2 is transmitted to the fourth node N4 through the turned-on seventh transistor T7, and the fourth node N4 is reset. The potential of the fourth node N4 is, for example, equal to vref. Wherein, vref represents the voltage value of the second initialization signal.

[0072] In the threshold compensation stage t2, the first scan signal terminal S1, the second scan signal terminal S2 and the fourth scan signal terminal S4 output the conduction level. The second transistor T2 is turned on in response to the conduction level of the first scan signal terminal S1, and the data signal of the data signal terminal data is written into the second node N2. The first transistor T1 is turned on in response to the conduction level of the first node N1, and the third transistor T3 is turned on in response to the conduction level of the second scan signal terminal S2. The data signal is written into the first node N1 through the turned-on first transistor T1 and the third transistor T3, and the threshold voltage compensation of the first transistor T1 is realized at the same time. The potential of the first node N1 and the potential of the third node N3 are both equal to Vdata+Vth. Among them, Vdata represents the voltage value of the data signal, and Vth represents the threshold voltage of the first transistor T1. The seventh transistor T7 is continuously turned on, and the second initialization signal continues to reset the fourth node N4, and the potential of the fourth node N4 is equal to vref.

[0073] In the light-emitting stage t3, the light-emitting control signal terminal EM outputs a conduction level, the fifth transistor T5 and the sixth transistor T6 are turned on in response to the conduction level of the light-emitting control signal terminal EM, and the first transistor T1 is turned on in response to the conduction level of the first node N1. The potential of the fourth node N4 is raised, and the potential of the fourth node N4 changes from vref to pvee+Vd. Among them, pvee represents the voltage value of the second power supply voltage signal output by the second power supply voltage signal terminal PVEE, and Vd represents the voltage value of the light-emitting element D. The voltage change difference of the potential of the fourth node N4 is Δu=pvee+Vd-vref. Under the coupling effect of the first storage capacitor C1, the potential of the first node N1 also changes accordingly Δu. The potential of the first node N1 is Vdata+Vth+Δu, that is, Vdata+Vth+pvee+Vd-vref. The voltage difference between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1 is equal to the voltage difference between the potential of the first node N1 and the potential of the fourth node N4, specifically Vgs=Vdata+Vth+pvee+Vd-vref-(pvee+Vd)=Vdata+Vth-vref. Accordingly, the driving current of the pixel driving circuit 10 is I=K(Vgs-Vth) 2 =K(Vdata-Vref) 2 .

[0074] It can be seen that the magnitude of the driving current of the pixel driving circuit 10 is not affected by the threshold voltage Vth of the first transistor T1 , thereby improving the Mura phenomenon of the display panel and improving display uniformity.

[0075] According to some embodiments of the present application, optionally, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 can all be N-type transistors. For N-type transistors, the conduction level is a high level and the cut-off level is a low level.

[0076] Compared with P-type transistors, N-type transistors have a smaller leakage current. Therefore, the stability of the potential of each node can be guaranteed, thereby ensuring the stability of the display of the display panel and effectively avoiding flickering.

[0077] Fig. 9 1 is another circuit diagram of a pixel driving circuit provided in an embodiment of the present application. Fig. 9 As shown, according to some embodiments of the present application, optionally, the pixel driving circuit 10 may include an 8T1C pixel circuit. Figure 7Different from the illustrated embodiment, the pixel driving circuit 10 may further include a bias voltage compensation module 901. The control end of the bias voltage compensation module 901 is electrically connected to the fifth scanning signal end S5, the first end of the bias voltage compensation module 901 is electrically connected to the bias voltage signal end VH, and the second end of the bias voltage compensation module 901 is electrically connected to the first end of the driving module 101 or the second end of the driving module 101.

[0078] Before the light-emitting stage, the bias voltage compensation module 901 can be used to be turned on in response to the conduction level provided by the fifth scanning signal terminal S5, and transmit the bias voltage signal of the bias voltage signal terminal VH to the first end of the driving module 101 or the second end of the driving module 101. Under the control of the conduction level of the first node N1, the driving module 101 is in a conducting state. Therefore, whether the bias voltage signal of the bias voltage signal terminal VH is transmitted to the first end of the driving module 101, or the bias voltage signal of the bias voltage signal terminal VH is transmitted to the second end of the driving module 101, the bias voltage signal can be transmitted to the second end of the driving module 101. The voltage value of the bias voltage signal is a forward voltage value, so the potential of the second end of the driving module 101 can be raised, so that the potential of the second end of the driving module 101 is higher than the potential of the control end of the driving module 101, thereby adjusting the offset state of the threshold voltage of the driving module 101, and then the brightness of the first frame after the display panel switches the screen can be improved.

[0079] Continue to see Fig. 9 According to some embodiments of the present application, optionally, the bias voltage compensation module 901 may include an eighth transistor T8. The gate of the eighth transistor T8 is electrically connected to the fifth scan signal terminal S5, the first electrode of the eighth transistor T8 is electrically connected to the bias voltage signal terminal VH, and the second electrode of the eighth transistor T8 is electrically connected to the first terminal of the driving module 101 or the second terminal of the driving module 101. Before the light-emitting stage, the eighth transistor T8 is turned on, and the bias voltage signal of the bias voltage signal terminal VH is transmitted to the first terminal of the driving module 101 or the second terminal of the driving module 101, so as to adjust the offset state of the threshold voltage of the driving module 101.

[0080] It should be noted that the above-mentioned 7T1C pixel circuit and 8T1C pixel circuit are only examples. The pixel driving circuit 10 of the embodiment of the present application includes but is not limited to the 7T1C pixel circuit and the 8T1C pixel circuit, and may also be other types of pixel driving circuits, such as a 7T2C pixel circuit, a 9T1C pixel circuit, and a 9T2C pixel circuit.

[0081] Based on the pixel driving circuit 10 provided in the above embodiment, accordingly, the embodiment of the present application further provides an array substrate.

[0082] Before introducing the array substrate, it should be noted that the signal terminal and the signal line in the embodiment of the present application can be understood as the same concept. For example, the first positive power supply voltage signal terminal can also be called the first positive power supply voltage signal line, or it can also be understood that the first positive power supply voltage signal terminal and the first positive power supply voltage signal line have the same potential and are electrically connected to each other.

[0083] Fig.10 A local layout of the array substrate provided in the embodiment of the present application. Fig.10 As shown, the array substrate 100 may include a first positive power supply voltage signal line VDD, a second positive power supply voltage signal line PVDD, and a pixel driving circuit 10. The first positive power supply voltage signal line VDD may extend along a first direction X, and the second positive power supply voltage signal line PVDD may extend along a second direction Y, and the first direction X intersects the second direction Y. Exemplarily, the first direction X may be a row direction of the array substrate 100, and the second direction Y may be a column direction of the array substrate 100.

[0084] In some specific examples, the first positive power supply voltage signal line VDD may extend in the same direction as the second positive power supply voltage signal line PVDD, such as both extend in the first direction X, or both extend in the second direction Y.

[0085] In some specific examples, the array substrate 100 may specifically include a plurality of first positive power supply voltage signal lines VDD extending along the first direction X and arranged in sequence along the second direction Y. The array substrate 100 may specifically include a plurality of second positive power supply voltage signal lines PVDD extending along the second direction Y and arranged in sequence along the first direction X. The first positive power supply voltage signal line VDD and the second positive power supply voltage signal line PVDD may both output power supply voltage signals of forward voltage values. The voltage values ​​of the power supply voltage signals output by the first positive power supply voltage signal line VDD and the second positive power supply voltage signal line PVDD may be the same or different, and this is not limited in the embodiments of the present application.

[0086] A plurality of pixel driving circuits 10 may be arranged in an array along a first direction X and a second direction Y. The pixel driving circuits 10 may be electrically connected to a first positive power supply voltage signal line VDD and a second positive power supply voltage signal line PVDD, respectively, and the pixel driving circuit 10 may be used to operate under the voltage signal provided by the first positive power supply voltage signal line VDD and the second positive power supply voltage signal line PVDD. In some specific examples, pixel driving circuits 10 in different rows may be connected to different first positive power supply voltage signal lines VDD, and pixel driving circuits 10 in the same row may be electrically connected to the same first positive power supply voltage signal line VDD. Pixel driving circuits 10 in different columns may be connected to different second positive power supply voltage signal lines PVDD, and pixel driving circuits 10 in the same column may be electrically connected to the same second positive power supply voltage signal line PVDD. Of course, pixel driving circuits 10 in different rows (such as adjacent rows) may also be electrically connected to the same first positive power supply voltage signal line VDD.

[0087] Continue to see Fig.10 , the pixel driving circuit 10 may include a first transistor T1 and a first storage capacitor C1. The gate of the first transistor T1 is electrically connected to the first node N1, and the first transistor T1 may be used to provide a driving current for the light emitting element. The first plate of the first storage capacitor C1 may be electrically connected to the first node N1, and the second plate of the first storage capacitor C1 may be electrically connected to the first electrode of the light emitting element through the first connection portion L1.

[0088] Before the light-emitting stage, the threshold voltage Vth of the first transistor T1 can be compensated in advance. In the light-emitting stage, the first storage capacitor C1 responds to the potential change of the first electrode of the light-emitting element D, and adjusts the potential of the gate of the first transistor T1 through its own coupling effect, so that the potential change trend of the first electrode of the light-emitting element D is consistent with the potential change trend of the gate of the first transistor T1. Since the second electrode of the first transistor T1 is connected to the first electrode of the light-emitting element D in the light-emitting stage, the change trend of the potential of the gate of the first transistor T1 can be consistent with the change trend of the potential of the second electrode of the first transistor T1 through the adjustment of the first storage capacitor C1, so that the threshold voltage Vth can be maintained within the voltage difference between the potential of the gate of the first transistor T1 and the potential of the second electrode of the first transistor T1, thereby eliminating the influence of the threshold voltage Vth on the driving current of the pixel driving circuit 10, improving the Mura phenomenon of the display panel, and improving the display uniformity.

[0089] Continue to see Fig.10According to some embodiments of the present application, optionally, the array substrate 100 may further include a first scan signal line S1, a second scan signal line S2, and a data signal line data. The first scan signal line S1 and the second scan signal line S2 may both extend along the first direction X, and the data signal line data may extend along the second direction Y. In some specific examples, the array substrate 100 may specifically include a plurality of first scan signal lines S1 extending along the first direction X and arranged in sequence along the second direction Y, a plurality of second scan signal lines S2 extending along the first direction X and arranged in sequence along the second direction Y, and a plurality of data signal lines data extending along the second direction Y and arranged in sequence along the first direction X. The multi-row pixel driving circuit 10 may be electrically connected to the plurality of first scan signal lines S1 in one-to-one correspondence. The multi-row pixel driving circuit 10 may be electrically connected to the plurality of second scan signal lines S2 in one-to-one correspondence. The multi-column pixel driving circuit 10 may be electrically connected to the plurality of data signal lines data in one-to-one correspondence.

[0090] The pixel driving circuit 10 may further include a second transistor T2 and a third transistor T3. The gate of the second transistor T2 is electrically connected to the first scanning signal line S1, the first electrode of the second transistor T2 is electrically connected to the data signal line data, and the second electrode of the second transistor T2 is electrically connected to the first electrode of the first transistor T1. The gate of the third transistor T3 is electrically connected to the second scanning signal line S2, the first electrode of the third transistor T3 is electrically connected to the first node N1, and the second electrode of the third transistor T3 is electrically connected to the second electrode of the first transistor T1.

[0091] In the threshold compensation stage, the second transistor T2 can be turned on in response to the on-level of the first scan signal line S1, and the data signal of the data signal line data is written into the first electrode of the first transistor T1. The first transistor T1 is turned on in response to the on-level of the first node N1, and the third transistor T3 is turned on in response to the on-level of the second scan signal line S2. The data signal is written into the first node N1 through the turned-on first transistor T1 and the third transistor T3, so as to realize the data signal writing and the threshold voltage compensation of the first transistor T1.

[0092] Continue to see Fig.10 According to some embodiments of the present application, the array substrate 100 may further include a light emitting control signal line EM. The light emitting control signal line EM may extend along the first direction X. In some specific examples, the array substrate 100 may include a plurality of light emitting control signal lines EM extending along the first direction X and sequentially arranged along the second direction Y. The plurality of rows of pixel driving circuits 10 may be electrically connected to the plurality of light emitting control signal lines EM in a one-to-one correspondence.

[0093] Fig.10The schematic diagram shows a part of the pixel driving circuits 10 in the i-th row, and the light emitting control signal lines EM connected to the pixel driving circuits 10 in the i-th row. i , the first scanning signal line S1 connected to the pixel driving circuit 10 in the i-th row i , i is a positive integer. Along the second direction Y, the light emitting control signal line EM i The first transistor T1 in the pixel driving circuit 10 of the i-th row may be located away from the first scanning signal line S1. i and is located between the first transistor T1 and the third transistor T3 in the pixel driving circuit 10 of the i-th row.

[0094] The array substrate 100 may further include a second connection portion L2 and a third connection portion L3. At least part of the wiring in the second connection portion L2 extends along the second direction Y, and at least part of the wiring in the third connection portion L3 extends along the second direction Y. The first electrode of the third transistor T3 may be electrically connected to the first node N1 through the second connection portion L2, and the second electrode of the third transistor T3 may be electrically connected to the second electrode ( Fig.10 A third node N3 in is electrically connected.

[0095] Along the thickness direction of the array substrate, the second connection portion L2 may partially overlap with the light emitting control signal line EM, and the third connection portion L3 may partially overlap with the light emitting control signal line EM.

[0096] like Fig.10 As shown, Fig.10 The second scanning signal line S2 corresponding to the pixel driving circuit 10 in the i-th row is schematically shown. i , the second scanning signal line S2 connected to the pixel driving circuit 10 in the i-1th row i-1 , a first positive power supply voltage signal line VDD connected to the pixel driving circuit 10 in the i-th row i Along the second direction Y, the second scanning signal line S2 i Located on the light emission control signal line EM i The i-1 second scanning signal line S2 is located on a side away from the first transistor T1 in the pixel driving circuit 10 of the i-th row. i-1 Located on the first scanning signal line S1 i The gate of the third transistor T3 may be connected to the second scanning signal line S2. i In some examples, the third transistor T3 may be a dual-gate transistor, and the first gate and the second gate of the third transistor T3 in the i-th row pixel driving circuit 10 may be electrically connected to the second scanning signal line S2. i Electrical connection.

[0097] The pixel driving circuit 10 may further include a fourth transistor T4, the gate of the fourth transistor T4 in the pixel driving circuit 10 of the i-th row is connected to the second scanning signal line S2. i-1 The first electrode of the fourth transistor T4 is electrically connected to the first positive power supply voltage signal line VDD i For the pixel driving circuit 10 of the i-th row, the fourth transistor T4 and the first node N1 can be located in the second direction Y, away from the light emitting control signal line EM of the first transistor T1. i side.

[0098] The pixel driving circuit 10 may further include a fifth transistor T5 and a sixth transistor T6. The gate of the fifth transistor T5 in the pixel driving circuit 10 of the i-th row may be connected to the light emission control signal line EM i The first electrode of the fifth transistor T5 in the pixel driving circuit 10 of the i-th row is electrically connected to the second positive power supply voltage signal line PVDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The gate electrode of the sixth transistor T6 in the pixel driving circuit 10 of the i-th row is electrically connected to the light emitting control signal line EM i The first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4.

[0099] like Fig.10 As shown, along the second direction Y, the third transistor T3 in the pixel driving circuit 10 of the i-th row is arranged so that the first transistor T1 in the pixel driving circuit 10 of the i-th row is away from the first scanning signal line S1. i On one side, the gate of the third transistor T3 can be connected to the second scanning signal line S2. i On the other hand, there is enough space to set the third transistor T3, which is convenient for wiring design. In addition, since the first node N1 is located at the first transistor T1 and is far away from the light emitting control signal line EM i Therefore, by providing the second connection part L2 and the third connection part L3, the third transistor T3 can be electrically connected to the first node N1 and the third node N3, thereby completing the threshold voltage compensation of the first transistor T1.

[0100] Continue to see Fig.10 According to some embodiments of the present application, optionally, the array substrate 100 may further include a second initialization signal line V2. The second initialization signal line V2 may extend along the first direction X. In some specific examples, the array substrate 100 may specifically include a plurality of second initialization signal lines V2 extending along the first direction X and sequentially arranged along the second direction Y. The multiple rows of pixel driving circuits 10 may be electrically connected to the plurality of second initialization signal lines V2 in a one-to-one correspondence. Fig.10 The schematic diagram shows the second initialization signal line V2 correspondingly connected to the pixel driving circuit 10 in the i-th row. i Along the second direction Y, the second initialization signal line V2 i Can be located on the light emission control signal line EM i The second scanning signal line S2 i between.

[0101] The pixel driving circuit 10 may further include a seventh transistor T7. The gate of the seventh transistor T7 in the pixel driving circuit 10 of the i-th row may be connected to the second scanning signal line S2. i The first electrode of the seventh transistor T7 in the pixel driving circuit 10 of the i-th row is electrically connected to the second initialization signal line V2 i The second electrode of the seventh transistor T7 may be electrically connected to the fourth node N4.

[0102] Along the second direction Y, the first positive power supply voltage signal line VDD connected to the pixel driving circuit 10 in the i+1th row i+1 Can be located on the light emission control signal line EM i The second scanning signal line S2 i The second initialization signal line V2 i Can be located on the second scan signal line S2 i Away from the first positive power supply voltage signal line VDD i+1 side.

[0103] Along the thickness direction of the array substrate, the first semiconductor portion B1 where the active region of the third transistor T3 in the pixel driving circuit 10 of the i-th row is located can be connected to the second initialization signal line V2 i and / or the first positive power supply voltage signal line VDD i+1 The overlap forms a second storage capacitor C2.

[0104] As mentioned above, the third transistor T3 may be a dual-gate transistor, and a node between the first gate and the second gate of the dual-gate transistor is the fifth node N5.

[0105] Thus, by providing the second storage capacitor C2, the function of storing charges in the second storage capacitor C2 can be utilized so that the charges of the fifth node N5 are stored in the second storage capacitor C2. i When the signal on the fifth node N5 is switched, the charge of the fifth node N5 can be prevented from being injected into the first node N1, so that the potential of the gate of the first transistor T1 can be kept stable, thereby improving display uniformity.

[0106] Fig.11 For along Fig.10 A schematic cross-sectional view of the A1-A2 direction. Fig.11 As shown, according to some embodiments of the present application, optionally, along the thickness direction Z of the array substrate, the array substrate 100 may include a substrate 01, a semiconductor layer 02, a first metal layer M1, a second metal layer M2 and a third metal layer M3, and an insulating layer sandwiched between any adjacent metal layers.

[0107] Combination Fig.10 and Fig.11 As shown, in some embodiments, the active area of ​​the third transistor T3 can be located in the semiconductor layer 02, the light emitting control signal line EM can be located in the first metal layer M1, the second electrode of the first storage capacitor C1 can be located in the second metal layer M2, and the second connection portion L2 and the third connection portion L3 can both be located in the third metal layer M3. The first end of the second connection portion L2 can be electrically connected to the semiconductor layer 02 through the third via h3 to achieve electrical connection between the first end of the second connection portion L2 and the first node N1, and the second end of the second connection portion L2 can be electrically connected to the first electrode (source region or drain region) of the third transistor T3 located in the semiconductor layer 02 through the fourth via h4. The first end of the third connection portion L3 can be electrically connected to the second electrode of the first transistor T1 located in the semiconductor layer 02 through the fifth via h5, and the second end of the third connection portion L3 can be electrically connected to the second electrode of the third transistor T3 located in the semiconductor layer 02 through the sixth via h6.

[0108] It should be noted that the above film layer structure is only for illustration, and the array substrate 100 is not limited to the above three metal layers, but may also include a greater number of metal layers. Fig.11 As shown, along the thickness direction Z of the array substrate, the array substrate 100 may also include a fourth metal layer M4 located on the side of the third metal layer M3 away from the second metal layer M2. The data signal line data may be located in the fourth metal layer M4. It should be noted that the second positive power supply voltage signal line PVDD and the data signal line data may be located in the same film layer or in different film layers. For example, the second positive power supply voltage signal line PVDD may be located in the third metal layer M3, or in the fourth metal layer M4 or other metal layers, which is not limited in the embodiments of the present application. In addition, the light-emitting control signal line EM may also be located in other metal layers other than the first metal layer M1, the second electrode plate of the first storage capacitor C1 may be located in other metal layers other than the second metal layer M2, and the second connection portion L2 and the third connection portion L3 may be located in other metal layers other than the third metal layer M3, which is not limited in the embodiments of the present application.

[0109] Continue to see Fig.10According to some embodiments of the present application, the array substrate 100 may further include a first subdivision F, which may be electrically connected to the first node N1. The first subdivision F may be located in the semiconductor layer 02, and the first subdivision F may be a subdivision where the active region of the fourth transistor T4 is located. Along the thickness direction of the array substrate, the second positive power supply voltage signal line PVDD may overlap with the first subdivision F to form a third storage capacitor C3.

[0110] In this way, since one of the plates of the third storage capacitor C3 is the second positive power supply voltage signal line PVDD, and the potential of the second positive power supply voltage signal line PVDD is a constant potential and is not easy to change, the formed third storage capacitor C3 can better maintain the potential of the first node N1 and ensure the stability of the potential of the first node N1.

[0111] Continue to see Fig.10 According to some embodiments of the present application, optionally, the second plate of the first storage capacitor C1 and the first electrode of the light-emitting element may be located in different film layers.

[0112] The second electrode of the first storage capacitor C1 can be electrically connected to the first electrode (not shown) of the light-emitting element through the first connection portion L1 and the first via h1, and the first connection portion L1 and the second electrode of the first storage capacitor C1 can be located in the same film layer. For example, the first electrode of the first storage capacitor C1 can be located in the first metal layer M1, and the first connection portion L1 and the second electrode of the first storage capacitor C1 can be located in the second metal layer M2.

[0113] In this way, the first connection portion L1 is disposed on the same layer as the second electrode plate of the first storage capacitor C1 , which can avoid additional drilling to provide a crossover line, thereby saving wiring space.

[0114] It should be noted that, in other embodiments, the second electrode of the first storage capacitor C1 may also be reused as the first electrode of the light emitting element.

[0115] Fig.12 Another local layout of the array substrate provided in an embodiment of the present application. Fig.13 For along Fig.12 A cross-sectional diagram of the B1-B2 direction in FIG. Fig.12 and Fig.13 As shown, according to some embodiments of the present application, optionally, the first connection portion L1 and the second electrode plate of the first storage capacitor C1 can be located in different film layers. The second electrode plate of the first storage capacitor C1 can be connected to the first end of the first connection portion L1 through the second via hole h2, and the second end of the first connection portion L2 can be connected to the first end of the first storage capacitor C1 through the first via hole ( Fig.12The first connection portion L1 is electrically connected to the first electrode of the light-emitting element (not shown). Along the thickness direction of the array substrate, the first connection portion L1 may overlap with the light-emitting control signal line EM, and the film layer where the first connection portion L1 is located may be located on the side of the film layer where the second electrode plate of the first storage capacitor C1 is located away from the film layer where the light-emitting control signal line EM is located. That is, along the thickness direction Z of the array substrate, the distance between the first connection portion L1 and the light-emitting control signal line EM is greater than the distance between the second electrode plate of the first storage capacitor C1 and the light-emitting control signal line EM.

[0116] The advantage of such a configuration is that the first connection portion L1 may overlap with the light-emitting control signal line EM to form a coupling capacitor, which may affect the potential of the fourth node N4. By arranging the first connection portion L1 on the side of the film layer where the second electrode plate of the first storage capacitor C1 is located away from the film layer where the light-emitting control signal line EM is located, the distance between the first connection portion L1 and the light-emitting control signal line EM can be increased, thereby reducing the coupling capacitor between the first connection portion L1 and the light-emitting control signal line EM, and reducing the influence on the potential of the fourth node N4.

[0117] Fig.14 A structural schematic diagram of a first connecting portion and a light emitting control signal line in an array substrate provided in an embodiment of the present application. Fig.14 As shown, according to some embodiments of the present application, optionally, the first connection portion L1 may include a first sub-connection portion L11 and a second sub-connection portion L12. Along the thickness direction of the array substrate, the first sub-connection portion L11 may partially overlap with the light emitting control signal line EM, and the second sub-connection portion L12 does not overlap with the light emitting control signal line EM.

[0118] The width w1 of the first sub-connection portion L11 may be smaller than the width w2 of the second sub-connection portion L12 , and the width is the minimum distance along the first direction X.

[0119] Thus, the portion of the first connection portion L1 overlapping the light emitting control signal line EM is narrowed to further reduce the coupling capacitance between the first connection portion L1 and the light emitting control signal line EM and reduce the influence on the potential of the fourth node N4.

[0120] Based on the pixel driving circuit 10 and array substrate 100 provided in the above embodiments, the present application also provides a display device, including the pixel driving circuit 10 or array substrate 100 provided in the present application. Fig.15 , Fig.15 A schematic diagram of the structure of a display device provided in an embodiment of the present application. Fig.15 The provided display device 1000 includes the pixel driving circuit 10 or the array substrate 100 provided in any one of the above embodiments of the present application. Fig.15In the embodiment, a mobile phone is used as an example to illustrate the display device 1000. It can be understood that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, a car display device, or other display devices with display functions, and the present application does not impose specific restrictions on this. The display device provided in the embodiment of the present application has the beneficial effects of the pixel driving circuit 10 or the array substrate 100 provided in the embodiment of the present application. For details, reference can be made to the specific description of the pixel driving circuit 10 or the array substrate 100 in the above embodiments, and this embodiment will not be repeated here.

[0121] It should be understood that the specific structures of the circuits and the cross-sectional structures of the array substrates provided in the drawings of the embodiments of the present application are merely examples and are not intended to limit the present application. In addition, the above embodiments provided in the present application may be combined with each other if there is no contradiction.

[0122] It should be clear that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. According to the embodiments described above in this application, these embodiments do not describe all the details in detail, nor do they limit the application to only the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the application, so that technicians in the relevant technical field can make good use of the application and the modified use based on the application. The application is only limited by the claims and their full scope and equivalents.

[0123] Those skilled in the art should understand that the above embodiments are exemplary rather than restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Based on the study of the drawings, the specification and the claims, those skilled in the art should be able to understand and implement other variations of the disclosed embodiments. In the claims, the term "comprising" does not exclude other structures; the quantity involves "one" but does not exclude multiple; the terms "first" and "second" are used to indicate names rather than to indicate any specific order. Any figure marks in the claims should not be understood as limiting the scope of protection. The appearance of certain technical features in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. A pixel driving circuit, characterized in that: include: A driving module, used for providing a driving current to the light emitting element; A data writing module, wherein a control end of the data writing module is electrically connected to the first scanning signal end, a first end of the data writing module is electrically connected to the data signal end, and a second end of the data writing module is electrically connected to the first end of the driving module; A threshold compensation module, wherein a control end of the threshold compensation module is electrically connected to the second scanning signal end, a first end of the threshold compensation module is electrically connected to the control end of the driving module, and a second end of the threshold compensation module is electrically connected to the second end of the driving module; a first storage module, wherein a first end of the first storage module is electrically connected to a control end of the driving module, and a second end of the first storage module is electrically connected to a first electrode of the light-emitting element; In the threshold compensation stage, the data writing module is turned on in response to the on-level provided by the first scanning signal terminal, and the threshold compensation module is turned on in response to the on-level provided by the second scanning signal terminal; In the light emitting stage, the first storage module adjusts the potential of the control terminal of the driving module in response to the potential change of the first electrode of the light emitting element.

2. The pixel driving circuit according to claim 1, characterized in that: The first storage module comprises a first storage capacitor, a first plate of the first storage capacitor is electrically connected to the control end of the driving module, and a second plate of the first storage capacitor is electrically connected to the first electrode of the light-emitting element; In the light emitting stage, the first storage capacitor adjusts the potential of the control terminal of the driving module in response to the potential change of the first electrode of the light emitting element.

3. The pixel driving circuit according to claim 1, characterized in that: The pixel driving circuit further includes: a first reset module, wherein a control end of the first reset module is electrically connected to the third scan signal end, a first end of the first reset module is electrically connected to the first initialization signal end, and a second end of the first reset module is electrically connected to the control end of the driving module; In a first initialization phase before the threshold compensation phase, the first reset module is turned on in response to a turn-on level provided by the third scan signal terminal.

4. The pixel driving circuit according to claim 3, characterized in that: The pixel driving circuit further includes: a second reset module, wherein a control end of the second reset module is electrically connected to the fourth scan signal end, a first end of the second reset module is electrically connected to the second initialization signal end, and a second end of the second reset module is electrically connected to the first electrode of the light emitting element; A second initialization phase is further included between the first initialization phase and the threshold compensation phase. In the second initialization phase, the first reset module is turned on in response to the turn-on level provided by the third scanning signal terminal; In the second initialization stage, the second reset module is turned on in response to the turn-on level provided by the fourth scan signal terminal.

5. The pixel driving circuit according to claim 4, characterized in that: In the threshold compensation stage, the second reset module is turned on in response to the turn-on level provided by the fourth scan signal terminal.

6. The pixel driving circuit according to claim 4, characterized in that: The fourth scanning signal terminal multiplexes the second scanning signal terminal; In the second initialization stage, the threshold compensation module is turned on in response to the turn-on level provided by the second scanning signal terminal.

7. The pixel driving circuit according to claim 1, characterized in that: The pixel driving circuit further includes a first reset module, a first light emitting control module, a second light emitting control module and a second reset module; The driving module includes a first transistor, the data writing module includes a second transistor, the threshold compensation module includes a third transistor, the first reset module includes a fourth transistor, the first light emitting control module includes a fifth transistor, the second light emitting control module includes a sixth transistor, the second reset module includes a seventh transistor, and the first storage module includes a first storage capacitor; The gate of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the third node; The first electrode of the light emitting element is electrically connected to the fourth node, and the second electrode of the light emitting element is electrically connected to the second power supply voltage signal terminal; The gate of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the data signal terminal, and the second electrode of the second transistor is electrically connected to the second node; The gate of the third transistor is electrically connected to the second scan signal terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the third node; The gate of the fourth transistor is electrically connected to the third scan signal terminal, the first electrode of the fourth transistor is electrically connected to the first initialization signal terminal, and the second electrode of the fourth transistor is electrically connected to the first node; The gate of the fifth transistor is electrically connected to the light emitting control signal terminal, the first electrode of the fifth transistor is electrically connected to the second positive power supply voltage signal terminal, and the second electrode of the fifth transistor is electrically connected to the second node; The gate of the sixth transistor is electrically connected to the light emitting control signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node; The gate of the seventh transistor is electrically connected to the fourth scan signal terminal, the first electrode of the seventh transistor is electrically connected to the second initialization signal terminal, and the second electrode of the seventh transistor is electrically connected to the fourth node; The first plate of the first storage capacitor is electrically connected to the first node, and the second plate of the first storage capacitor is electrically connected to the fourth node.

8. The pixel driving circuit according to claim 7, characterized in that: The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are all N-type transistors.

9. The pixel driving circuit according to claim 1, characterized in that: The pixel driving circuit further includes: A bias voltage compensation module, wherein a control end of the bias voltage compensation module is electrically connected to the fifth scanning signal end, a first end of the bias voltage compensation module is electrically connected to the bias voltage signal end, and a second end of the bias voltage compensation module is electrically connected to the first end or the second end of the driving module; Before the light-emitting stage, the bias voltage compensation module is used to be turned on in response to the on-level provided by the fifth scanning signal terminal, and transmit the bias voltage signal of the bias voltage signal terminal to the first terminal or the second terminal of the driving module.

10. An array substrate, characterized in that: include: A first positive power supply voltage signal line extending along a first direction; a second positive power supply voltage signal line extending along a second direction, wherein the first direction intersects the second direction; a plurality of pixel driving circuits, the pixel driving circuits being arranged in an array along the first direction and the second direction, the pixel driving circuits being electrically connected to the first positive power supply voltage signal line and the second positive power supply voltage signal line, respectively; The pixel driving circuit comprises: a first transistor, wherein a gate of the first transistor is electrically connected to the first node, and the first transistor is used to provide a driving current for the light emitting element; A first storage capacitor, wherein a first plate of the first storage capacitor is electrically connected to the first node, and a second plate of the first storage capacitor is electrically connected to the first electrode of the light-emitting element through a first connecting portion.

11. The array substrate according to claim 10, characterized in that: The array substrate further includes: a first scanning signal line extending along the first direction; A second scanning signal line extending along the first direction; a data signal line extending along the second direction; The pixel driving circuit further includes: a second transistor, wherein a gate of the second transistor is electrically connected to the first scanning signal line, a first electrode of the second transistor is electrically connected to the data signal line, and a second electrode of the second transistor is electrically connected to a first electrode of the first transistor; A third transistor, wherein a gate of the third transistor is electrically connected to the second scanning signal line, a first electrode of the third transistor is electrically connected to the first node, and a second electrode of the third transistor is electrically connected to the second electrode of the first transistor.

12. The array substrate according to claim 11, characterized in that: The array substrate further includes: a light emitting control signal line extending along the first direction, wherein along the second direction, the light emitting control signal line is located on a side of the first transistor away from the first scanning signal line and is located between the first transistor and the third transistor in the corresponding pixel driving circuit; A second connecting portion, wherein at least part of the wiring in the second connecting portion extends along the second direction; A third connection portion, wherein at least part of the wiring in the third connection portion extends along the second direction; wherein the first electrode of the third transistor is electrically connected to the first node through the second connection portion, and the second electrode of the third transistor is electrically connected to the second electrode of the first transistor through the third connection portion; Along the thickness direction of the array substrate, the second connection portion partially overlaps with the light emitting control signal line, and the third connection portion partially overlaps with the light emitting control signal line.

13. The array substrate according to claim 12, characterized in that: The array substrate further includes: a second initialization signal line extending along the first direction; Along the second direction, the first positive power supply voltage signal line is located between the light emitting control signal line and the second scanning signal line, and the second initialization signal line is located on a side of the second scanning signal line away from the first positive power supply voltage signal line; Along the thickness direction of the array substrate, the first semiconductor portion where the active region of the third transistor is located overlaps with the second initialization signal line and / or the first positive power supply voltage signal line to form a second storage capacitor.

14. The array substrate according to claim 12, characterized in that: The array substrate comprises a substrate, a semiconductor layer, a first metal layer, a second metal layer, a third metal layer and an insulating layer sandwiched between any adjacent metal layers; The active region of the third transistor is located in the semiconductor layer, the light emitting control signal line is located in the first metal layer, the second electrode of the storage capacitor is located in the second metal layer, and the second connecting portion and the third connecting portion are both located in the third metal layer.

15. The array substrate according to claim 10, characterized in that: Also included is a first subdivision electrically connected to the first node; Along the thickness direction of the array substrate, the second positive power supply voltage signal line overlaps with the first section to form a third storage capacitor.

16. The array substrate according to claim 10, characterized in that: The second electrode plate of the first storage capacitor and the first electrode of the light-emitting element are located in different film layers; The second electrode plate of the first storage capacitor is electrically connected to the first electrode of the light-emitting element through a first connecting portion and a first via hole, and the first connecting portion and the second electrode plate of the first storage capacitor are located in the same film layer.

17. The array substrate according to claim 11, characterized in that: The array substrate further includes: a light emitting control signal line extending along the first direction, wherein along the second direction, the light emitting control signal line is located on a side of the first transistor away from the first scanning signal line and is located between the first transistor and the third transistor in the corresponding pixel driving circuit; The first connection portion and the second electrode plate of the first storage capacitor C1 are located in different film layers, the second electrode plate of the first storage capacitor C1 is connected to the first end of the first connection portion through a second via hole, and the second end of the first connection portion is electrically connected to the first electrode of the light-emitting element through a first via hole; Along the thickness direction of the array substrate, the first connection portion partially overlaps the light control signal line, and the film layer where the first connection portion is located is located on a side of the film layer where the second electrode plate of the first storage capacitor C1 is located away from the film layer where the light control signal line is located.

18. The array substrate according to claim 17, characterized in that: The first connection portion includes a first sub-connection portion and a second sub-connection portion, and along the thickness direction of the array substrate, the first sub-connection portion overlaps with the light-emitting control signal line, and the second sub-connection portion does not overlap with the light-emitting control signal line; The width of the first sub-connection portion is smaller than the width of the second sub-connection portion, and the width is the minimum distance along the first direction.

19. A display device, characterized in that: The invention comprises a pixel driving circuit as claimed in any one of claims 1 to 9 or an array substrate as claimed in any one of claims 10 to 18.

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