Digital pulse grayscale display method, device, medium and equipment based on frequency doubling group

Abstract

The present application provides a digital pulse grayscale display method, device, medium and equipment based on a frequency multiplication group, including: setting the frequency multiplication number; grouping the set number of frequency multiplications, and dividing several adjacent frequency multiplications that achieve the same grayscale into the same frequency multiplication group to reduce the frequency and amplitude of the power load change between the frequency multiplication groups that changes inversely with the number of frequency multiplication groups. The present invention increases the number of frequency multiplication groups in each group by grouping the frequency multiplications, thereby reducing the frequency of the power load change between the frequency multiplication groups that changes inversely with the frequency multiplication groups, thereby reducing the vibration frequency of the chip capacitor, and thus reducing the noise of the display screen; in addition, by treating the points in the same column on adjacent rows in the same frequency multiplication group as one point, the visual refresh rate of the low grayscale / medium grayscale is effectively improved.

Description

Technical Field

[0001] The present application relates to the technical field of LED display screens, and in particular to a method, device, medium and equipment for displaying digital pulse grayscale based on a frequency doubling group. Background Art

[0002] The digital pulse grayscale implementation method uses the visual persistence effect of the human eye to achieve grayscale changes by controlling the length of time the light-emitting diode is lit each time and the number of times it is lit within a frame. Taking the 13-bit grayscale value as an example, d13 represents the highest bit of the grayscale value, that is, the value of the 13th bit, d12 represents the 12th bit of the grayscale value, and so on. D1 represents the lowest bit of the grayscale value, that is, the value of the 1st bit.

[0003] Taking the dynamic scanning method of 30 scans and the refresh rate of 1920Hz to achieve a display screen with 13 bits of grayscale as an example, the existing technical solution is to divide one frame display time (1 / 60 second) into 32 parts (called 32 times the frequency, the frequency multiplication number = 32), and light up 30 adjacent rows of light-emitting diodes in each time, and realize two grayscales in this time, and the grayscales realized in 30 rows are the same. One frame display time displays a total of 13 bits of grayscale data, such as Figure 1 As shown in the table, two gray levels are achieved with each frequency doubling.

[0004] When D13=1, the total duration of lighting up the LED in one frame (71.424us) = the duration of lighting up the LED once (4.464us) * the number of lighting times in one frame (16 times = the sum of the 13 grayscale values ​​in Table 1);

[0005] When D12=1, the total duration of lighting up the LED in one frame (35.712us) = the duration of lighting up the LED once (4.464us) * the number of lighting times in one frame (8 times = the sum of the 12 grayscale values ​​in Table 1);

[0006] …

[0007] When D1=1, the total duration of lighting the LED in one frame (16ns) = the duration of lighting the LED once (16ns) * the number of lighting times in one frame (1 time = the sum of the grayscale values ​​in Table 1).

[0008] The existing grayscale implementation scheme shows that the grayscale bits implemented in each frequency doubling are the same, which means that the duration of lighting the LED is fixed and the power supply load remains unchanged. However, the duration of lighting the LED is different between frequency doublings, and the power supply load varies greatly. The power supply load change will cause the chip capacitor to vibrate, and then emit noise. Therefore, in practice, it can be clearly heard that the circuit board with chip capacitors on the LED display will make a sound. Summary of the invention

[0009] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a digital pulse grayscale display method, device, medium and equipment based on a frequency doubling group, which is used to solve the problem of display screen noise caused by high load change frequency in the prior art.

[0010] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides a digital pulse grayscale display method based on a multiplication group, including: setting the number of multiplications; grouping the set number of multiplications, and dividing several adjacent multiplications that achieve the same grayscale into the same multiplication group, so as to reduce the frequency of power supply load changes between multiplication groups, which changes in the opposite direction to the number of multiplication groups.

[0011] In some embodiments of the first aspect of the present application, the number of subframes required to divide a frame time is calculated based on the refresh rate and the frame time; the number of subframes is a multiple number.

[0012] In some embodiments of the first aspect of the present application, after grouping, each frequency multiplication group includes a plurality of frequencies; and the power load change frequency between the frequency multiplication groups is correspondingly reduced to a plurality of times.

[0013] In some embodiments of the first aspect of the present application, it also includes: calculating the power load change frequency within the multiplication group based on the refresh rate, the sweep number and the multiplication number; wherein the power load change frequency within the multiplication group changes positively with the refresh rate and the sweep number, and changes negatively with the multiplication number.

[0014] In some embodiments of the first aspect of the present application, the method also includes: treating points in the same column on adjacent rows in the same frequency multiplication group as one point, so that the low-level grayscale and / or the middle grayscale experience multiple frequencies within the frequency multiplication group at different time points within a frame to improve the refresh rate of the low-level grayscale and / or the middle grayscale.

[0015] In some embodiments of the first aspect of the present application, the refresh rate of the low grayscale and / or the middle grayscale is increased several times, and the multiple is the multiplication number within a multiplication group; wherein the increased refresh rate does not exceed the refresh rate of the highest grayscale.

[0016] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides a digital pulse grayscale display device based on a frequency multiplication group, including: a frequency multiplication setting module for setting the number of frequency multiplications; a grouping module for grouping the set number of frequency multiplications, and dividing several adjacent frequency multiplications that achieve the same grayscale into the same frequency multiplication group, so as to reduce the frequency of power supply load changes between frequency multiplication groups, which changes in the opposite direction to the number of frequency multiplication groups.

[0017] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the digital pulse grayscale display method based on the frequency multiplication group is implemented.

[0018] To achieve the above-mentioned purpose and other related purposes, the fourth aspect of the present application provides a computer device, including: a processor and a memory; the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that the device executes the digital pulse grayscale display method based on the frequency multiplication group.

[0019] As described above, the digital pulse grayscale display method, device, medium and equipment based on the frequency multiplication group of the present application have the following beneficial effects: the present invention increases the number of frequency multiplication groups in each group by grouping the frequency multiplication, thereby reducing the frequency of power supply load changes between the frequency multiplication groups that change in the opposite direction, thereby reducing the vibration frequency of the chip capacitor, thereby reducing the noise of the display screen; in addition, by treating the points in the same column on adjacent rows in the same frequency multiplication group as one point, the visual refresh rate of low-level grayscale / mid-level grayscale is effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of a grayscale implementation scheme in the prior art.

[0021] Figure 2 It is a schematic diagram of a grayscale implementation scheme for the first frequency doubling within a frame in the prior art.

[0022] Figure 3 Shown is a flow chart of a digital pulse grayscale display method based on a frequency doubling group in one embodiment of the present invention.

[0023] Figure 4A It is a schematic diagram showing a grayscale implementation scheme for the first frequency doubling within a frame according to an embodiment of the present invention.

[0024] Figure 4B It is a schematic diagram showing a grayscale implementation scheme for the second frequency doubling within a frame according to an embodiment of the present invention.

[0025] Figure 5 Shown is a structural schematic diagram of a digital pulse grayscale display device based on a frequency doubling group in one embodiment of the present invention.

[0026] Figure 6 Shown is a schematic diagram of the structure of a computer device in one embodiment of the present application. DETAILED DESCRIPTION

[0027] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0028] It should be noted that in the following description, with reference to the accompanying drawings, several embodiments of the present application are described in the accompanying drawings. It should be understood that other embodiments may also be used, and mechanical composition, structure, electrical and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description should not be considered restrictive, and the scope of the embodiments of the present application is limited only by the claims of the published patents. The terms used here are only for describing specific embodiments and are not intended to limit the present application. Spatially related terms, such as "upper", "lower", "left", "right", "below", "below", "lower", "above", "upper", etc., may be used in the text to facilitate the description of the relationship between an element or feature shown in the figure and another element or feature.

[0029] In this application, unless otherwise clearly specified and limited, the terms "install", "connect", "connect", "fix", "hold" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0030] Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments described here can be implemented in an order other than that illustrated or described here. In addition, the terms "comprising" and "including" indicate the presence of the described features, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. It should be further understood that the terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition occur only when a combination of elements, functions, or operations are inherently mutually exclusive in some manner.

[0031] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the technical solution in the embodiments of the present invention is further described in detail through the following embodiments and in combination with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the invention.

[0032] The screen refresh rate is a hardware performance parameter of the display, that is, how many pictures it can refresh per second, generally expressed in physical units of Hz. Taking the currently commonly used mobile phone screen as an example, the mainstream is 1080P resolution, that is, 1080*1920 pixels, 1080 pixels per row, and 1920 pixels per column. Usually, the display is called row scan when it finishes drawing 1080 pixels in a row, and field scan when it finishes drawing all 1920 rows. The physical signal that starts scanning a row is called the horizontal synchronization signal (HSYNC), and the physical signal that starts scanning a field is called the vertical synchronization signal (VSYNC). The number of VSYNC signals that the display can draw per second is called the field frequency, which is the refresh rate of the screen. Generally speaking, a low refresh rate will cause image flickering and jittering, and image flickering and jittering will cause visual fatigue, and long-term viewing will cause eye fatigue. Therefore, the higher the refresh rate, the less damage to the eyes. At present, the common refresh rates of LED display screens are 1920Hz regular refresh and 3840Hz high refresh.

[0033] It can be seen from the existing grayscale implementation scheme that the grayscale implemented in each frequency doubling is the same, such as Figure 2The grayscale implementation scheme of the first frequency doubling within a frame is shown, which means that the duration of lighting the LED is fixed and the load of the power supply remains unchanged. Figure 1 The existing grayscale implementation scheme shown is used for explanation: the main grayscale is repeated every 4 multiples, for example, the main grayscale corresponding to the multiples 1 to 4 is 13, 12, 13, 11, and the main grayscale corresponding to the multiples 5 to 8 is also 13, 12, 13, 11. This pattern is repeated subsequently, so the number of multiples is 4. The 1st to 4th multiples are called a multiple group, the 5th to 8th multiples are also a multiple group, and so on.

[0034] However, the duration of lighting the LED is different between frequency multiples, which results in a large change in the power load. The frequency of the power load change is calculated as follows:

[0035] Power load change frequency = frame rate * multiplier = 60Hz * 32 times = 1920Hz (refresh rate).

[0036] Since the sound frequency that humans can hear is distributed in the range of 20Hz to 20Khz, the power load change frequency of 1920Hz falls within the sound frequency range that humans can hear. The power load change causes the chip capacitor to vibrate, which in turn makes a sound. Therefore, in practice, it is obvious that the circuit board with chip capacitors on the LED display makes noise.

[0037] like Figure 3 As shown, a flow chart of a digital pulse grayscale display method based on a frequency doubling group in one embodiment of the present invention is presented.

[0038] It should be noted that the digital pulse grayscale display method can be applied to a controller, and the electronic control unit is, for example, an ARM (Advanced RISC Machines) controller, an FPGA (Field Programmable Gate Array) controller, a SoC (System on Chip) controller, a DSP (Digital Signal Processing) controller, or an MCU (Microcontroller Unit) controller, etc. The digital pulse grayscale display method can also be applied to computer devices including components such as memory, storage controller, one or more processing units (CPU), peripheral interface, RF circuit, audio circuit, speaker, microphone, input / output (I / O) subsystem, display screen, other output or control devices, and external ports; the computer device includes but is not limited to personal computers such as desktop computers, laptops, tablet computers, smart phones, smart bracelets, smart watches, smart helmets, smart TVs, personal digital assistants (Personal Digital Assistant, referred to as PDA). In other embodiments, the digital pulse grayscale display method can also be applied to servers, which can be arranged on one or more physical servers according to various factors such as function and load, or can be composed of distributed or centralized server clusters.

[0039] In addition, digital pulse grayscale display is a grayscale display technology that uses pulses. It uses the visual retention phenomenon of the human eye, which refers to the phenomenon that after the image seen by the human eye disappears, the image still stays in the brain for a period of time, and the retention time is about 1 / 24 second. This is also the basis for the formation and dissemination of visual media such as animation and movies. Due to this characteristic of the human eye, the brightness of the light-emitting diode can be achieved by controlling the length and frequency of lighting the light-emitting diode to achieve this grayscale change, that is, digital pulse grayscale display technology. The effect of different pulse widths reflected on the LED is the different brightness changes of the LED. The pulse width is the length of the pulse duration. Based on the visual retention characteristics of the human eye, the human eye's perception of brightness is, to a certain extent, an integral effect. The lighting time corresponding to the low-order code is short, and the brightness felt by the human eye is small. The lighting time corresponding to the high-order code is long, and the brightness felt by the human eye is large.

[0040] In this embodiment, the digital pulse grayscale display method based on the frequency multiplication group mainly includes steps S31 and S32, and each step will be explained and illustrated in detail below. It should be noted that when facing the noise problem of a specific LED display panel, the actual solution used can flexibly select the frequency multiplication number and refresh rate to achieve optimal noise processing.

[0041] Step S31: Setting the frequency multiplication factor.

[0042] In some examples, the frequency multiplier is set by calculating the number of subframes required to divide the frame time according to the refresh rate and the frame time; the number of subframes is the frequency multiplier. For example, the refresh rate is 1920 Hz, that is, 1920 times per second, and the frame time is 1 / 60 second, so the frame time is divided into 32 subframes, and each subframe time is 1 / (60*32) seconds, which corresponds to a refresh rate of 1920 Hz. Therefore, 32 parts are called 32 times the frequency, so the frequency multiplier is 32.

[0043] Step S32: grouping a set number of multiple frequencies, and dividing several adjacent multiple frequencies that achieve the same grayscale into the same multiple frequency group, so as to reduce the frequency and amplitude of power supply load changes between multiple frequency groups that vary inversely with the number of multiple frequency groups.

[0044] In some examples, after grouping, each frequency multiplication group contains several frequencies; the power load change frequency between the frequency multiplication groups is correspondingly reduced to a multiple of one. For example, if each frequency multiplication group contains 4 frequencies after grouping, that is, the frequency multiplication number of each group is 4, since the frequency multiplication number of each group before grouping is theoretically 1, after grouping, the power load change frequency between the frequency multiplication groups, which changes inversely with the frequency multiplication group number, is reduced to 1 / 4 of the original frequency multiplication group number. The specific calculation process is as follows:

[0045] The frequency of power load change between frequency multiplication groups = refresh rate / frequency multiplication number per group = 1920Hz / 4 = 480Hz;

[0046] Therefore, compared with the 1920Hz power load change frequency between multiple frequency groups in the prior art, the power load change frequency between multiple frequency groups obtained by the present invention after grouping is reduced to 480Hz, which successfully reduces the noise, so the tone and loudness are also much smaller. It should be understood that the loudness is also reduced mainly due to the reduction in amplitude. Since the original technical solution is to switch between different multiple frequencies, it is the main grayscale (i.e. the highest grayscale, such as Figure 1 As shown in the figure, the grayscale is switched, which results in a very large change range; while the patent of the present invention adopts the switching between different frequency multiplication groups, and the secondary grayscale is switched, so the change range is correspondingly smaller.

[0047] In some examples, it is considered that the power load changes also occur within the multiplier group, and the power load change frequency between the multiplier groups changes positively with the refresh rate and the scan number, and changes negatively with the multiplier number. For the multiplier number, please refer to Figure 4A and 4B As shown, Figure 4A What is shown is the grayscale implementation scheme of the first frequency doubling within a frame. The main grayscale changes regularly, 13, 12, 13, 11, and then repeats the pattern; Figure 4BWhat is shown is the grayscale implementation scheme of the second frequency multiplication within a frame. The main grayscale changes regularly, 13, 12, 13, 11, but because the grayscale of the second frequency multiplication is 12, the main grayscale of the first row is 12, and then the pattern is repeated.

[0048] The calculation process of the power load change frequency within the frequency multiplication group is as follows:

[0049] The power load change frequency within the multiplication group = refresh rate * scan number / multiplication number = 1920Hz * 30 scans / 4 = 14.4Khz; therefore, compared with the load change frequency of 1920Hz in the prior art, the power load change frequency within the multiplication group in the present invention is also reduced, and the change amplitude is low, and the noise is obviously smaller than the existing solution.

[0050] In some examples, when the dot pitch of the LED display screen is small enough, the dots in the same column on adjacent rows in the same frequency multiplication group are regarded as one dot, so that the low grayscale and / or the middle grayscale experience multiple frequencies in the frequency multiplication group at different time points in one frame, so as to improve the refresh rate of the low grayscale and / or the middle grayscale. Specifically, the dots in the same column on four adjacent rows in the same frequency multiplication group can be regarded as one dot, so the low grayscale and / or the middle grayscale experience multiple different frequency multiplications at different time points in one frame, so the refresh rate of the low grayscale and / or the middle grayscale is actually increased by several times (for example, the multiple is the number of multiples in a frequency multiplication group). It should be understood that in the grayscale implementation technology, the refresh rate increases from low-level grayscale to high-level grayscale. For example, the refresh rate of grayscale 1 is 60Hz, the refresh rate of grayscale 2 is 60Hz, the refresh rate of grayscale 3 is 120Hz, the refresh rate of grayscale 4 is 120Hz, the refresh rate of grayscale 5 is 240Hz, and so on, until the high-level grayscale uses the highest refresh rate of 1920Hz.

[0051] Furthermore, the refresh rate of the low grayscale and / or the middle grayscale is increased by several times, the multiple being the frequency multiple in a frequency multiple group; wherein the increased refresh rate does not exceed the refresh rate of the highest grayscale. Therefore, if the refresh rate of the highest grayscale is 1920Hz, then even if the refresh rate of the low grayscale / middle grayscale is increased, the maximum will not exceed 1920Hz; and if the refresh rate of the highest grayscale is 3840Hz, then even if the refresh rate of the low grayscale / middle grayscale is increased, the maximum will not exceed 3840Hz.

[0052] For ease of understanding, the lowest bit "grayscale 1" is used as an example for explanation: the lowest bit "grayscale 1" is realized at different time points in a frame, that is, 4 different multiples, so the refresh rate of the lowest bit "grayscale 1" is actually 4 times the original, that is, 60Hz*4=240Hz. Therefore, compared with the refresh rate of 60Hz of the lowest bit "grayscale 1" in the prior art, the present invention effectively increases its refresh rate to 240Hz.

[0053] like Figure 5 , which shows a schematic diagram of the structure of a digital pulse grayscale display device based on a frequency multiplication group in an embodiment of the present invention. The digital pulse grayscale display device 500 comprises: a frequency multiplication setting module 501 and a grouping module 502.

[0054] The frequency multiplier setting module 501 is used to set the frequency multiplier. For example, the frequency multiplier setting method includes: calculating the number of subframes required to divide the frame time according to the refresh rate and the frame time; the number of subframes is the frequency multiplier. For example, the refresh rate is 1920Hz, that is, 1920 times per second, and the frame time is 1 / 60 second, so the frame time is divided into 32 subframes, and each subframe time is 1 / (60*32) seconds, which corresponds to a refresh rate of 1920Hz. Therefore, 32 parts are called 32 times the frequency, so the frequency multiplier is 32.

[0055] The grouping module 502 is used to group a set number of multiple frequencies and divide several adjacent multiple frequencies that achieve the same grayscale into the same multiple frequency group to reduce the power load change frequency between the multiple frequency groups that changes inversely with the number of multiple frequency groups.

[0056] In some examples, after grouping, each frequency multiplication group contains several frequencies; the power load change frequency between the frequency multiplication groups is correspondingly reduced to a multiple of one. For example, if each frequency multiplication group contains 4 frequencies after grouping, that is, the frequency multiplication number of each group is 4, since the frequency multiplication number of each group before grouping is theoretically 1, after grouping, the power load change frequency between the frequency multiplication groups, which changes inversely with the frequency multiplication group number, is reduced to 1 / 4 of the original frequency multiplication group number. The specific calculation process is as follows:

[0057] The frequency of power load change between frequency multiplication groups = refresh rate / frequency multiplication number per group = 1920Hz / 4 = 480Hz;

[0058] Therefore, compared with the 1920Hz power load change frequency between frequency multiplication groups in the prior art, the power load change frequency between frequency multiplication groups obtained by the present invention after grouping is reduced to 480Hz, which successfully reduces the noise, so the tone and loudness are also much smaller.

[0059] The calculation process of the power load change frequency within the frequency multiplication group is as follows:

[0060] The power load change frequency within the multiplication group = refresh rate * scan number / multiplication number = 1920Hz * 30 scans / 4 = 14.4Khz; therefore, compared with the load change frequency of 1920Hz in the prior art, the power load change frequency within the multiplication group in the present invention is also reduced, and the change amplitude is low, and the noise is obviously smaller than the existing solution.

[0061] It should be understood that the division of the various modules of the above device is only a division of logical functions. In actual implementation, they can be fully or partially integrated into one physical entity, or they can be physically separated. And these modules can all be implemented in the form of software called by processing elements; they can also be all implemented in the form of hardware; some modules can also be implemented in the form of software called by processing elements, and some modules can be implemented in the form of hardware. For example, the grouping module can be a separately established processing element, or it can be integrated in a chip of the above device. In addition, it can also be stored in the memory of the above device in the form of program code, and called and executed by a processing element of the above device. The implementation of other modules is similar. In addition, these modules can be fully or partially integrated together, or they can be implemented independently. The processing element described here can be an integrated circuit with signal processing capabilities. In the implementation process, each step of the above method or each module above can be completed by an integrated logic circuit of hardware in the processor element or instructions in the form of software.

[0062] For example, the above modules may be one or more integrated circuits configured to implement the above methods, such as one or more application specific integrated circuits (ASICs), or one or more digital signal processors (DSPs), or one or more field programmable gate arrays (FPGAs). For another example, when a module is implemented in the form of a processing element scheduling program code, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processors that can call program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0063] like Figure 6 As shown, a schematic diagram of the structure of a computer device in an embodiment of the present invention is shown. The computer device includes: a processor 61, a memory 62, and a communicator 63; the memory 62 is connected to the processor 61 and the communicator 63 through a system bus and completes communication between them, the memory 62 is used to store computer programs, the communicator 63 is used to communicate with other devices, and the processor 61 is used to run the computer program to enable the electronic terminal to execute the various steps of the digital pulse grayscale display method based on the frequency multiplication group.

[0064] The system bus mentioned above can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The system bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus. The communication interface is used to realize the communication between the database access device and other devices (such as clients, read-write libraries, and read-only libraries). The memory may include random access memory (RAM), and may also include non-volatile memory, such as at least one disk storage.

[0065] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0066] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the digital pulse grayscale display method based on the frequency multiplication group is implemented.

[0067] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to the computer program. The aforementioned computer program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other media that can store program codes.

[0068] In the embodiments provided in the present application, the computer readable and writable storage medium may include a read-only memory, a random access memory, an EEPROM, a CD-ROM or other optical disk storage device, a disk storage device or other magnetic storage device, a flash memory, a USB flash drive, a mobile hard disk, or any other medium that can be used to store a desired program code in the form of an instruction or data structure and can be accessed by a computer. In addition, any connection can be appropriately referred to as a computer-readable medium. For example, if the instruction is sent from a website, a server or other remote source using a coaxial cable, an optical fiber cable, a twisted pair, a digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves, the coaxial cable, optical fiber cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of the medium. However, it should be understood that computer readable and writable storage media and data storage media do not include connections, carriers, signals, or other temporary media, but are intended to be non-temporary, tangible storage media. Disk and disc, as used in this application, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.

[0069] In summary, the present application provides a digital pulse grayscale display method, device, medium and equipment based on a frequency multiplication group. The present invention increases the number of frequency multiplication groups in each group by grouping the frequency multiplication, thereby reducing the frequency of the power load change between the frequency multiplication groups that changes inversely, thereby reducing the vibration frequency of the chip capacitor, thereby reducing the noise of the display screen; in addition, by treating the points in the same column on adjacent rows in the same frequency multiplication group as one point, the visual refresh rate of the low grayscale / medium grayscale is effectively improved. Therefore, the present application effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0070] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A digital pulse grayscale display method based on a frequency multiplication group, characterized in that: include: Set the frequency multiple; A set number of multiples are grouped, and several adjacent multiples that achieve the same grayscale are divided into the same multiple group to reduce the frequency and amplitude of power load changes between multiple groups that vary inversely with the number of multiple groups; the number of subframes required to divide the frame time is calculated based on the refresh rate and a frame time; the number of subframes is the number of multiples; after grouping, each multiple group contains several multiples; the power load change frequency between the multiple groups is correspondingly reduced to one of several; wherein, the power load change frequency between the multiple groups = refresh rate / number of multiples per group; the power load change frequency within the multiple group is calculated based on the refresh rate, sweep number and multiple number; wherein, the power load change frequency within the multiple group varies positively with the refresh rate and sweep number, and varies inversely with the number of multiples.

2. The digital pulse grayscale display method based on the frequency doubling group according to claim 1, characterized in that: Also includes: Points in the same column and adjacent rows in the same frequency doubling group are regarded as one point, so that the low grayscale and / or the middle grayscale experience multiple frequencies in the frequency doubling group at different time points in one frame to improve the refresh rate of the low grayscale and / or the middle grayscale.

3. The digital pulse grayscale display method based on the frequency multiplication group according to claim 2, characterized in that: The refresh rate of the low grayscale and / or the middle grayscale is increased by several times, the multiple being the multiple number in a multiple group; wherein the increased refresh rate does not exceed the refresh rate of the highest grayscale.

4. A digital pulse grayscale display device based on a frequency multiplication group, characterized in that: include: The frequency multiplication setting module is used to set the frequency multiplication number; A grouping module is used to group a set number of multipliers, and divide several adjacent multipliers that achieve the same grayscale into the same multiplier group, so as to reduce the power load change frequency between multiplier groups that changes inversely with the number of multiplier groups; the number of subframes required to divide the frame time is calculated according to the refresh rate and one frame time; the number of subframes is the number of multipliers; after grouping, each multiplier group contains several multipliers; the power load change frequency between the multiplier groups is correspondingly reduced to one of several times; wherein, the power load change frequency between the multiplier groups = refresh rate / number of multipliers in each group; the power load change frequency within the multiplier group is calculated according to the refresh rate, sweep number and multiplier number; wherein, the power load change frequency within the multiplier group changes positively with the refresh rate and sweep number, and changes inversely with the number of multipliers.

5. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the digital pulse grayscale display method based on the frequency multiplication group described in any one of claims 1 to 3 is implemented.

6. A computer device, characterized in that: include: Processor and memory; The memory is used to store computer programs; The processor is used to execute the computer program stored in the memory, so that the computer device executes the digital pulse grayscale display method based on the frequency multiplication group as claimed in any one of claims 1 to 3.

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