Fuse structure, forming method and programmable memory

Abstract

Embodiments of the present application disclose a fuse structure, a formation method, and a programmable memory. The fuse structure includes: a gate structure, the gate structure being at least partially formed on an active region of a substrate; a first electrode, the first electrode being formed on the active region of the substrate and spaced apart from the gate structure; a second electrode, the second electrode being formed at least on a side of the gate structure; and an isolation structure formed between the active region and the second electrode. Embodiments of the present application help reduce conductive resistance, increase breakdown current, and reduce the difficulty of breakdown of the fuse dielectric layer.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor device technology, and more particularly to a fuse structure, a formation method, and a programmable memory. Background Art

[0002] OTP (One-Time Programmable) memories are categorized as fuse-type and antifuse-type memories. The programmable unit of an antifuse-type memory is an antifuse structure. The antifuse structure specifically consists of a fuse dielectric layer and two electrodes connected to either side of the fuse dielectric layer. When not being programmed, the voltage applied to the fuse dielectric layer is low, preventing breakdown. The antifuse structure acts as a capacitor, exhibiting a high-resistance state. During programming, increasing the voltage causes the fuse dielectric layer to break down, and the antifuse structure acts as a resistor, exhibiting a low-resistance state.

[0003] However, in order to tune the work function, the oxide layer of the gate structure in the memory is usually thicker, and the breakdown of the fuse dielectric layer is more difficult. Summary of the Invention

[0004] The embodiments of the present application provide a fuse structure, a formation method, and a programmable memory, which help to reduce conductive resistance, increase current, and reduce the difficulty of breaking down the fuse dielectric layer.

[0005] A first aspect of an embodiment of the present application provides a fuse structure, including:

[0006] a gate structure, the gate structure being at least partially formed on an active region of the substrate;

[0007] a first electrode, wherein the first electrode is formed on the active area of ​​the substrate and is spaced apart from the gate structure;

[0008] a second electrode, the second electrode being formed at least on a side surface of the gate structure;

[0009] An isolation structure is formed between the active region and the second electrode.

[0010] In some optional embodiments, the gate structure includes:

[0011] a fuse dielectric layer;

[0012] A gate material layer is formed on the fuse dielectric layer.

[0013] In some optional embodiments, the isolation structure is formed in the substrate and is adjacent to the active area;

[0014] The second electrode is formed on the isolation structure.

[0015] In some optional embodiments, the gate structure is formed on the active region and the isolation structure simultaneously.

[0016] In some optional embodiments, the fuse structure further includes an insulating structure, wherein the insulating structure is formed on the active region and is located between the first electrode and the gate structure.

[0017] In some optional embodiments, the gate material layer includes a first conductive layer and a second conductive layer, the first conductive layer and the second conductive layer are adjacent to each other in a direction parallel to the substrate, and the resistivity of the first conductive layer is less than that of the second conductive layer.

[0018] In some optional embodiments, the first conductive layer is adjacent to the second electrode.

[0019] In some optional embodiments, in a direction parallel to the substrate, the first conductive layer has a first width, the second conductive layer has a second width, and the first width is smaller than the second width.

[0020] In some optional embodiments, the fuse structure further includes:

[0021] A third conductive layer is formed between the active area of ​​the substrate and the first electrode, and the resistivity of the third conductive layer is lower than the resistivity of the first electrode.

[0022] In some optional embodiments, the fuse structure further includes:

[0023] A passivation layer is formed between the first electrode and the second electrode.

[0024] A second aspect of an embodiment of the present application provides a method for forming a fuse structure, comprising:

[0025] Providing a substrate, wherein the substrate includes an active area and an isolation structure adjacent to the active area;

[0026] forming a gate structure, wherein the gate structure is at least partially formed on the active area;

[0027] forming a first electrode, wherein the first electrode is formed on the active area and spaced apart from the gate structure;

[0028] A second electrode is formed, wherein the second electrode is at least partially formed on the isolation structure and is adjacent to a side surface of the gate structure.

[0029] In some optional embodiments, the step of forming the first electrode includes:

[0030] forming a passivation layer covering the gate structure on the substrate;

[0031] performing an etching process to form a first electrode hole in the passivation layer on the active area, wherein the first electrode hole exposes the active area;

[0032] The first electrode hole is filled with a first electrode material to form a first electrode.

[0033] In some optional embodiments, the step of forming the second electrode includes:

[0034] forming a second electrode hole in the passivation layer on the isolation structure, wherein the second electrode hole at least exposes a side surface of the gate structure;

[0035] The second electrode hole is filled with an electrode material to form the second electrode.

[0036] In some optional embodiments, before filling the second electrode hole with an electrode material, the method for forming the fuse structure further includes:

[0037] A first conductive layer is formed, wherein the first conductive layer is formed on a side of the gate structure adjacent to the first electrode, the gate structure includes a second conductive layer, the first conductive layer and the second conductive layer are adjacent in a direction parallel to the substrate, and the resistivity of the first conductive layer is less than the resistivity of the second conductive layer.

[0038] In some optional embodiments, the step of forming the first conductive layer includes:

[0039] depositing metal in the second electrode hole;

[0040] High-temperature annealing is performed to allow the polysilicon in the second conductive layer exposed in the second electrode hole to react with the metal to form a first conductive layer.

[0041] In some optional embodiments, in a direction parallel to the substrate, the first conductive layer has a first width, the second conductive layer has a second width, and the first width is smaller than the second width.

[0042] In some optional embodiments, before filling the first electrode hole with an electrode material, the method for forming the fuse structure further includes:

[0043] A third conductive layer is formed, wherein the third conductive layer is formed on a surface of the active region adjacent to the first electrode.

[0044] In some optional embodiments, the step of forming the third conductive layer includes:

[0045] depositing metal in the first electrode hole;

[0046] High-temperature annealing is performed to allow the polysilicon in the active area exposed in the first electrode hole to react with the metal to form a third conductive layer, wherein the resistivity of the third conductive layer is lower than the resistivity of the first electrode.

[0047] In some optional embodiments, the method for forming the fuse structure further includes:

[0048] An insulating structure is formed outside the gate structure.

[0049] A third aspect of the embodiments of the present application provides a programmable memory, comprising the fuse structure of any one of the embodiments of the first aspect.

[0050] The above technical solutions of the embodiments of the present application have at least the following beneficial technical effects:

[0051] The embodiment of the present application increases the contact area between the second electrode and the gate structure by changing the position connection relationship between the second electrode and the gate structure, which helps to reduce the conductive resistance, increase the current, and reduce the breakdown difficulty of the fuse dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 is a structural diagram of a fuse structure provided according to an embodiment of the present application;

[0053] Figure 2-Figure 8 This is a schematic diagram of a formation process of a fuse structure provided in an embodiment of the application;

[0054] Reference numerals:

[0055] 100. Substrate; 110. Active area; 120. Isolation structure; 130. Third conductive layer; 200. Gate structure; 210. Fuse dielectric layer; 220. Gate material layer; 221. First metal layer; 222. Second conductive layer; 223. First conductive layer; 224. Second metal layer; 300. First electrode; 400. Second electrode; 500. Insulation structure; 600. Passivation layer; 610. First electrode hole; 620. Second electrode hole. DETAILED DESCRIPTION

[0056] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the embodiments of the present application are further described in detail below in conjunction with specific implementation methods and with reference to the accompanying drawings. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the embodiments of the present application. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion in the concepts of the embodiments of the present application.

[0057] In the description of the embodiments of the present application, it should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance.

[0058] Reference Figure 1 , an embodiment of the present application provides a fuse structure, including:

[0059] a gate structure 200 , wherein the gate structure 200 is at least partially formed on the active region 110 of the substrate 100 ;

[0060] a first electrode 300 , wherein the first electrode 300 is formed on the active region 110 of the substrate 100 and is spaced apart from the gate structure 200 ;

[0061] A second electrode 400 , wherein the second electrode 400 is formed at least on a side surface of the gate structure 200 ;

[0062] The isolation structure 120 is formed between the active region 110 and the second electrode 400 .

[0063] In the fuse structure of this embodiment, the first electrode 300 , the active region 110 , the gate structure 200 , and the second electrode 400 are conductively connected in sequence from the first electrode 300 toward the second electrode 400 , forming an electrical path H. The second electrode 400 is connected to the side surface of the gate structure 200 , thereby increasing the contact area between the second electrode 400 and the gate structure 200 , thereby reducing the conductive resistance, increasing the current in the electrical path H, and making it easier to break through the fuse dielectric layer 210 in the gate structure 200 .

[0064] In an optional embodiment, the substrate 100 may be a P-type silicon substrate or an N-type silicon substrate. In this embodiment, the substrate 100 is a P-type silicon substrate.

[0065] In an optional embodiment, the substrate 100 may be a single crystal silicon substrate or a polycrystalline silicon substrate. In this embodiment, the substrate 100 is a polycrystalline silicon substrate, wherein the material of the active region 110 formed in the substrate 100 may be polycrystalline silicon.

[0066] In an optional embodiment, the material of the first electrode 300 and the second electrode 400 can be one or more materials selected from the group consisting of a tungsten (W) layer, a cobalt (Co) layer, a nickel (Ni) layer, a tantalum (Ta) layer, a tantalum nitride (TaN) layer, a titanium (Ti) layer, and a titanium nitride (TiN) layer. For example, the material of the first electrode 300 and the second electrode 400 is titanium nitride.

[0067] In an optional embodiment, in order to reduce the mutual influence between the first electrode 300 and the second electrode 400, the fuse structure further includes:

[0068] The passivation layer 600 is formed between the first electrode 300 and the second electrode 400 .

[0069] Exemplarily, the passivation layer 600 includes an insulating material having an isolation function. For example, the passivation layer 600 may be an oxide layer (BOX), and the material of the oxide layer may be silicon oxide (SiO 2 ).

[0070] In an optional embodiment, the isolation structure 120 may be an isolation structure formed on the surface of the substrate 100 , or may be a shallow trench isolation (STI) structure formed in the substrate 100 .

[0071] Illustratively, the isolation structure 120 is formed in the substrate 100 and is adjacent to the active region 110 ; the second electrode 400 is formed on the isolation structure 120 .

[0072] Exemplarily, the gate structure 200 is formed on the active region 110 and the isolation structure 120 at the same time.

[0073] In an optional embodiment, the gate structure 200 includes:

[0074] The fuse dielectric layer 210 is configured to be broken down by a programming current;

[0075] A gate material layer 220 is formed on the fuse dielectric layer 210 .

[0076] For example, the fuse dielectric layer 210 in the gate structure 200 serves as the gate dielectric layer of the gate structure 200. The material of the fuse dielectric layer 210 may be hafnium oxide (HfO2). Using HfO2 as the gate dielectric layer can reduce the thickness of the gate dielectric layer, thereby further reducing the difficulty of breakdown. In some embodiments, the equivalent thickness of HfO2 can be less than 25 angstroms. For example, the equivalent thickness of the fuse dielectric layer 210 can be 15 angstroms, 16 angstroms, 17 angstroms, 18 angstroms, 19 angstroms, or 20 angstroms.

[0077] Exemplarily, the gate material layer 220 includes a second conductive layer 222 , a first metal layer 221 and a second metal layer 224 . The first metal layer 221 is disposed between the second conductive layer 222 and the fuse dielectric layer 210 , and the second metal layer 224 is disposed between the second conductive layer 222 and the second electrode 400 .

[0078] In some embodiments, the second conductive layer 222 may be made of polysilicon and may have a thickness of 300-700 angstroms. For example, the dielectric layer 222 may have a thickness of 300 angstroms, 400 angstroms, 500 angstroms, 600 angstroms, or 700 angstroms.

[0079] In some embodiments, the first metal layer 221 may be one or more of a tungsten (W) layer, a cobalt (Co) layer, a nickel (Ni) layer, a tantalum (Ta) layer, a tantalum nitride (TaN) layer, a titanium (Ti) layer, and a titanium nitride (TiN) layer. In some embodiments, the material of the first metal layer 221 may be titanium nitride, and the thickness may be 30 to 60 angstroms. For example, the thickness of the first metal layer 221 may be 30 angstroms, 40 angstroms, 50 angstroms, or 60 angstroms.

[0080] In some embodiments, the material of the second metal layer 224 can be one or more of a tungsten (W) layer, a cobalt (Co) layer, a nickel (Ni) layer, a tantalum (Ta) layer, a tantalum nitride (TaN) layer, a titanium (Ti) layer, and a titanium nitride (TiN) layer. In some embodiments, the material of the second metal layer 224 can be tungsten (W), and the thickness of W can be 200-500 angstroms. For example, the thickness of the second metal layer 224 can be 200 angstroms, 300 angstroms, 400 angstroms, or 500 angstroms.

[0081] In an optional embodiment, in order to reduce the mutual influence between the gate structure 200 and the first electrode 300 , the fuse structure further includes an insulating structure 500 , which is formed on the active area 110 and located between the first electrode 300 and the gate structure 200 .

[0082] Exemplarily, the insulating structure 500 includes an insulating material having an isolation function. For example, the insulating structure 500 may be composed of one or more insulating materials such as a silicon nitride (Si3N4) layer, a silicon oxynitride (SiON) layer, or a silicon carbide nitride (SiCN) layer. When the insulating structure 500 has a multi-layer structure, an air gap may be formed in the middle to improve the isolation effect. In addition, the multi-layer structure of the insulating structure 500 may be formed of different materials. For example, the first layer may be silicon nitride, the second layer may be silicon oxide, and the third layer may be silicon nitride. In this embodiment, the insulating structure 500 may be a single-layer structure formed of silicon nitride material.

[0083] In some embodiments, the insulating structure 500 is formed outside the gate structure 200. When forming the second electrode 400, a portion of the insulating structure 500 can be removed by etching to expose a portion of the side surface of the gate structure 200, thereby forming the second electrode 400. The exposed side surface of the gate structure 200 can be the side of the gate structure 200 away from the first electrode 300.

[0084] In an optional embodiment, in order to reduce the contact resistance between the second electrode 400 and the gate structure 200, a first conductive layer 223 with lower resistivity is used instead of the second conductive layer 222 in the gate structure 200 to contact the second electrode 400. Exemplarily, the gate material layer 220 includes a first conductive layer 223 and a second conductive layer 222, wherein the material of the first conductive layer 223 can be cobalt silicide (CoSi2), the first conductive layer 223 and the second conductive layer 222 are adjacent in a direction parallel to the substrate 100, and the resistivity of the first conductive layer 223 is lower than the resistivity of the second conductive layer 222. The first conductive layer 223 can reduce the resistance of the electrical path, increase the breakdown current, and reduce the difficulty of breaking down the fuse dielectric layer 210.

[0085] In an optional embodiment, the first conductive layer 223 is adjacent to the second electrode 400 .

[0086] In an optional embodiment, in a direction parallel to the substrate 100 , the first conductive layer 223 has a first width, the second conductive layer 222 has a second width, and the first width is smaller than the second width.

[0087] In an optional embodiment, in order to reduce the contact resistance between the first electrode 300 and the active area 110, the fuse structure further includes:

[0088] The third conductive layer 130 is made of cobalt silicide and is formed between the active area 110 of the substrate 100 and the first electrode 300 . The resistivity of the third conductive layer 130 is lower than that of the first electrode 300 .

[0089] Reference Figure 2-8 , an embodiment of the present application further provides a method for forming a fuse structure, comprising:

[0090] Providing a substrate 100, wherein the substrate 100 includes an active region 110 and an isolation structure 120 adjacent to the active region 110;

[0091] forming a gate structure 200 , wherein the gate structure 200 is at least partially formed on the active area 110 ;

[0092] forming a first electrode 300 , wherein the first electrode 300 is formed on the active area 110 and spaced apart from the gate structure 200 ;

[0093] A second electrode 400 is formed. The second electrode 400 is at least partially formed on the isolation structure 120 and is adjacent to a side surface of the gate structure 200 .

[0094] In the fuse structure of this embodiment, the first electrode 300 , the active region 110 , the gate structure 200 , and the second electrode 400 are conductively connected in sequence from the first electrode 300 toward the second electrode 400 , forming an electrical path H. The second electrode 400 is connected to the side surface of the gate structure 200 , thereby increasing the contact area between the second electrode 400 and the gate structure 200 , thereby reducing the conductive resistance, increasing the current in the electrical path H, and making it easier to break through the fuse dielectric layer 210 in the gate structure 200 .

[0095] In an optional embodiment, the substrate 100 may be a P-type silicon substrate or an N-type silicon substrate. In this embodiment, the substrate 100 is a P-type silicon substrate.

[0096] In an optional embodiment, the substrate 100 may be a single crystal silicon substrate or a polycrystalline silicon substrate. In this embodiment, the substrate 100 is a polycrystalline silicon substrate, wherein the material of the active region 110 formed in the substrate 100 may be polycrystalline silicon.

[0097] In an optional embodiment, the material of the first electrode 300 and the second electrode 400 can be one or more materials selected from the group consisting of a tungsten (W) layer, a cobalt (Co) layer, a nickel (Ni) layer, a tantalum (Ta) layer, a tantalum nitride (TaN) layer, a titanium (Ti) layer, and a titanium nitride (TiN) layer. For example, the material of the first electrode 300 and the second electrode 400 is titanium nitride.

[0098] In an optional embodiment, in order to reduce the mutual influence between the first electrode 300 and the second electrode 400, the fuse structure further includes:

[0099] The passivation layer 600 is formed between the first electrode 300 and the second electrode 400 .

[0100] Exemplarily, the passivation layer 600 includes an insulating material having an isolation function. For example, the passivation layer 600 may be an oxide layer (BOX), and the material of the oxide layer may be silicon oxide (SiO 2 ).

[0101] In an optional embodiment, the isolation structure 120 may be an isolation structure 120 formed on the surface of the substrate 100 , or may be a shallow trench isolation structure formed in the substrate 100 .

[0102] Exemplarily, the second electrode 400 is formed on the isolation structure 120 .

[0103] Exemplarily, the gate structure 200 is formed on the active region 110 and the isolation structure 120 at the same time.

[0104] In an optional embodiment, the gate structure 200 includes:

[0105] The fuse dielectric layer 210 is configured to be broken down by a programming current;

[0106] A gate material layer 220 is formed on the fuse dielectric layer 210 .

[0107] For example, the fuse dielectric layer 210 in the gate structure 200 serves as the gate dielectric layer of the gate structure 200. The material of the fuse dielectric layer 210 may be hafnium oxide (HfO2). Using HfO2 as the gate dielectric layer can reduce the thickness of the gate dielectric layer, thereby further reducing the difficulty of breakdown. In some embodiments, the equivalent thickness of HfO2 can be less than 25 angstroms. For example, the equivalent thickness of the fuse dielectric layer 210 can be 15 angstroms, 16 angstroms, 17 angstroms, 18 angstroms, 19 angstroms, or 20 angstroms.

[0108] Exemplarily, the gate material layer 220 includes a second conductive layer 222 , a first metal layer 221 and a second metal layer 224 . The first metal layer 221 is disposed between the second conductive layer 222 and the fuse dielectric layer 210 , and the second metal layer 224 is disposed between the second conductive layer 222 and the second electrode 400 .

[0109] In some embodiments, the second conductive layer 222 may be made of polysilicon and may have a thickness of 300-700 angstroms. For example, the dielectric layer 222 may have a thickness of 300 angstroms, 400 angstroms, 500 angstroms, 600 angstroms, or 700 angstroms.

[0110] In some embodiments, the first metal layer 221 may be one or more of a tungsten (W) layer, a cobalt (Co) layer, a nickel (Ni) layer, a tantalum (Ta) layer, a tantalum nitride (TaN) layer, a titanium (Ti) layer, and a titanium nitride (TiN) layer. In some embodiments, the material of the first metal layer 221 may be titanium nitride, and the thickness may be 30 to 60 angstroms. For example, the thickness of the first metal layer 221 may be 30 angstroms, 40 angstroms, 50 angstroms, or 60 angstroms.

[0111] In some embodiments, the material of the second metal layer 224 can be one or more of a tungsten (W) layer, a cobalt (Co) layer, a nickel (Ni) layer, a tantalum (Ta) layer, a tantalum nitride (TaN) layer, a titanium (Ti) layer, and a titanium nitride (TiN) layer. In some embodiments, the material of the second metal layer 224 can be tungsten (W), and the thickness of W can be 200-500 angstroms. For example, the thickness of the second metal layer 224 can be 200 angstroms, 300 angstroms, 400 angstroms, or 500 angstroms.

[0112] In an optional embodiment, the step of forming the first electrode 300 includes:

[0113] forming a passivation layer 600 on the substrate 100 to cover the gate structure 200;

[0114] Performing an etching process to form a first electrode hole 300 in the passivation layer 600 on the active area 110 , wherein the first electrode hole 300 exposes the active area 110 ;

[0115] The first electrode 300 material is filled in the first electrode hole 300 to form the first electrode 300 .

[0116] The passivation layer 600 includes an insulating material having an isolation function. For example, the passivation layer 600 may be an oxide layer (BOX), and the material of the oxide layer may be silicon oxide (SiO 2 ).

[0117] Exemplarily, the formation process of the first electrode hole 300 may be:

[0118] A photoresist layer is formed on the passivation layer 600 ; the photoresist layer is patterned to form a first etching window; the passivation layer 600 is etched according to the first etching window to expose a portion of the active area 110 to form a first electrode hole 300 ; and the photoresist layer is removed.

[0119] In an optional embodiment, the step of forming the second electrode 400 includes:

[0120] forming a second electrode hole 400 in the passivation layer 600 on the isolation structure 120 , wherein the second electrode hole 400 at least exposes a side surface of the gate structure 200 ;

[0121] The second electrode hole 400 is filled with an electrode material to form the second electrode 400 .

[0122] Exemplarily, the second electrode hole 400 may be formed by:

[0123] A photoresist layer is formed on the passivation layer 600; the photoresist layer is patterned to form a first etching window and a second etching window; the passivation layer 600 and a portion of the blocking layer are etched according to the second etching window, and at least a portion of the top surface of the gate structure 200 and the side away from the first electrode 300 are exposed to form a second electrode hole 400; and the photoresist layer is removed.

[0124] In an optional embodiment, the method for forming the fuse structure further includes:

[0125] A first conductive layer 223 is formed, and the first conductive layer 223 is formed on the side of the gate structure 200 adjacent to the first electrode 300. The gate structure 200 includes a second conductive layer 222. The first conductive layer 223 and the second conductive layer 222 are adjacent in a direction parallel to the substrate 100. The resistivity of the first conductive layer 223 is less than the resistivity of the second conductive layer 222.

[0126] In an optional embodiment, the step of forming the first conductive layer 223 includes:

[0127] Before forming the second electrode 400 in the second electrode hole 400 , metal is first deposited in the second electrode hole 400 ;

[0128] High-temperature annealing is performed to allow the polysilicon in the second conductive layer 222 exposed in the second electrode hole 400 to react with the metal to form a first conductive layer 223 .

[0129] Exemplarily, the first conductive layer 223 may be formed by:

[0130] A metal is deposited in the second electrode hole 400 , which may be a cobalt layer. High-temperature annealing is performed to allow the polysilicon in the second conductive layer 222 to diffuse with the cobalt layer to form cobalt silicide (CoSi 2 , ie, the first conductive layer 223 ).

[0131] In an optional embodiment, in a direction parallel to the substrate 100 , the first conductive layer 223 has a first width, the second conductive layer 222 has a second width, and the first width is smaller than the second width.

[0132] In an optional embodiment, the method for forming the fuse structure further includes:

[0133] A third conductive layer 130 is formed on a surface of the active region 110 adjacent to the first electrode 300 .

[0134] In an optional embodiment, the step of forming the third conductive layer 130 includes:

[0135] Before filling the first electrode hole 300 with the electrode material, depositing metal in the first electrode hole 300;

[0136] High temperature annealing is performed to react the polysilicon in the active area 110 exposed in the first electrode hole 300 with the metal to form a third conductive layer 130 . The resistivity of the third conductive layer 130 is lower than that of the first electrode 300 .

[0137] Exemplarily, the first conductive layer 223 may be formed by:

[0138] A metal is deposited in the first electrode hole 300 , which may be a cobalt layer. High-temperature annealing is performed to allow the polysilicon in the active area 110 to diffuse with the cobalt layer to form cobalt silicide (CoSi 2 , ie, the third conductive layer 130 ).

[0139] In some optional embodiments, in order to reduce the mutual influence between the gate structure 200 and the first electrode 300, the method for forming the fuse structure further includes:

[0140] An insulating structure 500 is formed outside the gate structure 200 .

[0141] Exemplarily, the insulating structure 500 includes an insulating material having an isolation function. For example, the insulating structure 500 may be composed of one or more insulating materials such as a silicon nitride (Si3N4) layer, a silicon oxynitride (SiON) layer, or a silicon carbide nitride (SiCN) layer. When the insulating structure 500 has a multi-layer structure, an air gap may be formed in the middle to improve the isolation effect. In addition, the multi-layer structure of the insulating structure 500 may be formed of different materials. For example, the first layer may be silicon nitride, the second layer may be silicon oxide, and the third layer may be silicon nitride. In this embodiment, the insulating structure 500 may be a single-layer structure formed of silicon nitride material.

[0142] In some embodiments, the insulating structure 500 is formed outside the gate structure 200. When forming the second electrode 400, a portion of the insulating structure 500 can be removed by etching to expose a portion of the side surface of the gate structure 200, thereby forming the second electrode 400. The exposed side surface of the gate structure 200 can be the side of the gate structure 200 away from the first electrode 300.

[0143] An embodiment of the present application further provides a programmable memory, comprising the fuse structure of any one of the aforementioned embodiments.

[0144] The programmable memory of this embodiment includes the fuse structure of any of the aforementioned embodiments and has the technical effects of the fuse structure, which will not be described in detail here.

[0145] It should be understood that the above-mentioned specific implementation methods of the embodiments of the present application are merely used to illustrate or explain the principles of the embodiments of the present application, and do not constitute a limitation on the embodiments of the present application. Therefore, any modifications, equivalent substitutions, improvements, etc. made without departing from the spirit and scope of the embodiments of the present application should be included in the protection scope of the embodiments of the present application. In addition, the claims attached to the embodiments of the present application are intended to cover all changes and modifications that fall within the scope and boundaries of the attached claims, or the equivalent forms of such scope and boundaries.

Claims

1. A fuse structure comprising: a gate structure, the gate structure being at least partially formed on an active region of the substrate; a first electrode, wherein the first electrode is formed on the active area of ​​the substrate and is spaced apart from the gate structure; a second electrode, the second electrode being formed at least on a side surface of the gate structure; an isolation structure formed between the active region and the second electrode; The gate structure includes a gate material layer; the gate material layer includes a first conductive layer and a second conductive layer, the first conductive layer and the second conductive layer are adjacent to each other in a direction parallel to the substrate, and the first conductive layer is adjacent to the second electrode.

2. The fuse structure according to claim 1, wherein: The gate structure further includes: Fuse dielectric layer.

3. The fuse structure according to claim 1, wherein: The isolation structure is formed in the substrate and is adjacent to the active area; The second electrode is formed on the isolation structure.

4. The fuse structure according to claim 3, wherein: The gate structure is formed on the active region and the isolation structure at the same time.

5. The fuse structure according to claim 1, wherein: An insulating structure is also included, wherein the insulating structure is formed on the active area and is located between the first electrode and the gate structure.

6. The fuse structure according to claim 2, wherein: The resistivity of the first conductive layer is lower than that of the second conductive layer.

7. The fuse structure according to claim 1, wherein: In a direction parallel to the substrate, the first conductive layer has a first width, and the second conductive layer has a second width, wherein the first width is smaller than the second width.

8. The fuse structure according to claim 1, wherein: The fuse structure further includes: A third conductive layer is formed between the active area of ​​the substrate and the first electrode, and the resistivity of the third conductive layer is lower than the resistivity of the first electrode.

9. The fuse structure according to claim 1, wherein: The fuse structure further includes: A passivation layer is formed between the first electrode and the second electrode.

10. A method for forming a fuse structure, comprising: Providing a substrate, wherein the substrate includes an active area and an isolation structure adjacent to the active area; forming a gate structure, wherein the gate structure is at least partially formed on the active area; forming a first electrode, wherein the first electrode is formed on the active area and spaced apart from the gate structure; forming a second electrode, wherein the second electrode is at least partially formed on the isolation structure and is adjacent to a side surface of the gate structure; Before filling the second electrode hole with the electrode material, the method for forming the fuse structure further includes: A first conductive layer is formed, where the first conductive layer is formed on a side of the gate structure adjacent to the second electrode. The gate structure includes a second conductive layer, and the first conductive layer and the second conductive layer are adjacent to each other in a direction parallel to the substrate.

11. The method according to claim 10, wherein: The step of forming the first electrode includes: forming a passivation layer covering the gate structure on the substrate; performing an etching process to form a first electrode hole in the passivation layer on the active area, wherein the first electrode hole exposes the active area; The first electrode hole is filled with a first electrode material to form a first electrode.

12. The method of claim 11, wherein: The step of forming the second electrode comprises: forming a second electrode hole in the passivation layer on the isolation structure, wherein the second electrode hole at least exposes a side surface of the gate structure; The second electrode hole is filled with an electrode material to form the second electrode.

13. The method of claim 12, wherein: The resistivity of the first conductive layer is lower than that of the second conductive layer.

14. The method of claim 13, wherein: The step of forming the first conductive layer comprises: depositing metal in the second electrode hole; High-temperature annealing is performed to allow the polysilicon in the second conductive layer exposed in the second electrode hole to react with the metal to form a first conductive layer.

15. The method of claim 13, wherein: In a direction parallel to the substrate, the first conductive layer has a first width, and the second conductive layer has a second width, wherein the first width is smaller than the second width.

16. The method of claim 11, wherein: Before filling the first electrode hole with an electrode material, the method for forming the fuse structure further includes: A third conductive layer is formed, wherein the third conductive layer is formed on a surface of the active region adjacent to the first electrode.

17. The method of claim 16, wherein: The step of forming the third conductive layer comprises: depositing metal in the first electrode hole; High-temperature annealing is performed to allow the polysilicon in the active area exposed in the first electrode hole to react with the metal to form a third conductive layer, wherein the resistivity of the third conductive layer is lower than the resistivity of the first electrode.

18. The method of claim 10, wherein: The method for forming the fuse structure further includes: An insulating structure is formed outside the gate structure.

19. A programmable memory comprising the fuse structure according to any one of claims 1 to 9.

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