A real-time alignment method and system for multi-link data and a storage medium

Abstract

The application discloses a real-time alignment method and system of multi-link data and a storage medium, and the method comprises the following steps: an upper computer receives a plurality of parallel link data, the link data is link data after phase calibration and bit alignment; a corresponding first-in-first-out storage unit is constructed for each link data in the upper computer, when it is detected that the link data arrives, the link data is cached to the corresponding first-in-first-out storage unit; after all the link data is received and cached to the corresponding first-in-first-out storage unit, the link data in all the first-in-first-out storage units is synchronously released, and the multi-link data alignment is realized. The application re-aligns according to the delay among the current links when each row or each frame of data arrives, and the real-time alignment is ensured; and the alignment of each channel only needs to use a small amount of resources, and the number of simultaneously aligned links is not limited, and the alignment of hundreds of link channels can be extended.

Description

A method, system, and storage medium for real-time alignment of multi-link data Technical Field

[0001] This invention relates to digital communication technology, and in particular to a method, system, and storage medium for real-time alignment of multi-link data. Background Technology

[0002] With the rise of big data and the rapid development of information technology, data transmission demands increasingly higher bus bandwidth. The development of parallel transmission technology has been hampered by a series of problems, including difficulties in timing synchronization, severe signal offset, weak anti-interference capabilities, and high design complexity. Compared to parallel transmission technology, serial transmission technology has fewer pins, stronger scalability, and uses a point-to-point connection method, providing higher bandwidth. Therefore, it is now widely used in embedded high-speed transmission fields.

[0003] As sensor size, resolution, and transmission rate increase, sensor data is often transmitted to the FPGA via multiple LVDS interfaces or other high-speed data interfaces. For example, some large-area, high-resolution, high-speed sensors with LVDS interfaces can have hundreds of data link interfaces. For sensors with a large number of data output links, PCB length matching poses a significant challenge to onboard layout. Failure to control length matching will result in uncertain delays between data transmitted from each link, and this uncertainty will change with external factors such as temperature and voltage. Therefore, stable and reliable real-time alignment of data from different links is crucial.

[0004] In some non-sensor applications, several solutions have been developed to address data alignment issues. Chinese patent CN112799983A employs a method that uses the position of a query flag bit within the data stream as the target position for shifting to achieve alignment. However, this method relies on a specific flag bit; the sensor must send the flag bit at the beginning of a line or frame of data to complete alignment. Furthermore, once the alignment shift is complete, real-time alignment cannot be dynamically achieved.

[0005] In summary, the main shortcomings of the existing technology are as follows:

[0006] (1) Due to the presence of a flag, the sensor must send a specific start of line or start of frame flag in order to complete the alignment.

[0007] (2) Once the alignment is completed, the alignment between the links is locked and will not change. If the actual delay of the link changes due to external conditions, the previous alignment will no longer be applicable.

[0008] (3) The alignment between channels is interconnected, which is not conducive to expansion and system reliability. Summary of the Invention

[0009] The present invention proposes a real-time alignment method, system, and storage medium for multi-link data, which can at least solve one of the above-mentioned technical problems.

[0010] To achieve the above objectives, the present invention proposes the following technical solution:

[0011] A real-time alignment method for multi-link data includes:

[0012] The host computer receives multiple parallel link data, which are link data after phase calibration and bit alignment;

[0013] The host computer constructs a corresponding first-in-first-out (FIFO) storage unit for each link data. When the arrival of the link data is detected, the link data is cached in the corresponding FIFO storage unit.

[0014] After all link data is received and cached in the corresponding FIFO storage unit, the link data in all FIFO storage units is released synchronously to achieve multi-link data alignment.

[0015] Further, the step of caching the link data in the corresponding first-in-first-out storage unit when the arrival of the link data is detected includes:

[0016] For multi-link data with a start flag, when the start flag of the link data is detected, the link data is cached in the corresponding first-in-first-out storage unit starting from the start flag.

[0017] After all the link data has been received and cached in the corresponding FIFO storage unit, the link data in all FIFO storage units is released synchronously, including:

[0018] At each clock edge, it checks whether the first data in all FIFO memory cells is the start flag. When the first data in all FIFO memory cells is the start flag, all link data in all FIFO memory cells starts from the start flag and is released synchronously and one by one.

[0019] Further, the step of caching the link data in the corresponding first-in-first-out storage unit when the arrival of the link data is detected includes:

[0020] For multi-link data without a start flag, when the first valid data of the link data is detected, the link data is cached in the corresponding first-in-first-out storage unit starting from the first valid data.

[0021] After all the link data has been received and cached in the corresponding FIFO storage unit, the link data in all FIFO storage units is released synchronously, including:

[0022] At each clock edge, it checks whether the first data in all FIFO memory cells is valid. When the first data in all FIFO memory cells is valid, all link data in all FIFO memory cells are released synchronously and one by one, starting from the first valid data bit.

[0023] Furthermore, the multi-link data comes from the image sensor, and the host computer is an FPGA. Before the image sensor transmits the data to the FPGA through multiple data links, the data is also subjected to phase calibration, serial-to-parallel conversion, and bit alignment operations.

[0024] Furthermore, the link data is image data transmitted in parallel, including frame data or line data, and the real-time alignment method for multi-link data further includes:

[0025] After receiving each frame or line of multi-link data, the FPGA performs a real-time alignment method for the multi-link data.

[0026] Furthermore, the first-in-first-out (FIFO) memory unit is constructed based on the register resources within the FPGA.

[0027] On the other hand, the present invention also proposes a real-time alignment system for multi-link data, comprising:

[0028] Data receiving module: used to receive multiple parallel link data, the link data being link data after phase calibration and bit alignment, and to transmit the multiple parallel link data to the first-in-first-out storage unit module;

[0029] First-In-First-Out (FIFO) Storage Unit Module: Constructs a corresponding FIFO storage unit for each link data. When the arrival of the link data is detected, the link data is cached in the corresponding FIFO storage unit. After receiving the synchronization release signal sent from the link release determination module, the link data in all FIFO storage units is released synchronously to achieve multi-link data alignment.

[0030] Link release determination module: After detecting that all link data has been received and cached in the corresponding first-in-first-out storage unit, it sends a synchronization release signal to the first-in-first-out storage unit module.

[0031] Furthermore, each FIFO storage unit of the FIFO storage unit module sends a received signal to the link release determination module when it caches link data. When the link release determination module receives the received signals from all FIFO storage units, it sends a synchronization release signal to the FIFO storage unit module.

[0032] Furthermore, the present invention provides a computer-readable storage medium in which, when the computer program is executed by a processor, the processor enables the aforementioned real-time alignment method for multi-link data.

[0033] This invention primarily implements an automatic alignment method for receiving row or frame data from an image sensor based on an FPGA. This method is mainly used to automatically align the row or frame data of each link when acquiring parallel data transmitted from the image sensor through multiple data links and after phase calibration and serial-to-parallel conversion, thus avoiding data misalignment. For image sensors with multiple output links, there may be differences in link delays in the PCB design, leading to situations where, even after data bit alignment, the row or frame data from different links in a single frame of image data are still misaligned.

[0034] In this invention, either the start of line or start of frame flags can be used as the basis for alignment, or the difference between the data sent by the sensor in the empty state and the valid data can be used as the basis for alignment. There is no hard requirement for whether the sensor outputs flags. In addition, this invention will re-align according to the current link delay when each line or frame of data arrives, ensuring the real-time alignment. Finally, the alignment of each channel only requires a small amount of resources, and there is no limit to the number of links that can be aligned at the same time, which can be extended to align hundreds of link channels. Attached Figure Description

[0035] Figure 1 is a flowchart of a real-time alignment method for multi-link data according to the present invention;

[0036] Figure 2 is a schematic diagram of the multi-link data alignment method in Embodiment 1 of the present invention;

[0037] Figure 3 is a schematic diagram of the alignment method for multi-link data in Embodiment 2 of the present invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0039] Example 1

[0040] Image sensors typically transmit serial data to an FPGA via multiple data links. Upon receiving the data, the FPGA generally performs phase calibration, serial-to-parallel conversion, and bit alignment to obtain parallel sensor image data. At this point, the parallel sensor image data for each link is usually in IDLE (empty state) code. When a valid frame or line of data arrives, a start flag is typically received first, but it may not be present, and the image data information is transmitted directly. When the multiple links of the image sensor have long traces on the PCB without equalization control, if the delay between them after the preceding processing exceeds the clock length of one parallel data cycle, data misalignment will occur, requiring alignment.

[0041] In this embodiment, flag bits are used for link data alignment, as shown in Figure 2. First, data arrives from multiple links. Due to transmission delays, misalignment may occur after clock sampling, resulting in a difference of several clock cycles between them. In this invention, the FPGA's register resources are used to construct a first-in-first-out (FIFO) storage unit for each data link. When a start-of-line or start-of-frame flag bit is detected, data is temporarily and continuously buffered in the storage unit starting from the flag bit. Simultaneously, at each clock edge, the first data stored in all storage units is checked until the first data stored in all link storage units is the flag bit, indicating that all valid link data has arrived in the storage unit. After detecting this, all data link storage units are synchronously released, and data information is output one by one starting from the flag bit. In this way, during the output of line or frame data, each link's storage unit always buffers the number of data corresponding to the link's delay, thus keeping all data links synchronized and completing alignment.

[0042] The alignment process described above ensures that consecutive rows or frames of data remain aligned. When a row or frame of data ends, all storage units will empty their stored data to guarantee data integrity. At this point, the alignment process returns to its initial state. When the next row or frame of data arrives, the same process is repeated to cache and release data from each data link, aligning it according to the current latency of each link, thus ensuring the real-time performance of this alignment method.

[0043] Furthermore, this embodiment is based on FPGA to align multi-link data from an image sensor. If other carriers that can achieve the same function are used to align multi-link data from other sources, it should also be within the scope of this invention.

[0044] The method described in this embodiment is based on an FPGA, and is implemented by dividing the FPGA into the following modules:

[0045] Data receiving module: The data sent to this module must be parallel data from multiple links after phase calibration, serial-to-parallel conversion, and bit alignment. The data receiving module is responsible for receiving parallel data from multiple links and transmitting it to the input of the first-in-first-out (FIFO) memory array to await operation execution.

[0046] First-in-first-out storage unit module: Each link is allocated a storage unit to buffer the link data after the start flag or non-idle code is detected, in order to wait for the synchronization release signal;

[0047] Link release determination module: Used to generate signals to control the synchronous release of all storage units. Each storage unit will give a single link received signal when it starts to cache valid data. After receiving signals from all links, this module will give a synchronous release signal to achieve alignment.

[0048] Example 2

[0049] Example 1 addresses multi-link data with a start flag, but cannot align multi-link data without a start flag. Therefore, Example 2 of the present invention proposes a corresponding alignment method for multi-link data without a start flag, based on Example 1.

[0050] As shown in Figure 3, the link data in this embodiment includes an IDLE (empty state) code, i.e., the idle bit, the fill bit in Figure 3, and the data bit immediately following the IDLE code. For sensor data without a flag bit, the first valid data can be used as the signal to determine the start and release of the buffer based on the difference between the valid data and the data in the empty state. Each link starts buffering data when the first valid data arrives. When it is detected that the first data of all link storage units is not an empty code, all storage units are released synchronously, and real-time alignment is achieved in a manner similar to that in Embodiment 1.

[0051] Based on the same inventive concept, this invention also discloses a computer-readable storage medium storing at least one program data for implementing the aforementioned burst image acquisition control method for industrial cameras. The computer-readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0052] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0053] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for real-time alignment of multi-link data, characterized in that, include: The host computer receives multiple parallel link data, which are link data after phase calibration and bit alignment. The host computer constructs a corresponding first-in-first-out (FIFO) storage unit for each link data. When the arrival of the link data is detected, the link data is cached in the corresponding FIFO storage unit. For multi-link data without a start flag, when the first valid data of the link data is detected, the link data is cached in the corresponding FIFO storage unit starting from the first valid data. After all link data is received and cached in the corresponding FIFO (First-In, First-Out) memory unit, the link data in all FIFO memory units is released synchronously. This includes: at each clock edge, checking whether the first data in each FIFO memory unit is valid data; when the first data in all FIFO memory units is valid data, the link data in all FIFO memory units is released synchronously and sequentially, starting from the first valid data bit; for multi-link data with a start flag bit, when the start flag bit of the link data is detected, the link data is cached in the corresponding FIFO memory unit starting from the start flag bit. Storage unit; after all link data is received and cached in the corresponding FIFO storage unit, the link data in all FIFO storage units is released synchronously, including: when each clock edge arrives, detecting whether the first data in all FIFO storage units is a start flag bit; when the first data in all FIFO storage units is a start flag bit, the link data in all FIFO storage units is released synchronously and one by one, starting from the start flag bit; after all link data is received and cached in the corresponding FIFO storage unit, the link data in all FIFO storage units is released synchronously, realizing multi-link data alignment.

2. The real-time alignment method for multi-link data according to claim 1, characterized in that, The multi-link data comes from the image sensor, and the host computer is an FPGA. Before the image sensor transmits the data to the FPGA through multiple data links, the data also includes phase calibration, serial-to-parallel conversion, and bit alignment operations.

3. The real-time alignment method for multi-link data according to claim 2, characterized in that, The link data is image data transmitted in parallel, including frame data or line data. The real-time alignment method for multi-link data further includes: after the FPGA receives each frame or each line of multi-link data, it performs a real-time alignment method for multi-link data once.

4. The real-time alignment method for multi-link data according to claim 3, characterized in that, The first-in-first-out (FIFO) memory unit is constructed based on the register resources within the FPGA.

5. A real-time alignment system for multi-link data, characterized in that, include: Data receiving module: used to receive multiple parallel link data, the link data being link data after phase calibration and bit alignment, and to transmit the multiple parallel link data to the first-in-first-out storage unit module; First-in-first-out (FIFO) storage unit module: Constructs a corresponding FIFO storage unit for each link data. When the arrival of the link data is detected, the link data is cached in the corresponding FIFO storage unit. For multi-link data without a start flag, when the first valid data of the link data is detected, the link data is cached in the corresponding FIFO storage unit starting from the first valid data. After all link data is received and cached in the corresponding FIFO (First-In, First-Out) memory unit, the link data in all FIFO memory units is released synchronously. This includes: at each clock edge, checking whether the first data in each FIFO memory unit is valid data; when the first data in all FIFO memory units is valid data, all link data in all FIFO memory units are released synchronously and sequentially, starting from the first valid data bit; for multi-link data with a start flag bit, when the start flag bit of the link data is detected, the link data is cached in the corresponding FIFO memory unit starting from the start flag bit; the process of receiving and caching all link data in the corresponding FIFO memory unit is as follows: After the storage unit is completed, the link data in all FIFO storage units is released synchronously, including: when each clock edge arrives, detecting whether the first data in all FIFO storage units is a start flag; when the first data in all FIFO storage units is a start flag, the link data in all FIFO storage units is released synchronously and one by one, starting from the start flag; after receiving the synchronous release signal sent from the link release determination module, the link data in all FIFO storage units is released synchronously to achieve multi-link data alignment; the link release determination module: after detecting that all link data has been received and cached in the corresponding FIFO storage unit, sends a synchronous release signal to the FIFO storage unit module.

6. The real-time alignment system for multi-link data according to claim 5, characterized in that, When each FIFO storage unit of the FIFO storage unit module caches link data, it sends a received signal to the link release determination module. When the link release determination module receives the received signals from all FIFO storage units, it sends a synchronization release signal to the FIFO storage unit module.

7. A computer-readable storage medium comprising a computer program, characterized in that, When the computer program is executed by a processor, the processor performs the real-time alignment method for multi-link data as described in any one of claims 1 to 4.

Images