Power consumption monitoring system and server

Abstract

The present application relates to a power consumption monitoring system and a server. The power consumption monitoring system is arranged inside the server, and the power consumption monitoring system includes a processor, a first monitored device, and a baseboard management controller BMC; wherein the processor communicates with the first monitored device through a serial voltage identification SVID bus, and the processor communicates with the BMC through a platform environment control interface PECI bus; the processor is used to obtain first power consumption data of the first monitored device through the SVID bus, and send the first power consumption data and the second power consumption data of the processor to the BMC through the PECI bus. That is to say, in the present application, the processor obtains the power consumption data of the first monitored device in real time through the SVID bus. Compared with the BMC obtaining the power consumption data through the SMBus bus, since the transmission frequency of the SVID bus is much greater than the transmission frequency of the SMBus bus, the acquisition rate of the power consumption data can be greatly improved, and the real-time performance of the power consumption monitoring can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of servers, and in particular to a power consumption monitoring system and a server. Background Art

[0002] As processor performance improves, the better the processor's computing performance, the higher the corresponding power consumption. Therefore, for servers using high-performance processors, after deploying a large-scale data center including multiple such servers, in order to ensure that the power consumption of the entire data center is within a controllable range, it is necessary to monitor and limit the power consumption of each server cabinet in the data center.

[0003] When monitoring the power consumption of a server, a baseboard management controller (BMC) in the server is usually used to read the power consumption data of each component in the server through the system management bus (SMBus), and monitor and record the power consumption data of each component.

[0004] However, existing power consumption data monitoring methods cannot meet the real-time monitoring requirements of power consumption monitoring. Summary of the invention

[0005] Based on this, it is necessary to provide a power consumption monitoring system and a server that can improve the real-time performance of power consumption data monitoring of the server in response to the above technical problems.

[0006] In a first aspect, the present application provides a power consumption monitoring system, including: a processor, a first monitored device, and a baseboard management controller BMC;

[0007] The processor communicates with the first monitored device via a serial voltage identification SVID bus, and the processor communicates with the BMC via a platform environment control interface PECI bus;

[0008] The processor is used to obtain first power consumption data of a first monitored device through an SVID bus, and send the first power consumption data and second power consumption data of the processor to the BMC through a PECI bus.

[0009] In this embodiment, a power consumption monitoring system is set inside the server, and the power consumption monitoring system includes a processor, a first monitored device, and a baseboard management controller BMC; wherein the processor communicates with the first monitored device through a serial voltage identification SVID bus, and the processor communicates with the BMC through a platform environment control interface PECI bus; the processor is used to obtain the first power consumption data of the first monitored device through the SVID bus, and send the first power consumption data and the second power consumption data of the processor to the BMC through the PECI bus. That is to say, in this application, the processor obtains the power consumption data of the first monitored device in real time through the SVID bus, compared with the BMC obtaining the power consumption data through the SMBus bus, because the transmission frequency of the SVID bus is much greater than the transmission frequency of the SMBus bus, therefore, the acquisition rate of the power consumption data can be greatly improved, and the real-time performance of the power consumption monitoring can be improved.

[0010] In one of the embodiments, the first monitored device includes at least one of a power supply unit PSU, a power supply device VR, and a key component.

[0011] In one embodiment, the power consumption monitoring system further includes a first power consumption monitoring circuit and a second power consumption monitoring circuit; the power supply device VR includes a first power supply device VR and a second power supply device VR;

[0012] The PSU is connected to the processor via the first power consumption monitoring circuit and the first power supply device VR in sequence, and the processor communicates with the first power supply device VR via the SVID bus;

[0013] The key components are connected to the processor via the second power consumption monitoring circuit and the second power supply device VR in sequence, and the processor communicates with the second power supply device VR via the SVID bus.

[0014] In this embodiment, the power consumption data of the first monitored device is measured by combining the power consumption monitoring circuit and the power supply device VR. That is, with the help of the power supply device VR supporting high communication frequency and the power consumption monitoring circuit adapted to the power supply device VR, the power consumption data of the first monitored device is measured in real time, so that the processor can obtain the power consumption data of the first monitored device in real time and at high frequency, thereby improving the real-time performance of power consumption monitoring.

[0015] In one embodiment, the first power consumption monitoring circuit includes a first precision resistor and a first amplifier; the first output terminal of the PSU is connected to the first end of the first precision resistor, the second end of the first precision resistor is connected to the input end of the first amplifier, and the output end of the first amplifier is connected to the input end of the first power supply device VR;

[0016] The second power consumption monitoring circuit includes a second precision resistor and a second amplifier; the output end of the key component is connected to the first end of the second precision resistor, the second end of the second precision resistor is connected to the input end of the second amplifier, and the output end of the second amplifier is connected to the input end of the second power supply device VR.

[0017] In this embodiment, the detection accuracy of power consumption data can be improved by using a precision resistance measurement method.

[0018] In one of the embodiments, the power consumption monitoring system further includes a second monitored device, and the second monitored device communicates with the BMC via a system management SMBus bus;

[0019] The BMC is used to obtain third power consumption data of the second monitored device through the SMBus bus.

[0020] In this embodiment, for some monitored devices that do not have high requirements for real-time power consumption monitoring inside the server, the SMBus interface of the BMC can still be used to read and monitor power consumption data. For some monitored devices that have high requirements for real-time power consumption monitoring inside the server, the above-mentioned method can be used to read and monitor power consumption data through the SVID bus. On the basis of ensuring real-time power consumption monitoring of core components, the structure of the power consumption monitoring system is simplified, the complexity of the power consumption monitoring system is reduced, and the overall working performance of the power consumption monitoring system is improved.

[0021] In one of the embodiments, the power consumption monitoring system further includes a logic circuit;

[0022] A logic circuit, configured to send a frequency reduction signal to the processor when receiving a first warning signal output by the PSU or a second warning signal output by the BMC;

[0023] The processor is used to perform a frequency reduction operation when a frequency reduction signal is received.

[0024] In this embodiment, by setting up a logic circuit in the power consumption monitoring system, adding early warning mechanisms such as overcurrent and overheating protection of the server, as well as a power consumption limiting function, it is possible to not only avoid power outages and downtime of the server under abnormal circumstances, but also ensure the efficient and stable operation of the server, thereby ensuring the stable operation of the data center.

[0025] In one embodiment, the second output terminal of the PSU is connected to the first input terminal of the logic circuit, the output terminal of the BMC is connected to the second input terminal of the logic circuit, and the output terminal of the logic circuit is connected to the processor.

[0026] In one of the embodiments, the PSU is configured to output a first warning signal through a second output terminal of the PSU when it is determined that the power consumption exceeds a first preset threshold;

[0027] The BMC is used to output a second warning signal through an output terminal of the BMC when it is determined that the power consumption exceeds a second preset threshold value; wherein the second preset threshold value is smaller than the first preset threshold value.

[0028] In one of the embodiments, the second output terminal of the PSU is also connected to the BMC.

[0029] In a second aspect, the present application further provides a server, which includes the power consumption monitoring system in the first aspect.

[0030] The above-mentioned power consumption monitoring system and server, the power consumption monitoring system is arranged inside the server, and the power consumption monitoring system includes a processor, a first monitored device and a baseboard management controller BMC; wherein the processor communicates with the first monitored device through the serial voltage identification SVID bus, and the processor communicates with the BMC through the platform environment control interface PECI bus; the processor is used to obtain the first power consumption data of the first monitored device through the SVID bus, and send the first power consumption data and the second power consumption data of the processor to the BMC through the PECI bus. That is to say, in the present application, the processor obtains the power consumption data of the first monitored device in real time through the SVID bus, compared with the BMC obtaining the power consumption data through the SMBus bus, because the transmission frequency of the SVID bus is much greater than the transmission frequency of the SMBus bus, therefore, the acquisition rate of the power consumption data can be greatly improved, and the real-time performance of the power consumption monitoring can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic diagram of the topological structure of a traditional power consumption monitoring system provided in an embodiment of the present application;

[0032] Figure 2 A schematic diagram of the structure of the power consumption monitoring system provided in an embodiment of the present application;

[0033] Figure 3 Another structural diagram of the power consumption monitoring system provided in an embodiment of the present application;

[0034] Figure 4 Another structural diagram of the power consumption monitoring system provided in an embodiment of the present application;

[0035] Figure 5 Another structural diagram of the power consumption monitoring system provided in an embodiment of the present application;

[0036] Figure 6 Another structural diagram of the power consumption monitoring system provided in an embodiment of the present application;

[0037] Figure 7 A logic flow chart of the early warning mechanism of the power consumption monitoring system provided in the embodiment of the present application;

[0038] Figure 8 A complete structural diagram of the power consumption monitoring system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0040] In the description of the embodiments of the present application, the terms "first" and "second" are used only for descriptive purposes and are not to be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more features.

[0041] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly stipulated and limited, the terms "connected" and "connection" should be understood in a broad sense. For example, it can be an electrical connection, a fixed connection, a detachable connection, or an integral connection. It can be a direct connection or an indirect connection. It can be the internal connection of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0042] The power consumption monitoring system provided in the embodiment of the present application is applicable to the field of server technology, especially to the power consumption data monitoring technology of the server. When the server is running, each component inside the server will generate a certain amount of power consumption, especially when the server has high performance or runs at high speed, the power consumption will increase accordingly.

[0043] As processor performance improves, many mainstream processor manufacturers in the industry have launched the latest central processing unit (CPU), graphics processing unit (GPU), field programmable gate array (FPGA) and AI processors. The computing performance of these processors is getting better and better, resulting in higher computing power. As processor power consumption continues to increase, large-scale data centers will have increasingly important requirements for the power consumption of each server in the data center after deployment.

[0044] When building and deploying a data center, the power consumption of the entire data center needs to be considered in advance. The scale of the data center is also taken into consideration, and the maximum power consumption that each server cabinet can support is determined. Usually, the maximum supported power consumption of a cabinet is about 8KW-10KW. The current high-specification version of the entire cabinet power consumption is about 15KW. In order to protect the power of the entire data center within a controllable range, the power consumption of each server cabinet must be limited to ensure the stable operation of the data center.

[0045] In order to monitor the power consumption of the server in real time, in the current server system design, the server system adopts the method of monitoring the power consumption by reading the baseboard management controller (Baseboard Management Controller, BMC) through the system management bus (System Management Bus, SMBus). The great defect of this method is the lag, which does not meet the requirements of real-time response to the current system power consumption. Specifically, in the current system design, the main components of the server system include the central processing unit (CPU), the platform control hub (Platform Controller Hub, PCH), the baseboard management controller (Baseboard Management Controller, BMC), the power supply unit (Power Supply Unit, PSU), power supply components and other key components. Its power consumption monitoring topology is as follows: Figure 1 As shown, in the system topology, the CPU and PCH are interconnected using the PECI bus, the BMC and PCH use the SMlink interface, and the BMC and other power-consuming components mainly include: SMBus1 between BMC and PSU (i.e., the entire system power consumption), SMBus2 between BMC and power supply VR and key components, and SMBus3 between BMC and other sensors (such as temperature sensors, etc.). In the method of using the main control chip BMC to read and monitor the power consumption of other important components through the SMBus bus, the operating frequency of the SMBus is 10KHz to 100KHz, so the transmission speed is very slow.

[0046] In addition, the current power consumption monitoring method still has the following technical problems:

[0047] 1. The SMBus bus is a bus protocol proposed by Intel in 1995. The SMBus provides a control bus for tasks such as system and power management. However, the clock frequency of the SMBus is between 10KHz and 100KHz, which greatly limits the effectiveness of power consumption data acquisition.

[0048] 2. In the current server platform, the processor pursues higher performance. During the working process, there will be a transient power consumption state, which lasts from 5us to tens of milliseconds. Therefore, the traditional SMBus has serious delays in reading speed and other problems, and cannot timely and accurately feedback the current power consumption data of the processor.

[0049] 3. During the operation of a low-power processor, the high power consumption state is instantly raised to 1.7 to 2 times the rated power. When the system has high power consumption, the PSU has no alarm feedback mechanism, which can easily trigger overcurrent protection and cause the system to shut down. Therefore, new requirements are put forward for the system response time and processing mechanism after obtaining the power consumption.

[0050] In response to the above technical problems, an embodiment of the present application proposes a power consumption monitoring system for a server. The power consumption monitoring system adopts a high-frequency SVID protocol to read the power consumption data of each key component to improve the real-time performance of power consumption monitoring. In addition, an alarm and feedback mechanism of the PSU is added, so that the processor can take a series of measures in time to reduce power consumption when the PSU has high power consumption, thereby ensuring the stable operation of the system.

[0051] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0052] Figure 2 This is a schematic diagram of the structure of the power consumption monitoring system provided in the embodiment of the present application. Figure 2 As shown, the power consumption monitoring system 100 includes: a processor 10, a first monitored device 20 and a baseboard management controller BMC30; wherein, the processor 10 communicates with the first monitored device 20 via a serial voltage identification SVID bus, and the processor 10 communicates with the BMC30 via a platform environment control interface PECI bus; the processor 10 is used to obtain first power consumption data of the first monitored device 20 via the SVID bus, and send the first power consumption data and the second power consumption data of the processor 10 to the BMC30 via the PECI bus.

[0053] Optionally, the processor 10 may include but is not limited to a CPU, a GPU, an FPGA, and an AI processor, and the first monitored device 20 may include but is not limited to a power supply unit PSU, a power supply device VR, and at least one of key components. The first monitored device 20 can communicate with the processor 10 directly or indirectly through a serial voltage identification SVID bus; that is, the first monitored device 20 can communicate with the processor 10 directly through a serial voltage identification SVID bus, or can communicate with the processor 10 through an intermediate device, that is, the first monitored device 20 is connected to an intermediate device, and the intermediate device communicates with the processor 10 through a serial voltage identification SVID bus; it should be noted that the number and type of intermediate devices in the embodiment of the present application are not specifically limited, as long as the intermediate device directly connected to the processor 10 supports SVID bus communication.

[0054] In the case where there are multiple first monitored devices 20, each first monitored device 20 can be connected to the processor 10 through different SVID bus interfaces of the processor 10, and the processor 10 includes multiple SVID bus interfaces; illustratively, the SVID bus protocol can be applied to the communication between the CPU and the power supply device VR, and is used to adjust the output voltage, monitor the state of the power supply device VR, and read the output power consumption data. Its communication frequency is 25MHz, and the SVID bus protocol is extended to read the input power consumption data to meet the requirements of real-time reading of power consumption data. For the power supply device VR, it can be directly connected to the SVID bus interface of the processor 10 through the SVID bus, the power supply unit PSU can be connected to the SVID bus0 interface of the processor 10 through a power supply device VR, and the key components can be connected to the SVID bus1 interface of the processor 10 through another power supply device VR, wherein the power supply device VR can include power supply devices VR14-1, VR14-2, VR14-3, etc. Optionally, a server can include 16 power supply devices VR.

[0055] Based on this, the processor 10 can obtain the first power consumption data of each first monitored device 20 through the SVID bus, and the processor 10 can also obtain its own second power consumption data through internal components, and then send the first power consumption data of each first monitored device 20 and the second power consumption data of the processor 10 itself to the BMC30 through the PECI bus; optionally, the processor 10 may include a battery control unit (Power Control Unit), also known as Pcode, which can complete the task of real-time reading of power consumption through the BIOS configuration function, that is, obtaining the first power consumption data of each first monitored device 20 and the second power consumption data of the processor 10 in real time; further, the Pcode inside the processor is interconnected with the BMC through the PECI bus, so that the BMC can obtain the power consumption data sent by the Pcode in real time through the PECI bus.

[0056] In this embodiment, a power consumption monitoring system is set inside the server, and the power consumption monitoring system includes a processor, a first monitored device, and a baseboard management controller BMC; wherein the processor communicates with the first monitored device through a serial voltage identification SVID bus, and the processor communicates with the BMC through a platform environment control interface PECI bus; the processor is used to obtain the first power consumption data of the first monitored device through the SVID bus, and send the first power consumption data and the second power consumption data of the processor to the BMC through the PECI bus. That is to say, in this application, the processor obtains the power consumption data of the first monitored device in real time through the SVID bus, compared with the BMC obtaining the power consumption data through the SMBus bus, because the transmission frequency of the SVID bus is much greater than the transmission frequency of the SMBus bus, therefore, the acquisition rate of the power consumption data can be greatly improved, and the real-time performance of the power consumption monitoring can be improved.

[0057] In one embodiment, Figure 3 As shown, the power consumption monitoring system 100 also includes a first power consumption monitoring circuit 401 and a second power consumption monitoring circuit 402; the power supply device VR includes a first power supply device VR501 and a second power supply device VR502; the PSU is connected to the processor 10 through the first power consumption monitoring circuit 401 and the first power supply device VR501 in sequence, and the processor 10 communicates with the first power supply device VR501 through the SVID bus; the key components are connected to the processor 10 through the second power consumption monitoring circuit 402 and the second power supply device VR502 in sequence, and the processor 10 communicates with the second power supply device VR502 through the SVID bus.

[0058] In this embodiment, a power consumption monitoring circuit is designed for the PSU and key components to adapt to the reading data requirements of the power supply device VR; optionally, the processor 10 may include multiple SVID bus interfaces, for example: the PSU is connected to the first power consumption monitoring circuit 401, the first power consumption monitoring circuit 401 is connected to the first power supply device VR501, and the first power supply device VR501 is connected to the SVID bus0 interface of the processor 10; the key components are connected to the second power consumption monitoring circuit 402, the second power consumption monitoring circuit 402 is connected to the second power supply device VR502, and the second power supply device VR502 is connected to the SVID bus1 interface of the processor 10.

[0059] It should be noted that the specific circuit structure of the power consumption monitoring circuit is not specifically limited in the embodiment of the present application. In practical applications, the actual circuit structure of the power consumption monitoring circuit can be adaptively developed according to the specific model or chip type of the power supply device VR, as long as the power consumption monitoring circuit can transmit the power consumption related parameters of the PSU or key components to the power supply device VR, or directly transmit the power consumption data of the PSU or key components to the power supply device VR; in addition, for the first power consumption monitoring circuit 401 and the second power consumption monitoring circuit 402, their circuit structures can be the same or different.

[0060] Exemplarily, for the first power consumption monitoring circuit 401 and the second power consumption monitoring circuit 402, they can use precision resistors in series to transmit the voltage and current signals of the first monitored device 20 to the power supply device VR, so that the power supply device VR can calculate the power consumption data of the first monitored device 20 based on the collected voltage and current signals, and then send the power consumption data of the first monitored device 20 to the processor 10 through the SVID bus.

[0061] Optionally, the first power consumption monitoring circuit 401 and the second power consumption monitoring circuit 402 may use a resistor four-wire measurement method to improve detection accuracy; for example, Figure 4 As shown, the first power consumption monitoring circuit 401 includes a first precision resistor 4011 and a first amplifier 4012, the first output end of the PSU is connected to the first end of the first precision resistor 4011, the second end of the first precision resistor 4011 is connected to the input end of the first amplifier 4012, and the output end of the first amplifier 4012 is connected to the input end of the first power supply device VR501; the second power consumption monitoring circuit 402 includes a second precision resistor 4021 and a second amplifier 4022, the output end of the key component is connected to the first end of the second precision resistor 4021, the second end of the second precision resistor 4021 is connected to the input end of the second amplifier 4022, and the output end of the second amplifier 4022 is connected to the input end of the second power supply device VR502.

[0062] In this embodiment, the power consumption data of the first monitored device is measured by combining the power consumption monitoring circuit and the power supply device VR. That is, with the help of the power supply device VR supporting high communication frequency and the power consumption monitoring circuit adapted to the power supply device VR, the power consumption data of the first monitored device is measured in real time, so that the processor can obtain the power consumption data of the first monitored device in real time and at high frequency, thereby improving the real-time performance of power consumption monitoring.

[0063] In one embodiment, Figure 5 As shown, the power consumption monitoring system 100 further includes a second monitored device 60, which communicates with the BMC 30 via a system management SMBus bus; the BMC 30 is configured to obtain third power consumption data of the second monitored device 60 via the SMBus bus.

[0064] Optionally, the second monitored device may include PCH, sensors, etc. That is to say, in this embodiment, for some monitored devices inside the server that do not have high requirements for real-time power consumption monitoring, the SMBus interface of the BMC can still be used to read and monitor power consumption data. For some monitored devices inside the server that have high requirements for real-time power consumption monitoring, the above-mentioned method can be used to read and monitor power consumption data through the SVID bus. On the basis of ensuring real-time power consumption monitoring of core components, the structure of the power consumption monitoring system is simplified, the complexity of the power consumption monitoring system is reduced, and the overall working performance of the power consumption monitoring system is improved.

[0065] In one embodiment, Figure 6 As shown, the power consumption monitoring system 100 also includes a logic circuit 70; the logic circuit 70 is used to send a frequency reduction signal to the processor 10 when receiving the first warning information output by the PSU or the second warning signal output by the BMC 30; the processor 30 is used to perform a frequency reduction operation when receiving the frequency reduction signal.

[0066] refer to Figure 6 A logic circuit 70 for abnormal alarm and power consumption reduction is also provided in the power consumption monitoring system. The second output end of the PSU is connected to the first input end of the logic circuit 70, the output end of the BMC30 is connected to the second input end of the logic circuit 70, and the output end of the logic circuit 70 is connected to the processor 10; optionally, the second output end of the PSU can be the function pin SM_Alert# of the PSU, the output end of the BMC30 can be the GPIO pin of the BMC, and the logic circuit can be a circuit composed of logic elements, and the logic element can include at least one of an AND gate, an OR gate, a NOT gate, a NAND gate, and a NOR gate.

[0067] Exemplarily, the PSU can output alarm signals such as overheating and overcurrent through the pin SM_Alert#. Optionally, the PSU can output the alarm signal to the BMC and PCH, and output it to the processor through the logic circuit, and implement AND operations of the alarm signals such as overheating and overcurrent in the logic circuit, so that in the event of an abnormal state in the entire server system, it can provide early warning and inform the processor, so that the processor can promptly adopt a series of operations to reduce power consumption and ensure the stable operation of the server system.

[0068] In one implementation, the abnormal alarm logic of the server system may include an abnormal alarm of the PSU and an abnormal alarm of the BMC. When the logic circuit receives an abnormal alarm signal of the PSU or an abnormal alarm signal of the BMC, it performs a corresponding frequency reduction operation. Wherein, the PSU may output a first warning signal through the second output terminal (i.e., pin SM_Alert#) of the PSU when judging that its power consumption exceeds a first preset threshold value. The first warning signal may be a low-level signal. The first preset threshold value may be the rated power of the PSU, or a certain threshold value higher or lower than the rated power of the PSU.

[0069] Similarly, for the BMC, the BMC can output a second warning signal through the output end of the BMC when it is determined that the power consumption exceeds the second preset threshold value. The second warning signal can also be a low-level signal, wherein the second preset threshold value is less than the first preset threshold value; wherein the BMC obtains the first power consumption data of the first monitored device and the second power consumption data of the processor from the processor through the PECI bus, and the first power consumption data of the first monitored device includes the power consumption data of the PSU and the power consumption data of the key components; then, the BMC can determine whether to output the second warning signal based on the size relationship between the first power consumption data and / or the second power consumption data and the second preset threshold value, that is, the BMC can determine whether to output the second warning signal based on the size relationship between the first power consumption data or the second power consumption data and the second preset threshold value, or it can combine the first power consumption data and the second power consumption data, and the size relationship with the second preset threshold value to determine whether to output the second warning signal, such as: determining whether to output the second warning signal based on the sum of the first power consumption data and the second power consumption data; the embodiment of the present application does not specifically limit the specific detection method of the BMC detection abnormal alarm.

[0070] Exemplarily, for a rack server, the total power consumption of the rack server is the output power consumption of the PSU. Then, the BMC can also determine whether to output a second warning signal based on the relationship between the power consumption data of the PSU and the second preset threshold. That is to say, the BMC can make an abnormal alarm judgment based on the power consumption monitoring data of the PSU in the first power consumption monitoring data; for other types of servers, such as blade servers, their total power consumption is the output power consumption of the back end of the hot-swap circuit, that is, the above-mentioned first power consumption monitoring circuit can also include a hot-swap circuit, and the BMC makes an abnormal alarm judgment based on the power consumption data of the hot-swap circuit.

[0071] The early warning mechanism of the above server system can refer to Figure 7 The logic flow chart shown has abnormal alarms of PSU and hot-swappable modules on the left and abnormal alarms of BMC on the right. Please refer to the detailed discussion above for details, which will not be repeated here. In addition, for the CPU frequency reduction operation, the CPU can work in different performance modes according to the business load, that is, perform different frequency reduction operations, such as: the abnormal alarm measures of PSU and hot-swappable modules and the abnormal alarm measures of BMC can be different, that is, corresponding to different frequency reduction strategies, to indicate that the CPU works in different performance working modes; of course, for the abnormal alarms of PSU and hot-swappable modules and the abnormal alarms of BMC, it can also include multiple different alarm levels, that is, multiple first preset thresholds or multiple second preset thresholds can be set, corresponding to different alarm levels; for different alarm levels, correspondingly, multiple CPU working modes with different performances can also be set, and the higher the alarm level, the faster and more the CPU frequency reduction is, so as to avoid excessive power consumption of the server causing system downtime.

[0072] It should be noted that for the BMC detection abnormality alarm, the server power consumption data constraint can be set according to the deployment requirements of the data center, that is, the server power consumption data constraint can be written into the BMC so that the BMC can compare all the collected power consumption data with the power consumption data constraint to achieve real-time power consumption limitation. Among them, all the power consumption data acquired by the BMC includes the power consumption data of the PSU, the power consumption data of key components, the power consumption data of the processor, the power consumption data of the PCH, and the power consumption data of the sensor, etc.

[0073] In this embodiment, by setting up a logic circuit in the power consumption monitoring system, adding early warning mechanisms such as overcurrent and overheating protection of the server, as well as a power consumption limiting function, it is possible to not only avoid power outages and downtime of the server under abnormal circumstances, but also ensure the efficient and stable operation of the server, thereby ensuring the stable operation of the data center.

[0074] In a complete embodiment, if Figure 8As shown, the power consumption monitoring system includes a CPU, a PCH, a BMC, a PSU / hot swap controller (Hot Swap Controller, HSC), key components, and sensors, etc., wherein the PSU / HSC is connected to the power supply device VR14-1 through a power consumption monitoring circuit, the power supply device VR14-1 is connected to the SVID bus0 interface of the CPU through the SVID bus, the key components are connected to the power supply devices VR14-2, 3... through the power consumption monitoring circuit, the power supply devices VR14-2, 3... are connected to the SVID bus1 interface of the CPU through the SVID bus, the Pcode unit of the CPU is connected to the BMC through the PECI bus, the SML0 interface of the PCH is connected to the SVID bus0 interface of the BMC, and the sensor is connected to the SVID of the BMC. bus2 interface. In addition, the SM_Alert# pin of PSU / HSC is connected to the input end of the logic circuit, the GPIO interface of BMC is connected to the input end of the logic circuit, the output end of the logic circuit is connected to the CPU, and the SM_Alert# pin of PSU / HSC is also connected to the GPIO interface of PCH and the GPIO interface of BMC, so that the warning signal output by PSU / HSC can be synchronized to PCH and BMC, so that PCH and BMC perform corresponding recording and feedback work.

[0075] In addition, it should be noted that SVID bus0 mounts the CPU main power supply device VR14-1, SVID bus1 mounts other power supply devices VR14-2 or VR14-3, and so on, up to 16 devices.

[0076] For relevant details, please refer to the relevant description of the power consumption monitoring system in the above embodiments, which will not be repeated here.

[0077] In one embodiment, a server is provided, which includes the power consumption monitoring system in any of the above embodiments, and the power consumption monitoring system includes: a processor, a first monitored device and a baseboard management controller BMC; wherein the processor communicates with the first monitored device through a serial voltage identification SVID bus, and the processor communicates with the BMC through a platform environment control interface PECI bus; the processor is used to obtain first power consumption data of the first monitored device through the SVID bus, and send the first power consumption data and second power consumption data of the processor to the BMC through the PECI bus.

[0078] The server in this embodiment has a built-in power consumption monitoring system. The processor in the power consumption monitoring system obtains the power consumption data of the first monitored device in real time through the SVID bus. Compared with the BMC obtaining the power consumption data through the SMBus bus, since the transmission frequency of the SVID bus is much greater than the transmission frequency of the SMBus bus, the acquisition rate of the power consumption data can be greatly improved, the real-time performance of the power consumption monitoring can be improved, and the accuracy of the power consumption monitoring can be improved.

[0079] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0080] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A power consumption monitoring system, characterized in that: include: A processor, a first monitored device, a second monitored device, a baseboard management controller BMC and a logic circuit; The first monitored device includes at least one of a power supply unit PSU, a power supply device VR and key components; the second monitored device includes at least one of a platform control hub PCH and a sensor; The processor communicates with the first monitored device via a serial voltage identification SVID bus, and the processor communicates with the BMC via a platform environment control interface PECI bus; the second monitored device communicates with the BMC via a system management SMBus bus; the PSU is also connected to the PCH and the BMC; The processor is configured to obtain first power consumption data of the first monitored device through the SVID bus, and send the first power consumption data and second power consumption data of the processor to the BMC through the PECI bus; The BMC is used to obtain third power consumption data of the second monitored device through the SMBus bus; The logic circuit is used to send a frequency reduction signal to the processor when receiving the first warning information output by the PSU or the second warning signal output by the BMC; The processor is configured to perform a frequency reduction operation when receiving the frequency reduction signal; The PSU is used to output the first warning information to the PCH and the BMC.

2. The power consumption monitoring system according to claim 1, characterized in that: The power supply device VR is connected to the processor via the SVID bus; The power supply unit PSU is connected to the processor through the power supply device VR; The key component is connected to the processor via the power supply device VR.

3. The power consumption monitoring system according to claim 2, characterized in that: The power consumption monitoring system further comprises a first power consumption monitoring circuit and a second power consumption monitoring circuit; the power supply device VR comprises a first power supply device VR and a second power supply device VR; The PSU is connected to the processor via the first power consumption monitoring circuit and the first power supply device VR in sequence, and the processor communicates with the first power supply device VR via the SVID bus; The key component is connected to the processor via the second power consumption monitoring circuit and the second power supply device VR in sequence, and the processor communicates with the second power supply device VR via the SVID bus.

4. The power consumption monitoring system according to claim 3, characterized in that: The first power consumption monitoring circuit includes a first precision resistor and a first amplifier; the first output end of the PSU is connected to the first end of the first precision resistor, the second end of the first precision resistor is connected to the input end of the first amplifier, and the output end of the first amplifier is connected to the input end of the first power supply device VR; The second power consumption monitoring circuit includes a second precision resistor and a second amplifier; the output end of the key component is connected to the first end of the second precision resistor, the second end of the second precision resistor is connected to the input end of the second amplifier, and the output end of the second amplifier is connected to the input end of the second power supply device VR.

5. The power consumption monitoring system according to claim 1, characterized in that: The second output terminal of the PSU is connected to the first input terminal of the logic circuit, the output terminal of the BMC is connected to the second input terminal of the logic circuit, and the output terminal of the logic circuit is connected to the processor.

6. The power consumption monitoring system according to claim 5, characterized in that: The PSU is configured to output a first warning signal through a second output terminal of the PSU when it is determined that the power consumption exceeds a first preset threshold; The BMC is used to output the second warning signal through the output end of the BMC when it is determined that the power consumption exceeds a second preset threshold; wherein the second preset threshold is smaller than the first preset threshold.

7. The power consumption monitoring system according to claim 6, characterized in that: The BMC is used to determine whether to output the second warning signal according to a magnitude relationship between the first power consumption data and / or the second power consumption data and the second preset threshold.

8. The power consumption monitoring system according to claim 6, characterized in that: The BMC is used to determine whether to output the second warning signal according to the relationship between the power consumption data of the PSU in the first power consumption data and the second preset threshold.

9. The power consumption monitoring system according to claim 5, characterized in that: The second output terminal of the PSU is also connected to the BMC.

10. A server, characterized in that: The invention comprises a power consumption monitoring system as claimed in any one of claims 1 to 9.

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