A system-level packaging structure and preparation method thereof

Abstract

The present invention provides a system-level packaging structure and a preparation method thereof, wherein the three-dimensional packaging structure comprises: a redistribution layer, a TSV bridging substrate, a first type chip, a second type chip, a first plastic encapsulation material layer, a PCB board, a third type chip and a second plastic encapsulation material layer; wherein the TSV bridging substrate and the first type chip are bonded and arranged on the upper surface of the redistribution layer; the second type chip is bonded and arranged on the upper surface of the TSV bridging substrate; the PCB board is bonded and arranged on the lower surface of the redistribution layer; and the third type chip is bonded and arranged on the lower surface of the PCB board. The system-level packaging structure and the preparation method thereof provided by the present invention can solve the problems of high cost and low process yield of the packaging structure used in the existing packaging technology, and the need to go through multiple different manufacturing plants during preparation, which is not conducive to rapid product development.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging, and in particular to a system-level packaging structure and a preparation method thereof. Background Art

[0002] As end users want their devices to be smaller, faster, more energy-efficient and more powerful, packaging more functions in a single wafer will inevitably become an important trend in the future of semiconductor packaging. From an architectural perspective, SiP (System In a Package) integrates multiple functional chips, including processors, memory and other functional wafers, into a package to form a standard package that implements specific functions. After forming a standard package, it needs to be interconnected with power modules and passive devices (for example, LEDs or vertical emitting lasers) through a printed circuit board (PCB).

[0003] In SIP packaging, for the connection of chips with different precisions (for example, logic chips, memory chips, power chips and other chips with different process requirements), chips with low solder joint density are directly connected to the PCB board, chips with medium solder joint density are connected to the PCB board through RDL (redistribution layer), and high-density chips are connected to RDL with the help of TSV bridge substrate (bridge substrate with silicon through via), and then connected to PCB by RDL; finally, different chips are finally interconnected with PCB, but PCB is usually made of plastic ester material, the larger its size, the easier it is to produce warping stress deformation, This causes yield loss, and from the initial chip manufacturing to the final bonding and connection of various devices on the PCB to form a complete SIP device, it usually takes three semiconductor production processes. The first process: chip production; the second process: chips with high and / or medium solder joint density are interconnected through a redistribution layer and then packaged; the third process: low-density chips and the redistribution layer bonded with high-density chips are interconnected through a PCB; these three processes are usually manufactured separately by three-level manufacturing plants, the process procedures are cumbersome, the interaction processes between factories at all levels are cumbersome, communication is poor, and the product verification cycle is long, which is not conducive to rapid product development. Summary of the invention

[0004] In view of the shortcomings of the prior art described above, an object of the present invention is to provide a system-level packaging structure and a preparation method thereof, so as to solve the problems that the packaging structure used in the existing SIP packaging technology has high cost, low process yield, and needs to go through multiple different manufacturing plants during preparation, which is not conducive to rapid product development.

[0005] To achieve the above object, the present invention provides a method for preparing a system-level packaging structure, the method comprising:

[0006] S1, providing a temporary carrier, and forming a redistribution layer on the upper surface of the temporary carrier;

[0007] S2, providing at least one TSV bridging substrate and at least one first type chip, and bonding the TSV bridging substrate and the first type chip to the upper surface of the redistribution layer respectively;

[0008] S3, providing at least one second type chip, and bonding the second type chip to the TSV bridging substrate, wherein the solder joint density of the second type chip is higher than that of the first type chip;

[0009] S4, forming a first plastic packaging material layer on the upper surface of the redistribution layer;

[0010] S5, removing the temporary carrier, providing a plurality of PCB boards, and bonding the plurality of PCB boards to the lower surface of the redistribution layer;

[0011] S6, providing a plurality of third-type chips, and bonding the plurality of the third-type chips to a plurality of the PCB boards, wherein the solder joint density of the third-type chips is lower than the solder joint density of the first-type chips;

[0012] S7, forming a second plastic packaging material layer on the lower surface of the redistribution layer.

[0013] Optionally, after S4 and before S5, the preparation method further includes:

[0014] S41, thinning the first plastic encapsulation material layer until the upper surface of the first type chip and / or the upper surface of the second type chip are exposed.

[0015] Optionally, after S4 and before S5, the preparation method further includes:

[0016] S42, disposing a heat sink on the upper side of the redistribution layer, wherein the heat sink encapsulates a plurality of the first type chips and a plurality of the second type chips therein.

[0017] Optionally, after S7, the preparation method further includes:

[0018] S8, forming a groove in the second plastic packaging material layer, wherein the groove exposes a portion of the surface of the PCB board;

[0019] S9, providing at least one connection plug-in, and bonding the connection plug-in to the PCB board in the groove.

[0020] Optionally, in S2, the number of the TSV bridging substrates is greater than or equal to 2; in S3, the number of the second type chips is greater than or equal to 2; wherein at least one of the second type chips is bonded to at least two of the TSV bridging substrates at the same time.

[0021] Optionally, in S6, at least one chip of the third type is bonded to at least two PCB boards at the same time.

[0022] The present invention also provides a system-level packaging structure, the system-level packaging structure comprising:

[0023] A redistribution layer, at least one TSV bridge substrate, at least one first type chip, at least one second type chip, a first plastic packaging material layer, a plurality of PCB boards, a plurality of third type chips and a second plastic packaging material layer, wherein the solder joint density of the first type chip is less than the solder joint density of the second type chip but greater than the solder joint density of the third type chip; wherein,

[0024] The TSV bridging substrate and the first type chip are bonded and arranged on the upper surface of the redistribution layer;

[0025] The second type chip bonding is arranged on the upper surface of the TSV bridging substrate;

[0026] The first plastic encapsulation material layer is formed on the upper surface of the redistribution layer, and covers the first type chip and the second type chip;

[0027] The PCB board is bonded to the lower surface of the redistribution layer;

[0028] The third type chip is bonded on the lower surface of the PCB board;

[0029] The second plastic packaging material layer is formed on the lower surface of the redistribution layer and covers the third type chip.

[0030] Optionally, the system-level packaging structure further includes a heat sink, which is disposed on an upper surface of the redistribution layer and encapsulates the first plastic packaging material layer therein.

[0031] Optionally, the system-level packaging structure further includes a connecting plug-in, and a groove exposing a portion of the surface of the PCB board is formed in the second plastic packaging material layer; the connecting plug-in is arranged in the groove and bonded to the PCB board.

[0032] Optionally, the number of the TSV bridging substrates is greater than or equal to 2, the number of the second type chips is greater than or equal to 2, and at least one of the second type chips is bonded to at least two of the TSV bridging substrates at the same time.

[0033] Optionally, at least one of the third type chips is bonded to at least two of the PCB boards at the same time.

[0034] As described above, the system-level packaging structure and the preparation method thereof of the present invention,

[0035] 1. Using several small PCB boards instead of a whole PCB board can increase the production yield of PCB boards, reduce preparation costs, and increase the packaging process yield without affecting the interconnection function;

[0036] 2. The redistribution layer is used as an interconnection layer to connect various chips. On both sides of the redistribution layer, the chips with medium solder joint density are directly connected to the redistribution layer, the chips with high solder joint density are connected to the redistribution layer through several small TSV bridge substrates, and the chips with low solder joint density are connected to the redistribution layer through several small PCB boards. The structure occupies a small space and has high space utilization;

[0037] 3. Since small pieces of PCB boards are used instead of whole PCB boards, each small piece of PCB board can be directly packaged and bonded with the redistribution layer. Moreover, after each small piece of PCB board is bonded with the redistribution layer, the low solder joint density chip that needs to be directly connected to the PCB board can be directly bonded to the PCB. The interconnection process of low-density chips, medium-density chips, and high-density chips is completed in the same manufacturing plant, reducing production links, reducing production costs, and improving product development efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 Shown is a flow chart of a method for preparing the system-level packaging structure of the present invention.

[0039] Figure 2 It is a schematic diagram of the structure after forming the redistribution layer according to the present invention.

[0040] Figure 3 It is a schematic structural diagram of bonding the first type chip and the TSV bridge substrate to the redistribution layer according to the present invention.

[0041] Figure 4 It is a schematic diagram of the structure after the second type chip is bonded to the TSV bridge substrate according to an embodiment of the present invention.

[0042] Figure 5 It is a schematic diagram of the structure after the first plastic packaging material layer is formed according to the present invention.

[0043] Figure 6 It is a schematic diagram of the structure after the first plastic packaging material layer is thinned according to the present invention.

[0044] Figure 7It is a schematic diagram of the structure after the heat dissipation plate is formed according to the present invention.

[0045] Figure 8 It is a schematic diagram of the structure after the temporary carrier plate is removed according to the present invention.

[0046] Fig. 9 It is a schematic diagram of the structure after the PCB board and the redistribution layer of the present invention are bonded.

[0047] Fig.10 It shows a schematic diagram of the structure after the third type chip of the present invention is bonded to the PCB board.

[0048] Fig.11 It is a schematic diagram of the structure after the second plastic packaging material layer is formed according to the present invention.

[0049] Fig.12 It is a schematic diagram of the structure after the connection plug-in is formed according to the present invention.

[0050] Component number description

[0051] 10 System-level package structure

[0052] 110 Temporary carrier board

[0053] 111 Release layer

[0054] 100 Rewiring Layer

[0055] 200 TSV bridge substrate

[0056] 201-203 First TSV bridge substrate-third TSV bridge substrate

[0057] 300 Type 1 Chip

[0058] 400 Type II Chip

[0059] 401~404 4 second type chips with different solder joint densities

[0060] 500 First plastic material layer

[0061] 600 PCB board

[0062] 601~603 The first PCB board~the third PCB board

[0063] 700 Type III Chip

[0064] 701~703 3 types of chips with different solder joint densities

[0065] 710 Connection Plug-in

[0066] 800 Second plastic material layer

[0067] 900 Radiator DETAILED DESCRIPTION

[0068] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0069] See also Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0070] This embodiment provides a method for preparing a system-level packaging structure 10, such as Figure 1 As shown, the method for preparing the system-level package structure 10 includes: step S1) to step S7). Specifically, it also includes step S8) to step S9).

[0071] Step S1): Provide a temporary carrier 110, such as Figure 2 As shown, a redistribution layer 100 is formed on the upper surface of the temporary carrier 110 .

[0072] In this embodiment, the temporary carrier 110 may be a glass carrier, a ceramic carrier, etc., and the redistribution layer 100 may be a single-layer redistribution layer or a multi-layer redistribution layer.

[0073] Specifically, Figure 2 As shown, before forming the redistribution layer 100 on the upper surface of the temporary carrier 110 , a release layer 111 is formed on the upper surface of the temporary carrier 110 .

[0074] In this embodiment, the upper surface of the release layer 111 is equivalent to the upper surface of the temporary carrier 110, that is, the redistribution layer 100 is formed on the upper surface of the release layer 111; the release layer 111 can be formed on the temporary carrier 110 by, for example, spin coating; the release layer 111 can be formed by an adhesive, such as ultraviolet glue, photothermal conversion glue and other types of adhesives; the release layer 111 can be decomposed under the action of light and heat, so that the temporary carrier 110 can be separated from the overlying structure formed in subsequent steps.

[0075] Step S2) to Step S3): First, Figure 3As shown, at least one TSV bridge substrate 200 and at least one first type chip 300 are provided, and the TSV bridge substrate 200 and the first type chip 300 are bonded to the upper surface of the redistribution layer 100, respectively. Figure 4 As shown, at least one second type chip 400 is provided, and the second type chip 400 is bonded to the TSV bridging substrate 200 , wherein the solder joint density of the second type chip 400 is higher than the solder joint density of the first type chip 300 .

[0076] In this embodiment, the first type chip 300 can be, for example, a capacitor die, a resistor die, an inductor die, etc. The solder joint density range of this type of die (between 1μm and 20μm) matches the line width and line spacing of the RDL layer (the line width and line spacing of the RDL layer is usually between 1um and 20um, for example, a line spacing of 2um). Therefore, the first type chip 300 can be directly connected to the RDL layer.

[0077] The second type chip 400 can be, for example, a logic die (CPU, GPU, PCIE, etc.), a memory die (DRAM, SRAM, etc.), an input and output (IO) die, etc. It can be seen from the category of the second type chip that it has a higher solder point density than the first type chip. When in use, the second type chip is suitable for first being connected to a TSV bridge substrate with a small line width and small line spacing (the line width and line spacing of the TSV bridge substrate is usually less than 1μm, such as a small one of 0.2μm and a large one of 0.8μm), and then connected to the redistribution layer 100 through the TSV bridge substrate. Therefore, the solder point density range of the second type chip 400 is less than 1μm.

[0078] It should be noted that the manufacturing process yield of a large-sized TSV bridge substrate 200 is low and the cost is high. Therefore, in this embodiment, multiple smaller TSV bridge substrates 200 are preferably used. For example, the number of TSV bridge substrates 200 is 3 and the number of second-type chips 400 is 4. Figure 4 As shown in FIG. 1 , the solder joint densities of the four second type chips 401, 402, 403 and 404 are different (the solder joint density of 401 is the same as that of 402, the solder joint density of 403 is the same as that of 404, and the solder joint density of 401 is lower than that of 403). The three TSV bridge substrates are the first TSV bridge substrate 201, the second TSV bridge substrate 202 and the third TSV bridge substrate 203. Moreover, the through silicon via (TSV) density in the first bridge substrate 201 is higher than that in the third bridge substrate 203, and the second bridge substrate 202 has two through silicon via densities (equivalent to the through silicon via densities in 201 and 203, respectively). As shown in FIG. 1 , Figure 4As shown, the first bridging substrate 201 is bonded to 401 with a lower solder point density, the third bridging substrate 201 is bonded to 404 with a higher solder point density, and both ends of the second bridging substrate 202 are respectively bonded to 403 and 404 with different solder point densities. At this time, the second bridging substrate 202 serves as a bridge for high-density signal transmission connection between 403 and 404, which can meet the design and use requirements, and compared with using a large-size bridging substrate, it can significantly reduce production costs and improve process yield.

[0079] Step S4): Figure 5 As shown, a first plastic encapsulation material layer 500 is formed on the upper surface of the redistribution layer 100 .

[0080] In this embodiment, the method of forming the first plastic packaging material layer 500 includes but is not limited to compression molding, molding, liquid sealing molding, vacuum lamination and spin coating, and its materials include but are not limited to polyimide, silicone and epoxy resin.

[0081] Specifically, after step S4), the preparation method further includes: step S41) to step S42).

[0082] Step S41): Figure 6 As shown, the first molding material layer 500 is thinned until the upper surface of the first type chip 300 and / or the upper surface of the second type chip 400 are exposed.

[0083] In this embodiment, the method of thinning the first plastic encapsulation material layer 500 includes but is not limited to a grinding process (i.e., backside grinding). The upper surface of the thinned first plastic encapsulation material layer 500 exposes the upper surface of the chip (the figure shows that the upper surface of the second type chip is exposed). It should be noted that in actual applications, after bonding, the upper surface of each first type chip and second type chip may be at different levels. Therefore, the first plastic encapsulation material layer 500 only needs to be thinned to the highest chip surface.

[0084] Step S42): Figure 7 As shown, a heat sink 900 is disposed on the upper side of the redistribution layer 100 , wherein the heat sink 900 encloses a plurality of the first type chips 300 and a plurality of the second type chips 400 therein, and the heat generated by the chips is conducted and dissipated by the heat sink 900 .

[0085] Step S5) to Step S6): First, Figure 8 As shown, the temporary carrier 110 is removed, and several PCB boards 600 are provided, such as Fig. 9 As shown, several PCB boards 600 are bonded to the lower surface of the redistribution layer 100. Then, as shown in FIG. Fig.10As shown, a plurality of third type chips 700 are provided, and the plurality of third type chips 700 are bonded to a plurality of PCB boards 600 , wherein the solder joint density of the third type chips 700 is lower than the solder joint density of the first type chips 300 .

[0086] In this embodiment, when removing the temporary carrier 110, first, heating and / or light irradiation can be used to reduce the viscosity of the release layer 111 to remove the temporary carrier 110. Then, treatment methods such as tearing and light irradiation can be used to peel off the release layer 111. Of course, the laser peeling process can also be used directly to peel off the laser peeling and the redistribution layer 100 from each other. The laser peeling process directly vaporizes the release layer 111 to achieve the effect of peeling off the temporary carrier 110 and the redistribution layer 100. The processing precision is high and the impurities retained are small.

[0087] In this embodiment, the third type chip 700 can be, for example, a power module chip or a passive device (such as a pulse width modulation chip). Due to its low solder joint density, it is suitable for being first connected to a PCB board with a large line width and a large line spacing (the line width and line spacing of the PCB board is usually greater than 20μm, such as 50μm, 100μm), and then connected to the redistribution layer 100 through the PCB board. Therefore, the solder joint density range of the third type chip 700 is greater than 20μm; in the traditional packaging structure, the first type chip, the second type chip and the third type chip are always ultimately interconnected through a large PCB board, but since the large-sized PCB board is prone to warping, this can easily affect the process yield. In this embodiment, such a packaging structure is no longer used, and the redistribution layer 100 is used instead as a signal connection bridge between the first type chip, the second type chip and the third type chip 700. This does not affect the interconnection requirements between the chips, and the redistribution layer can provide a shorter signal transmission distance compared to the PCB board, saving space and improving signal transmission quality while meeting the device design indicators. Furthermore, the use of multiple smaller PCB boards to interconnect the third type chip with the redistribution layer 100 can solve the problem of warping caused by large PCB boards. At the same time, after packaging the first type chip, the second type chip, and the redistribution layer, multiple small PCB boards can be directly bonded to the redistribution layer in the same factory. After bonding, all packaging steps are completed by bonding the third type chip to the PCB board. This can save the packaging process flow and does not require additional material delivery to other factories to complete the operation, thereby simplifying the production process.

[0088] As an example, the number of PCB boards 600 is 3 and the number of third-type chips 700 is 3. Fig.10As shown, the solder joint densities of the three third-type chips 701, 702 and 703 are different (the solder joint density of 702 is the same as that of 703, and the solder joint density of 701 is higher than that of 703, but the solder joint densities of 701, 702 and 703 are all greater than 20 μm, that is, 701, 702 and 703 all need to rely on PCB to connect with the RDL layer; the three PCB boards are the first PCB board 601, the second PCB board 602 and the third PCB board 603; among them, the first PCB board 601 has two different solder joint densities, the part with high solder joint density is bonded to 701, the part with low solder joint density is bonded to 702, the second PCB board 602 is also bonded to 702, and the third PCB board 603 is bonded to 703. The three PCB boards with different solder joint densities are bonded to the chips with different solder joint densities respectively, which can not only meet the design requirements of interconnecting the third type chip with the first type chip and the second type chip, but also avoid the problems of high cost and low yield of large PCB boards.

[0089] Step S7): Fig.11 As shown, a second plastic encapsulation material layer 800 is formed on the lower surface of the redistribution layer 100 .

[0090] In this embodiment, the method of forming the second plastic packaging material layer 800 includes but is not limited to compression molding, molding, liquid sealing molding, vacuum lamination and spin coating, and its materials include but are not limited to polyimide, silicone and epoxy resin.

[0091] Step S8) to Step S9): Fig.12 As shown, first, a groove is formed in the second plastic packaging material layer, wherein the groove exposes a portion of the surface of the PCB board; then, at least one connecting plug-in 710 is provided, and the connecting plug-in is bonded to the PCB board in the groove.

[0092] In this embodiment, for example, a groove is formed by laser cutting, and the bottom of the groove is the lower surface of the PCB board, and the groove at least exposes part of the solder joints of the PCB board so that the connecting plug-in is connected to the PCB board. The first type chip, the second type chip and the third type chip in the system-level packaging structure 10 are connected to the external power supply through the connecting plug-in 710 to supply the working voltage.

[0093] Accordingly, the present embodiment further provides a system-level packaging structure 10. As shown in the figure, the system-level packaging structure 10 includes: a redistribution layer 100, at least one TSV bridging substrate 200, at least one first type chip 300, at least one second type chip 400, a first plastic packaging material layer 500, a plurality of PCB boards 600, a plurality of third type chips 700 and a second plastic packaging material layer 800, wherein the solder joint density of the first type chip 300 is less than the solder joint density of the second type chip 400 but greater than the solder joint density of the third type chip 700; wherein the TSV bridging substrate 200 and the first type The chip 300 is bonded to the upper surface of the redistribution layer 100; the second type chip 400 is bonded to the upper surface of the TSV bridging substrate 200; the first plastic encapsulation material layer 500 is formed on the upper surface of the redistribution layer 100, covering the first type chip 300 and the second type chip 400; the PCB board 600 is bonded to the lower surface of the redistribution layer 100; the third type chip 700 is bonded to the lower surface of the PCB board 600; the second plastic encapsulation material layer 800 is formed on the lower surface of the redistribution layer 100, covering the third type chip 700.

[0094] In this embodiment, the wiring density of the redistribution layer 100 is lower than the wiring density of the TSV bridge substrate 200. When the number of the TSV bridge substrate 200 and the second type chip 400 is greater than or equal to two, the second type chip 400 can communicate with each other through the TSV bridge substrate 200 with different wiring densities, with short lines and excellent communication quality, which can increase the yield and reduce the manufacturing cost. The wiring density of the PCB board 600 is lower than the wiring density of the redistribution layer 100. The third type chip 700 can communicate with other chips through the PCB board 600 with different solder joint densities, which can increase the yield and reduce the manufacturing cost.

[0095] It should be noted that the present embodiment only illustrates the situation in which the first type chip 300 and the second type chip 400 are located on the upper side of the redistribution layer 100, and the third type chip 700 is located on the lower side of the redistribution layer 100; in the actual packaging structure design, the first type chip can be located either on the upper side or on the lower side of the redistribution layer, the second type chip can be located either on the upper side or on the lower side of the redistribution layer, and the third type chip can be located either on the upper side or on the lower side of the redistribution layer.

[0096] Specifically, the number of the TSV bridging substrates 200 is greater than or equal to 2, the number of the second type chips 400 is greater than or equal to 2, and at least one second type chip 400 is bonded to at least two of the TSV bridging substrates 200 at the same time.

[0097] In this embodiment, Figure 4 As shown, when the number of TSV bridging substrates 200 and second type chips 400 is greater than two, the second type chip 400 can be bridged on two TSV bridging substrates 200, and the TSV bridging substrate 200 connected to the bridged second type chip 400 can have only one TSV through-hole density or multiple different TSV through-hole densities.

[0098] Specifically, at least one of the third type chips 700 is bonded to at least two of the PCB boards 600 at the same time.

[0099] In this embodiment, Fig.10 As shown, the third type chip can be bridged between two PCB boards, and the PCB board connected to the bridged third type chip can have only one solder joint density or multiple different solder joint densities.

[0100] Specifically, the system-level packaging structure 10 also includes a heat sink 900, which is arranged on the upper surface of the redistribution layer 100, and the first plastic packaging material layer 500 is wrapped therein. The heat generated by the chip is conducted and dissipated by the heat sink 900. It should be noted that the heat sink 900 can be arranged only on the upper side of the redistribution layer 100, or only on the lower side of the redistribution layer 100, or on both the upper and lower sides of the redistribution layer 100.

[0101] Specifically, the system-level packaging structure 10 further includes a connection plug-in 710 , and a groove exposing a portion of the surface of the PCB board is formed in the second plastic packaging material layer 800 ; the connection plug-in 710 is disposed in the groove and bonded to the PCB board 600 .

[0102] In this embodiment, the connection plug-in 710 is used to connect to a voltage source, for example, to supply system operating voltage to the system-level package structure 10 . The number of the connection plug-in 710 may also be multiple to meet more diverse system voltage requirements.

[0103] In summary, the system-level packaging structure and preparation method of the present invention: 1. Using a plurality of small PCB boards to replace a whole PCB board can increase the production yield of the PCB board without affecting the interconnection function, reduce the preparation cost, and increase the packaging process yield; 2. Using the redistribution layer as the interconnection layer to connect various chips, on both sides of the redistribution layer, the chip with medium solder point density is directly connected to the redistribution layer, the chip with high solder point density is connected to the redistribution layer through a plurality of small TSV bridge substrates, and the chip with low solder point density is connected to the redistribution layer through a plurality of TSV bridge substrates. Small pieces of PCB boards are connected to the redistribution layer, and the structure occupies a small space and has a high space utilization rate; 3. Since small pieces of PCB boards are used instead of whole pieces of PCB boards, each small piece of PCB board can be directly packaged and bonded with the redistribution layer, and after each small piece of PCB board is bonded to the redistribution layer, the low solder joint density chip that needs to be directly connected to the PCB board can be directly bonded to the PCB. The interconnection process of low-density chips, medium-density chips, and high-density chips is completed in the same manufacturing plant, reducing production links, reducing production costs, and improving product development efficiency.

[0104] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a system-level packaging structure, characterized in that: The preparation method comprises: S1, providing a temporary carrier, and forming a redistribution layer on the upper surface of the temporary carrier; S2, providing at least one TSV bridging substrate and at least one first type chip, and bonding the TSV bridging substrate and the first type chip to the upper surface of the redistribution layer respectively; S3, providing at least one second type chip, and bonding the second type chip to the TSV bridging substrate, wherein the solder joint density of the second type chip is higher than that of the first type chip; S4, forming a first plastic encapsulation material layer on the upper surface of the redistribution layer, wherein the first plastic encapsulation material layer covers the first type chip and the second type chip; S5, removing the temporary carrier, providing a plurality of PCB boards, and bonding the plurality of PCB boards to the lower surface of the redistribution layer; S6, providing a plurality of third-type chips, and bonding the plurality of the third-type chips to a plurality of the PCB boards, wherein the solder joint density of the third-type chips is lower than the solder joint density of the first-type chips; S7, forming a second plastic encapsulation material layer on the lower surface of the redistribution layer, wherein the second plastic encapsulation material layer covers the third type chip.

2. The method for preparing a system-level packaging structure according to claim 1, characterized in that: After S4 and before S5, the preparation method further includes: S41, thinning the first plastic encapsulation material layer until the upper surface of the first type chip and / or the upper surface of the second type chip are exposed.

3. The method for preparing a system-level packaging structure according to claim 1, characterized in that: After S4 and before S5, the preparation method further includes: S42, disposing a heat sink on the upper side of the redistribution layer, wherein the heat sink encapsulates a plurality of the first type chips and a plurality of the second type chips therein.

4. The method for preparing a system-level packaging structure according to claim 1, characterized in that: After S7, the preparation method further includes: S8, forming a groove in the second plastic packaging material layer, wherein the groove exposes a portion of the surface of the PCB board; S9, providing at least one connection plug-in, and bonding the connection plug-in to the PCB board in the groove.

5. The method for preparing a system-level packaging structure according to claim 1, characterized in that: In S2, the number of the TSV bridging substrates is greater than or equal to 2; in S3, the number of the second type chips is greater than or equal to 2; wherein at least one of the second type chips is bonded to at least two of the TSV bridging substrates at the same time.

6. The method for preparing a system-level packaging structure according to claim 1, characterized in that: In S6), at least one of the third type chips is bonded to at least two of the PCB boards at the same time.

7. A system-level packaging structure, characterized in that: The system-level packaging structure comprises: A redistribution layer, at least one TSV bridge substrate, at least one first type chip, at least one second type chip, a first plastic packaging material layer, a plurality of PCB boards, a plurality of third type chips and a second plastic packaging material layer, wherein the solder joint density of the first type chip is less than the solder joint density of the second type chip but greater than the solder joint density of the third type chip; wherein, The TSV bridging substrate and the first type chip are bonded and arranged on the upper surface of the redistribution layer; The second type chip bonding is arranged on the upper surface of the TSV bridging substrate; The first plastic packaging material layer is formed on the upper surface of the redistribution layer, and covers the first type chip and the second type chip; The PCB board is bonded to the lower surface of the redistribution layer; The third type chip is bonded on the lower surface of the PCB board; The second plastic packaging material layer is formed on the lower surface of the redistribution layer and covers the third type chip.

8. The system-level packaging structure according to claim 7, characterized in that: The system-level packaging structure further includes a heat sink, which is disposed on the upper surface of the redistribution layer and encapsulates the first plastic packaging material layer therein.

9. The system-level packaging structure according to claim 7, characterized in that: The system-level packaging structure also includes a connecting plug-in, and a groove exposing a portion of the surface of the PCB board is formed in the second plastic packaging material layer; the connecting plug-in is arranged in the groove and bonded to the PCB board.

10. The system-level packaging structure according to claim 7, characterized in that: The number of the TSV bridging substrates is greater than or equal to 2, the number of the second type chips is greater than or equal to 2, and at least one of the second type chips is bonded to at least two of the TSV bridging substrates at the same time.

11. The system-level packaging structure according to claim 7, characterized in that: At least one of the third type chips is bonded to at least two of the PCB boards at the same time.

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