Semiconductor structure and manufacturing method thereof

Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a channel layer, a barrier layer, a source electrode, a gate electrode, a drain electrode and a covering layer. Wherein the channel layer is located on the substrate, the barrier layer is located on the channel layer, the source electrode, the gate electrode and the drain electrode are respectively located on the barrier layer, and the covering layer covers the source electrode and the drain electrode except above the source electrode and the drain electrode.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a manufacturing method thereof, and in particular to a structure of a high electron mobility transistor (HEMT) and a manufacturing method thereof. Background Art

[0002] In recent years, due to the increasing demand for high-frequency and high-power products, semiconductor power devices made of gallium nitride, such as aluminum gallium nitride / gallium nitride (AlGaN / GaN), have been widely used in high-power semiconductor structures, especially in RF and power applications, due to their wide band gap and high-speed electron movement, which can achieve very fast switching speeds and can operate in high-frequency, high-power and high-temperature working environments. Traditionally, high-electron mobility transistors use III-V semiconductor stacks to form a heterojunction at their interface. Due to the band bending at the heterojunction, a potential well is formed deep in the conduction band bending, and a two-dimensional electron gas (2DEG) is formed in the potential well.

[0003] Generally speaking, a high electron mobility transistor is a normally-on (D-mode) device, or a depletion mode device, which requires an additional negative bias to turn off the device. In addition to being relatively inconvenient to use, it also limits the scope of use of the device. On the other hand, another enhancement-mode high electron mobility transistor has been proposed, which uses fluorine ion bombardment to destroy the lattice structure of the aluminum gallium nitride layer before forming a metal gate, or forms a recess in the aluminum gallium nitride layer by etching, and then epitaxy a gate stack structure of a gallium nitride layer with P-type impurities at the bottom of the recess, so as to achieve a normally-off (E-mode: Normally-off) device that can turn off the two-dimensional electron gas without applying an additional bias.

[0004] When manufacturing the above two types of semiconductor components, titanium / aluminum metal is usually used as the electrode material for the source electrode and the drain electrode in the component. The two electrode ends and the aluminum gallium nitride barrier layer must be subjected to a high-temperature heating treatment to form an ohmic contact between the electrode and the gallium nitride. If the alloy temperature is too low, it is difficult to form an ohmic contact between the electrode and the gallium nitride; conversely, if the alloy temperature is too high, due to the low melting point of the aluminum metal in the electrode, it is easy to produce gold overflow, affecting the yield of the manufacturing process. Figure 1AThe dotted lines show the conceptual diagram of the lateral and upper gold overflows caused by high temperature during the ohmic contact manufacturing process of the source electrode and the drain electrode in the conventional HEMT device manufacturing process. Figure 1B , Figure 1B This is a real microscopic magnified image of lateral gold overflow. If this lateral gold overflow occurs during the manufacturing process, it may cause a short circuit between the gate and the source during the subsequent gate electrode manufacturing process. On the other hand, Figure 1C The actual microscopic magnified image shows the gold overflow on the top. If gold overflow occurs on the top during the production process, it will affect the flatness of the metal layer surface, which is not conducive to the subsequent metal stacking production process.

[0005] In order to overcome the above problems, the industry is in urgent need of an innovative semiconductor structure and manufacturing method to improve the problems of gold overflow and insufficient flatness generated during the ohmic contact alloy manufacturing process, thereby improving the manufacturing process yield. Summary of the invention

[0006] The main purpose of the present invention is to provide an innovative semiconductor structure and manufacturing method to improve the problems of gold overflow and insufficient flatness in the existing ohmic contact alloy manufacturing process for heterostructure field effect transistors, thereby improving the yield of the manufacturing process.

[0007] To achieve the above-mentioned purpose, the present invention provides a semiconductor structure, which includes a substrate, a channel layer, a barrier layer, a source electrode, a gate electrode, a drain electrode and a covering layer. The channel layer is located on the substrate, the barrier layer is located on the channel layer, the source electrode, the gate electrode and the drain electrode are respectively located on the barrier layer, and the covering layer covers the source electrode and the drain electrode except for the top of the source electrode and the drain electrode.

[0008] In one embodiment, the present invention provides a semiconductor structure, wherein the source electrode and the drain electrode are selected from one of the group consisting of titanium, aluminum, nickel, and gold.

[0009] In one embodiment, the present invention provides a semiconductor structure, wherein the capping layer is selected from the group consisting of silicon nitride, silicon dioxide, and silicon oxynitride.

[0010] In one embodiment, the semiconductor structure provided by the present invention further includes a first metal layer disposed above the source electrode and the drain electrode and electrically connected to the source electrode and the drain electrode.

[0011] In one embodiment, the semiconductor structure provided by the present invention further comprises a liner layer. Except for the upper portion of the first metal layer, the liner layer covers a portion of the barrier layer, the capping layer, the first metal layer, and the gate electrode.

[0012] In one embodiment, the present invention provides a semiconductor structure, wherein the liner layer is selected from the group consisting of silicon nitride, silicon dioxide, aluminum nitride, and silicon carbide.

[0013] In one embodiment, the semiconductor structure provided by the present invention further comprises a through-hole structure and a second metal layer. The through-hole structure and the second metal layer are sequentially located above the first metal layer and are electrically connected to the first metal layer.

[0014] In one embodiment, the semiconductor structure provided by the present invention, wherein the material of the barrier layer comprises aluminum indium gallium nitride (Al x In y Ga (1-x-y) N), where 0≦x<1, 0≦x+y≦1.

[0015] In one embodiment, the semiconductor structure provided by the present invention further includes a two-dimensional electron gas, and the two-dimensional electron gas is disposed at an interface between the channel layer and the barrier layer.

[0016] In one embodiment, the present invention provides a semiconductor structure, wherein the substrate is selected from the group consisting of silicon, sapphire, and silicon carbide.

[0017] To achieve the above-mentioned purpose, the present invention provides a semiconductor structure, which includes a substrate, a channel layer, a barrier layer, a source electrode, a gate electrode, a drain electrode and a conductive covering layer. The channel layer is located on the substrate, the barrier layer is located on the channel layer, the source electrode, the gate electrode and the drain electrode are respectively located on the barrier layer, and the conductive covering layer covers the source electrode and the drain electrode.

[0018] In one embodiment, the present invention provides a semiconductor structure, wherein the conductive capping layer is selected from the group consisting of titanium nitride, titanium tungsten, titanium tungsten nitride, aluminum nitride, and stone mill.

[0019] In one embodiment, the semiconductor structure provided by the present invention further includes a first metal layer, which is disposed on the conductive covering layer above the source electrode and the drain electrode and is electrically connected to the conductive covering layer, the source electrode and the drain electrode.

[0020] To achieve the above-mentioned purpose, the present invention provides a method for manufacturing a semiconductor structure, which includes the following steps: sequentially forming a channel layer and a barrier layer on a substrate, and an interface between the channel layer and the barrier layer has a two-dimensional electron gas to form a source electrode and a drain electrode, which are respectively located on the barrier layer; forming a covering layer to cover the source electrode and the drain electrode; and heating the source electrode and the drain electrode so that the source electrode and the drain electrode form ohmic contacts with the barrier layer respectively.

[0021] In one embodiment, the manufacturing method of the semiconductor structure provided by the present invention also includes: forming a gate electrode on the barrier layer between the source electrode and the drain electrode; and forming a first metal layer in the area above the source electrode and the drain electrode, so that the first metal layer is electrically connected to the source electrode and the drain electrode respectively.

[0022] In one embodiment, the manufacturing method of the semiconductor structure provided by the present invention also includes: forming a pad layer to cover the first metal layer and a portion of the barrier layer, the covering layer, and the gate electrode; removing a portion of the pad layer above the first metal layer to expose the upper area of ​​the first metal layer; and high-temperature annealing the exposed upper area of ​​the first metal layer.

[0023] After referring to the accompanying drawings and the embodiments described below, a person skilled in the art will be able to understand other objects, technical means and implementation schemes of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1A A schematic diagram of the lateral and upper gold overflow of the source electrode and the drain electrode in a conventional high electron mobility transistor element;

[0025] Figure 1B This is an actual microscopic magnified image of lateral gold overflow in a conventional high electron mobility transistor element;

[0026] Figure 1C This is a real microscopic magnified image of the gold overflow on the top of a conventional high electron mobility transistor element; and

[0027] Figures 2 to 9 The following are the steps and structure diagram of the manufacturing process of a semiconductor structure according to one embodiment of the present invention.

[0028] Description of Reference Numerals

[0029] 10 Semiconductor structure

[0030] 100 substrates

[0031] 110 Nucleation layer

[0032] 120 Buffer layer

[0033] 130 Channel Layer

[0034] 132 Two-dimensional electron gas

[0035] 140 Barrier Layer

[0036] 150 Source electrode

[0037] 160 Drain electrode

[0038] 170 Overlay

[0039] 180 Gate electrode

[0040] 182 Field Effect Board

[0041] 190 First Metal Layer

[0042] 200 cushion layer

[0043] 210 Inner dielectric layer

[0044] 220 Dielectric layer

[0045] 230 Through-hole structure

[0046] 240 Second metal layer. DETAILED DESCRIPTION

[0047] The present invention will be explained below by way of examples, and the examples of the present invention are not intended to limit the present invention to any specific environment, application or special method as described in the examples. Therefore, the description of the examples is only for the purpose of explaining the present invention, and is not intended to limit the present invention. It should be noted that in the following examples and drawings, elements that are not directly related to the present invention have been omitted and are not shown, and the dimensional relationship between the elements in the drawings is only for easy understanding, and is not intended to limit the actual proportion.

[0048] See also Figure 2 , which shows a semiconductor structure and a manufacturing method thereof in one embodiment of the present invention, wherein a nucleation layer 110, a buffer layer 120, a channel layer 130 and a barrier layer 140 are sequentially formed on a substrate 100. The material of the substrate 100 may include silicon, sapphire, gallium nitride, silicon carbide, gallium arsenide, etc. The nucleation layer 110 is located above the substrate 100, and has a thickness of about tens of nanometers or hundreds of nanometers, and is used to reduce the lattice difference between the substrate 100 and the barrier layer 140. The nucleation layer 110 is, for example, a III-V material, including aluminum nitride, gallium nitride, or aluminum gallium nitride. The buffer layer 120 is located above the nucleation layer 110, and has a thickness of about several micrometers or tens of micrometers. Its material may be a III-V material, and is also used to reduce the lattice difference between the substrate 100 and the barrier layer 140 and reduce lattice defects. In this embodiment, the buffer layer 120 may include a single-layer structure or a multi-layer structure, such as a multi-layer super lattice stack (Super Lattice Multilayer) or a single-layer III-V semiconductor material, such as aluminum nitride, gallium nitride, or aluminum gallium nitride.

[0049] The channel layer 130 is formed on the buffer layer 120 and has a first energy gap. The barrier layer 140 is formed on the channel layer 130 and has a second energy gap, which is higher than the first energy gap. The lattice constant of the barrier layer 140 is smaller than that of the channel layer 130. In this embodiment, the materials of the channel layer 130 and the barrier layer 140 include aluminum indium gallium nitride (AlInGaN). x In y Ga (1-x-y) N), where 0≦x<1, 0≦x+y≦1. In the present embodiment, the channel layer 130 may be a gallium nitride layer, and the barrier layer 140 may be an aluminum gallium nitride layer or an indium gallium nitride layer. Due to the spontaneous polarization (Spontaneous Polarization) formed by the channel layer 130 and the barrier layer 140 themselves, and the piezoelectric polarization (Piezoelectric Polarization) between the channel layer 130 and the barrier layer 140, the heterojunction between the channel layer 130 and the barrier layer 140 generates a two-dimensional electron gas 132.

[0050] Please continue reading Figure 2 , a source electrode 150 and a drain electrode 160 are formed on the barrier layer 140. The source electrode and the drain electrode can be made of materials selected from the group consisting of titanium, aluminum, nickel, gold, or alloys thereof. Figure 3 , forming a covering layer 170 to cover the source electrode 150 and the drain electrode 160. The covering layer 170 may be made of a hard insulating dielectric material, or may be made of a hard conductive ceramic material or a metal material, for example, one of the groups consisting of silicon nitride, silicon dioxide, silicon oxynitride, titanium nitride, titanium tungsten, titanium tungsten nitride, aluminum nitride, and stone mill, so as to prevent the source electrode and the drain electrode from having lateral gold overflow and upper gold overflow during the subsequent high-temperature manufacturing process of the ohmic contact. Next, a high-temperature heating manufacturing process is performed at a temperature of about 850°C, so that the titanium, aluminum and other metals of the source electrode 150 and the drain electrode 160 form an ohmic contact between the metal alloy and the aluminum gallium nitride barrier layer 140. It should be noted that, since the source electrode 150 and the drain electrode 160 are covered by the cover layer 170, even if the source electrode 150 and the drain electrode 160 are at high temperature, the lateral gold overflow and the upper gold overflow caused by the electrode melting and flowing in the existing semiconductor manufacturing process will not occur, and the possible short circuit problem between the source electrode and the drain electrode during the subsequent manufacturing of the gate structure can be avoided. At the same time, the upper gold overflow of the source electrode and the drain electrode is avoided, which affects the flatness of the surface, which is beneficial to the subsequent metal stacking process.

[0051] In a specific embodiment, an insulating ion implantation process is then performed between components to destroy the two-dimensional electron gas that may exist between the components to ensure the insulation independence between the components on the wafer. Specifically, a boron ion beam can be used for insulating ion implantation, and the boron ion concentration can be controlled at 1E15 / cm 3 , the ion implantation energy is about 180Kev. Figure 4 , and then the process of forming the gate electrode is performed, and the gate electrode 180 is formed on the barrier layer 140 between the source electrode 150 and the drain electrode 160. In the preferred embodiment of the present invention, when the gate structure is manufactured, in order to effectively increase the breakdown voltage (Break Down Voltage) and reduce the gate leakage current, a field effect plate (Field Plate) structure 182 can be further added. It is emphasized again that in the semiconductor structure disclosed by the present invention, since the periphery of the source electrode 150 and the drain electrode 160 has been covered by the covering layer 170, the subsequent high-temperature alloy manufacturing process of the ohmic contact can avoid the defect of lateral gold overflow, and therefore, the short circuit problem between the lateral gold overflow and the gate electrode is also avoided, thereby improving the manufacturing process yield.

[0052] Next, a metal stacking process is performed on the source electrode and the drain electrode. The metal stacking process at this time varies depending on the conductivity of the covering layer. Figure 5A As shown, when the covering layer 170 is an insulating dielectric material such as silicon nitride, silicon dioxide, silicon oxynitride, etc., before the metal stacking process is performed, part of the covering layer 170 above the source electrode 150 and the drain electrode 160 needs to be removed in advance to expose the upper regions of the source electrode 150 and the drain electrode 160, respectively. Only then can a first metal layer 190 be formed in the upper regions of the source electrode 150 and the drain electrode 160. The stacking height of this first metal layer 190 must be higher than the height of the gate electrode 180 including the field effect plate 182 to prevent the gate electrode structure from being damaged during the subsequent planarization process. The material of the first metal layer 190 may include aluminum Al, copper Cu, tungsten W, titanium Ti, tantalum Ta, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, tantalum carbide, tantalum silicon nitride, tantalum carbonitride, titanium aluminum, titanium aluminum nitride, metal alloys or other suitable conductive materials. On the other hand, as Figure 5B As shown, when the cover layer 170 is a conductive material such as titanium nitride, titanium tungsten, titanium tungsten nitride, aluminum nitride, stone mill, etc., it is a conductive cover layer because of its conductivity. When performing the metal stacking process, it is not necessary to remove the cover layer 170 above the source electrode 150 and the drain electrode 160 in advance, but the first metal layer 190 can be directly formed on the cover layer 170 in the area above the source electrode 150 and the drain electrode 160. Similar to the above content, the stacking height of this first metal layer 190 must also be higher than the height of the gate electrode 180 including the field effect plate 182.

[0053] It should be noted that, although the above-mentioned manufacturing process is different due to the difference in the conductivity of the cover layer 170, the subsequent semiconductor structure manufacturing process of the present invention is substantially the same. For the sake of simplicity, the following is a specific description of the implementation scheme of the cover layer 170 with insulating properties. A person skilled in the art should be able to easily deduce the subsequent specific implementation scheme based on the cover layer 170 with conductive properties based on the above disclosure of the present invention, so the relevant description is omitted.

[0054] See also Figure 6 , a liner layer 200 is formed to cover the first metal layer 190 and a portion of the barrier layer 140, the cap layer 170, and the gate electrode 180. Next, refer to Figure 7 After forming an inner dielectric layer 210 covering the entire wafer, a planarization process is performed. Specifically, the planarization process uses the liner layer 200 above the first metal layer 190 as a stop layer to perform chemical mechanical polishing or etching back to remove the liner layer 200 above the first metal layer 190 and expose the upper area of ​​the first metal layer 190, such as Figure 8 As shown. It should be noted that, since the metal stacking height of the first metal layer 190 is higher than the height of the gate electrode 180 and the field effect plate 182, the above-mentioned planarization process will stop at the liner layer 200 above the first metal layer 190. Therefore, this planarization process will not damage the gate electrode 180 and the field effect plate 182. Then, a high-temperature annealing process is used to planarize the area above the exposed first metal layer 190. In a preferred embodiment, the surface flatness of the area above the first metal layer 190 after high-temperature annealing can be less than 0.1 microns, which is beneficial to the subsequent metal stacking process.

[0055] See also Fig. 9 , and then the internal connection manufacturing process of the metal stack of the electrode is carried out. A dielectric layer 220 is formed on the liner layer 200, and then a through hole structure 230 is formed in the dielectric layer 220, and finally a second metal layer 240 is formed, which is electrically connected to the through hole structure 230 and the first metal layer 190 to respectively conduct the source electrode 150 and the drain electrode 160, and the semiconductor structure 10 of the present invention is completed. The materials of the through hole structure 230 and the second metal layer 240 can be the same as those of the first metal layer 190, and are not repeated here.

[0056] It should be noted that the above description is only one of the implementation schemes of the present invention. The structures disclosed in the present invention can be applied to normally-on devices or normally-off devices in high electron mobility transistors, for example, the Schottky Gate structure and the Metal-Insulator-Semiconductor Gate structure commonly used in normally-on devices, or the recessed gate structure and the p-type doped gallium nitride gate structure commonly used in normally-off devices. When manufacturing the above-mentioned different gate structures, the isolation function of the cover layer 170 disclosed in the present invention can be applied, so that the problem of lateral gold overflow of the source electrode and thus causing a short circuit between the source and the gate will not occur during the manufacturing process of these devices, and the flatness of the metal electrode surface in the subsequent metal stacking process can also be ensured, thereby increasing the yield of the manufacturing process.

[0057] The above embodiments are only used to illustrate the embodiments of the present invention and to explain the technical features of the present invention, and are not used to limit the protection scope of the present invention. Any changes or equivalent arrangements that can be easily completed by those skilled in the art belong to the scope claimed by the present invention, and the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A semiconductor structure comprising: a substrate; a channel layer, located on the substrate; a barrier layer, located on the channel layer; a source electrode, a gate electrode, and a drain electrode, each located on the barrier layer; and A covering layer, in, The covering layer covers the source electrode and the drain electrode except the upper part of the source electrode and the drain electrode.

2. The semiconductor structure as claimed in claim 1, wherein the source electrode and the drain electrode are selected from one of the group consisting of titanium, aluminum, nickel and gold.

3. The semiconductor structure as claimed in claim 1, wherein the capping layer is selected from the group consisting of silicon nitride, silicon dioxide, and silicon oxynitride. 4 . The semiconductor structure as claimed in claim 1 , further comprising a first metal layer, wherein the first metal layer is disposed above the source electrode and the drain electrode and is electrically connected to the source electrode and the drain electrode. 5 . The semiconductor structure as claimed in claim 4 , further comprising a liner layer, wherein the liner layer covers a portion of the barrier layer, the capping layer, the first metal layer, and the gate electrode except for an area above the first metal layer. 6 . The semiconductor structure as claimed in claim 5 , wherein the liner layer is selected from the group consisting of silicon nitride, silicon dioxide, aluminum nitride, and silicon carbide. 7 . The semiconductor structure as claimed in claim 4 , further comprising a via structure and a second metal layer, wherein the via structure and the second metal layer are sequentially located above the first metal layer and are electrically connected to the first metal layer. 8 . The semiconductor structure as claimed in claim 1 , further comprising a two-dimensional electron gas, wherein the two-dimensional electron gas is disposed at an interface between the channel layer and the barrier layer.

9. The semiconductor structure as claimed in claim 1, wherein the material of the barrier layer comprises aluminum indium gallium nitride (AlInGaN). x In y Ga (1-x-y) N, where 0≦x<1, 0≦x+y≦1.

10. The semiconductor structure of claim 1, wherein the substrate is selected from the group consisting of silicon, sapphire, and silicon carbide.

11. A semiconductor structure comprising: a substrate; a channel layer, located on the substrate; a barrier layer, located on the channel layer; a source electrode, a gate electrode, and a drain electrode, each located on the barrier layer; and a conductive covering layer, in, The conductive covering layer covers the source electrode and the drain electrode.

12. The semiconductor structure of claim 11, wherein the conductive cap layer is selected from the group consisting of titanium nitride, titanium tungsten, titanium tungsten nitride, aluminum nitride, and stone mill. 13 . The semiconductor structure as claimed in claim 11 , further comprising a first metal layer, wherein the first metal layer is disposed on the conductive cover layer above the source electrode and the drain electrode and is electrically connected to the conductive cover layer, the source electrode and the drain electrode.

14. A method for manufacturing a semiconductor structure, comprising: A channel layer and a barrier layer are sequentially formed on a substrate, and a two-dimensional electron gas is present at an interface between the channel layer and the barrier layer; forming a source electrode and a drain electrode, respectively located on the barrier layer; forming a covering layer to cover the source electrode and the drain electrode; as well as The source electrode and the drain electrode are heated to form ohmic contacts between the source electrode and the drain electrode and the barrier layer respectively.

15. The method for manufacturing a semiconductor structure according to claim 14, further comprising: forming a gate electrode on the barrier layer between the source electrode and the drain electrode; and A first metal layer is formed on the upper region of the source electrode and the drain electrode, so that the first metal layer is electrically connected to the source electrode and the drain electrode respectively.

16. The method for manufacturing a semiconductor structure according to claim 15, further comprising: Forming a liner layer to cover the first metal layer and a portion of the barrier layer, the capping layer, and the gate electrode; Removing a portion of the liner layer above the first metal layer to expose an upper region of the first metal layer; as well as The exposed upper region of the first metal layer is annealed at a high temperature.

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