Chip packaging structure, electronic device and preparation method

Abstract

The present application discloses a chip packaging structure, an electronic device and a preparation method, wherein the packaging structure comprises: a first redistribution layer, a chip wafer, a second redistribution layer and a packaging layer, wherein the first redistribution layer and the second redistribution layer are electrically connected, the packaging layer is sandwiched between the first redistribution layer and the second redistribution layer, at least two stacked chip wafers are embedded in the packaging layer, any two adjacent chip wafers are electrically connected, and any chip wafer is electrically connected to at least one of the first redistribution layer and the second redistribution layer. In this way, the volume of the chip packaging structure can be made smaller.

Description

Technical Field

[0001] The present application belongs to the field of electronic technology, and specifically relates to a chip packaging structure, an electronic device and a preparation method. Background Art

[0002] With the continuous development of electronic technology, more and more functions can be realized in electronic devices, which leads to an increasing number and types of devices arranged on the chip packaging structure of electronic devices, resulting in an increasing space occupied by the chip packaging structure, and thus the volume of the chip packaging structure is also increasing. The chip packaging structure in the prior art is as follows: Figure 1A As shown, the current chip packaging structure uses multiple chip wafers and a substrate to be stacked, and the chip wafers are soldered to the substrate through solder balls. It can be seen that the current chip packaging structure has a large volume. Summary of the invention

[0003] The present application aims to provide a chip packaging structure, an electronic device and a preparation method, which at least solve the problem of the large volume of the chip packaging structure.

[0004] In order to solve the above technical problems, this application is implemented as follows:

[0005] In the first aspect, an embodiment of the present application proposes a chip packaging structure, comprising: a first redistribution layer, a chip wafer, a second redistribution layer and a packaging layer, the first redistribution layer and the second redistribution layer are electrically connected, the packaging layer is sandwiched between the first redistribution layer and the second redistribution layer, at least two stacked chip wafers are embedded in the packaging layer, any two adjacent chip wafers are electrically connected, and any chip wafer is electrically connected to at least one of the first redistribution layer and the second redistribution layer.

[0006] In a second aspect, an embodiment of the present application proposes an electronic device, comprising the above-mentioned chip packaging structure.

[0007] In a third aspect, an embodiment of the present application provides a method for preparing a chip packaging structure, comprising:

[0008] coating a first thin film layer on a carrier, and forming a first redistribution layer on the first thin film layer;

[0009] At least two chip wafers stacked in sequence are arranged on a side of the first redistribution layer away from the carrier, and any two adjacent chip wafers are electrically connected via a first conductive connector;

[0010] Filling a packaging layer on the at least two chip wafers to package the at least two chip wafers;

[0011] A second redistribution layer is formed on a side of the packaging layer away from the first redistribution layer.

[0012] In the embodiment of the present application, the chip packaging structure includes a first redistribution layer and a second redistribution layer, that is, the first redistribution layer and the second redistribution layer can replace the function of the substrate, and the first redistribution layer and the second redistribution layer are thinner than the substrate, so the occupied space can be reduced, thereby reducing the volume of the chip packaging structure; at the same time, since the chip packaging structure includes at least two stacked chip wafers, Figure 1A Compared with the current packaging method of stacking multiple chip wafers and a substrate and soldering the chip wafers to the substrate through solder balls, the distance between any two adjacent chip wafers can be shortened, thereby further reducing the occupied space and further reducing the volume of the chip packaging structure.

[0013] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0015] Figure 1A It is a structural schematic diagram of a chip packaging structure in the prior art;

[0016] Figure 1B is a schematic structural diagram of a chip packaging structure provided in an embodiment of the present application;

[0017] Figure 2 is a structural schematic diagram of another chip packaging structure provided in an embodiment of the present application;

[0018] Figure 3 is a structural schematic diagram of a support member in a chip packaging structure provided in an embodiment of the present application;

[0019] Figure 4 This is one of the structural schematic diagrams of the second redistribution layer in a chip packaging structure provided in an embodiment of the present application;

[0020] Figure 5 This is the second structural schematic diagram of the second redistribution layer in a chip packaging structure provided in an embodiment of the present application;

[0021] Figure 6 is a flow chart of a chip packaging structure preparation method provided in an embodiment of the present application;

[0022] Figure 7This is one of the structural schematic diagrams of a chip packaging structure preparation process provided in an embodiment of the present application;

[0023] Figure 8 This is the second structural schematic diagram of a chip packaging structure preparation process provided in an embodiment of the present application;

[0024] Fig. 9 This is the third structural schematic diagram of a chip packaging structure preparation process provided in an embodiment of the present application;

[0025] Fig.10 This is the fourth structural schematic diagram of a chip packaging structure preparation process provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The embodiments of the present application will be described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limitations on the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0027] See also Figure 1B and Figure 2 , Figure 1B and Figure 2 They are schematic diagrams of a chip packaging structure provided in an embodiment of the present application, such as Figure 1B and Figure 2 As shown, the chip packaging structure includes: a first redistribution layer 10, a chip wafer 21, a second redistribution layer 30 and a packaging layer 40, wherein the packaging layer 40 is sandwiched between the first redistribution layer 10 and the second redistribution layer 30, at least two stacked chip wafers 21 are embedded in the packaging layer 40, any two adjacent chip wafers 21 are electrically connected, and any chip wafer 21 is electrically connected to at least one of the first redistribution layer 10 and the second redistribution layer 30.

[0028] Among them, the first redistribution layer 10, the encapsulation layer 40, and the second redistribution layer 30 can be understood as being arranged in sequence and overlapping, and the encapsulation layer 40 is sandwiched between the first redistribution layer 10 and the second redistribution layer 30. It can be understood that: the two side surfaces of the encapsulation layer 40 that are opposite to each other are respectively in contact with the first redistribution layer 10 and the second redistribution layer 30, or, the two side surfaces of the encapsulation layer 40 that are opposite to each other have a gap with the first redistribution layer 10 and the second redistribution layer 30, and the above-mentioned gap can be filled with connecting parts.

[0029] The working principle of the embodiment of the present application can be seen in the following description:

[0030] The chip packaging structure includes a first redistribution layer 10 and a second redistribution layer 30, that is, the first redistribution layer 10 and the second redistribution layer 30 can replace the function of the substrate, and the first redistribution layer 10 and the second redistribution layer 30 are thinner than the substrate, so that the occupied space can be reduced, thereby reducing the volume of the chip packaging structure; at the same time, since the chip packaging structure includes at least two stacked chip wafers 21, the distance between any two adjacent chip wafers 21 can be shortened compared with the prior art, thereby further reducing the occupied space and further reducing the volume of the chip packaging structure. The chip packaging structure in the prior art is as follows: Figure 1A As shown, a plurality of chip wafers 21 are stacked with a substrate 100 , and the chip wafers 21 are soldered to the substrate 100 via solder balls 101 .

[0031] In addition, the first redistribution layer 10 and the second redistribution layer 30 can both be referred to as redistribution layers (RDL), and RDL packaging technology is the core technology in wafer-level packaging technology. RDL can play the role of electrical extension and interconnection on different planes in the chip packaging structure. Specifically, RDL is to change the chip circuit contact position (I / Opad) in the originally designed chip packaging structure through the wafer-level metal wiring process and the bump process, so that the chip packaging structure can be applied to different packaging forms, and the thickness of RDL is thinner than the substrate in the prior art. .

[0032] The encapsulation layer 40 may be referred to as a molding compound (MC) layer.

[0033] Among them, the packaging layer 40 is located between the first redistribution layer 10 and the second redistribution layer 30, and the packaging layer 40 is respectively abutted against the first redistribution layer 10 and the second redistribution layer 30, so as to support the packaging layer 40 and reduce the warping deformation of the entire chip packaging structure, that is, enhance the rigidity of the entire chip packaging structure and extend the service life.

[0034] In addition, the module composed of at least two stacked chip wafers 21 can be called a chip body 20. Since at least two stacked chip wafers 21 are embedded in the packaging layer 40, it can be understood that the chip body 20 is embedded in the packaging layer 40, that is, the packaging layer 40 can protect the chip body 20 and enhance the waterproof and dustproof effect of the chip body 20. At the same time, the rigidity of the entire chip packaging structure can be further enhanced, thereby further extending the service life of the chip packaging structure.

[0035] The specific manner of electrical connection between any two adjacent chip wafers 21 is not limited herein. Optionally, any two adjacent chip wafers 21 may be directly abutted against each other to achieve electrical connection.

[0036] As another optional embodiment, the chip wafer 21 includes a first surface and a second surface arranged opposite to each other, the first surface and / or the second surface is provided with a first conductive connector 22, and any two adjacent chip wafers 21 are electrically connected through the first conductive connector 22.

[0037] In the embodiment of the present application, any two adjacent chip wafers 21 are electrically connected via the first conductive connector 22, so that at least two chip wafers 21 can cooperate with each other, enhance the performance of the chip packaging structure, and increase the functional diversity of the chip packaging structure.

[0038] It should be noted that the specific structure of the first conductive connector 22 is not limited here. For example, the first conductive connector 22 can be a metal connector, so that the conductive effect between any two adjacent chip wafers 21 can be enhanced, and at the same time, it can also play a supporting role between any two adjacent chip wafers 21, that is, it enhances the connection strength between any two adjacent chip wafers 21. Alternatively, the first conductive connector 22 can also be a flexible connector, so that the diversity of the first conductive connector 22 is increased.

[0039] As an optional implementation, see Figure 1B and Figure 2 The chip wafer 21 is provided with a through hole connecting the first surface 211 and the second surface 212 , and the through hole is filled with a second conductive connecting member 213 , and the first surface 211 and the second surface 212 are electrically connected via the second conductive connecting member 213 .

[0040] Among them, the first surface 211 of the chip wafer 21 located at the bottom of any two adjacent chip wafers 21 is electrically connected to the first conductive connecting component 22, and the second surface 212 of the chip wafer 21 located at the top of any two adjacent chip wafers 21 is electrically connected to the first conductive connecting component 22. The second surface 212 of the chip wafer 21 located at the top of any two adjacent chip wafers 21 is electrically connected to the first surface 211 of the chip wafer 21 located below the chip wafer 21 through a first conductive connecting component 22, thereby realizing the electrical connection between the chip wafer 21 located at the top of any two adjacent chip wafers 21 and the chip wafer 21 located below.

[0041] In the embodiment of the present application, the second conductive connector 213 is filled in the through hole, and the first surface 211 and the second surface 212 are electrically connected through the second conductive connector 213. In this way, at least two chip wafers 21 can be electrically connected to each other in the stacking direction, that is, vertical interconnection of at least two chip wafers 21 can be achieved. At the same time, at least two chip wafers 21 can transmit signals through the first conductive connector 22 and the second conductive connector 213 in turn, thereby reducing signal transmission delay and loss, improving signal speed and bandwidth, and enhancing signal transmission effect.

[0042] As an optional implementation, the chip wafer 21 includes a silicon body layer, and the through hole is opened on the silicon body layer.

[0043] Among them, a through hole connecting the first surface 211 and the second surface 212 of the chip wafer 21 is opened on the silicon body layer included in the chip wafer 21, and a second conductive connecting member 213 is filled in the through hole, so that the first surface 211 and the second surface 212 are electrically connected through the second conductive connecting member 213. The above-mentioned setting method can be referred to as through silicon via (TSV) technology.

[0044] In addition, the chip wafer 21 may include a silicon body layer and other functional layers, and the number of other functional layers is not limited here, and the other functional layers can be stacked in sequence. The positional relationship between the other functional layers and the silicon body layer is not limited here, for example: the other functional layers can be arranged around the silicon body layer.

[0045] In the implementation manner of the present application, the through hole is opened on the silicon body layer, so that the processing difficulty of opening the through hole can be reduced. At the same time, the occurrence of damage to the wiring on the chip wafer 21 caused by drilling the through hole can be reduced, that is, the influence of the through hole on the wiring on the chip wafer 21 is reduced.

[0046] As an optional implementation, see Figure 1B The chip packaging structure further includes a support member 50 , and the support member 50 is embedded in the packaging layer 40 .

[0047] The support member 50 may be made of a conductive material, that is, the support member 50 may be a conductive member, for example, the support member 50 may be a copper column.

[0048] In the embodiment of the present application, the support member 50 is embedded in the packaging layer 40. In this way, the connection strength of the packaging layer 40 can be enhanced, thereby enhancing the strength of the chip packaging structure. The support member 50 can further enhance the supporting effect of the packaging layer 40 on the first redistribution layer 10 and the second redistribution layer 30, further reducing the warping deformation of the entire chip packaging structure, that is, further enhancing the rigidity of the entire chip packaging structure, and further extending the service life of the chip packaging structure.

[0049] As an optional implementation, see Figure 1B The support member 50 includes a first support member 51 , which is respectively in contact with the first redistribution layer 10 and the second redistribution layer 30 , and the first redistribution layer 10 and the second redistribution layer 30 are electrically connected through the first support member 51 .

[0050] In the embodiment of the present application, the first support member 51 is respectively in contact with the first redistribution layer 10 and the second redistribution layer 30, that is, the first support member 51 can support the first redistribution layer 10 and the second redistribution layer 30, and the first redistribution layer 10 and the second redistribution layer 30 are electrically connected through the first support member 51, that is, the first support member 51 can have a conductive function. In this way, the first support member 51 integrates the supporting function and the conductive function, thereby reducing the use of components and reducing the cost of use.

[0051] As an optional implementation, see Figure 2 and Figure 3 The first support member 51 includes a plurality of support columns 511 connected in sequence, and a reinforcing beam 512 is provided at the connection between adjacent support columns 511 , and the reinforcing beam 512 is provided perpendicular to the support columns 511 .

[0052] In the embodiment of the present application, reinforcing beams 512 are provided at the connection points of adjacent support columns 511 , so as to further enhance the connection strength between adjacent support columns 511 , thereby further enhancing the supporting effect of the packaging layer 40 on the first redistribution layer 10 and the second redistribution layer 30 .

[0053] As an optional implementation, see Figure 3 The number of the reinforcing beams 512 is multiple, and the multiple reinforcing beams 512 include a first reinforcing beam 5121 and a second reinforcing beam 5122, and the first vertical projection of the first reinforcing beam 5121 on the first redistribution layer 10 and the second vertical projection of the second reinforcing beam 5122 on the first redistribution layer 10 are alternately arranged.

[0054] In the embodiment of the present application, the first vertical projection of the first reinforcing beam 5121 on the first redistribution layer 10 and the second vertical projection of the second reinforcing beam 5122 on the first redistribution layer 10 are alternately arranged. It can be understood that the first reinforcing beam 5121 and the second reinforcing beam 5122 are arranged in different directions. In this way, different positions of the packaging layer 40 can be supported and the connection strength of different positions of the packaging layer 40 can be strengthened, thereby further reducing the warping deformation of the entire chip packaging structure, that is, further enhancing the rigidity of the entire chip packaging structure, and further extending the service life of the chip packaging structure.

[0055] For example: the first reinforcement beam 5121 can be arranged along the northwest to southeast direction of the plane where the first redistribution layer 10 is located, the second reinforcement beam 5122 can be arranged along the north-south direction of the plane where the first redistribution layer 10 is located, and the multiple reinforcement beams 512 can also include a third reinforcement beam, and the third reinforcement beam can be arranged along the east-west direction of the plane where the first redistribution layer 10 is located.

[0056] In addition, the first support member 51 can be a frame structure. In this way, the first support member 51 can serve as a stress-bearing structure for the entire chip packaging structure and can withstand the stress load of the chip packaging structure, thereby reducing the degree of warping deformation of the entire chip packaging structure under stress, so that the degree of warping deformation is within a preset range, thereby enhancing the stability and safety of the chip packaging structure.

[0057] It should be noted that the specific manner in which the first redistribution layer 10 and the second redistribution layer 30 are electrically connected through the first support member 51 is not limited herein. As an optional embodiment, the first redistribution layer 10 and the second redistribution layer 30 are directly electrically connected through the first support member 51, that is, the first support member 51 can serve as a conductive member between the first redistribution layer 10 and the second redistribution layer 30.

[0058] As another optional implementation, a connection line is passed through the first support member 51 , and the first redistribution layer 10 and the second redistribution layer 30 are electrically connected via the connection line.

[0059] In the embodiment of the present application, the first redistribution layer 10 and the second redistribution layer 30 are electrically connected via a connecting wire passing through the inside of the first support member 51. In this way, the safety performance of electrical conduction can be improved. At the same time, since the first support member 51 is usually wider, the width of the connecting wire can be wider, so that the method of transmitting electricity using the connecting wire can reduce the loss of electricity during the transmission process.

[0060] It should be noted that the first redistribution layer 10 and the second redistribution layer 30 are electrically connected through the connecting wires in the first support member 51. In this way, the connecting wires can enhance the conductivity between the first redistribution layer 10 and the second redistribution layer 30, and the first support member 51 has a supporting function, thereby reducing the number of components and reducing the cost of use.

[0061] As another optional implementation, see Figure 1B The support member 50 includes a second support member 52, the second support member 52 is located between the first redistribution layer 10 and the second redistribution layer 30, and the first end of the second support member 52 abuts against the first redistribution layer 10, and the second end of the second support member 52 abuts against one of the at least two chip wafers 21.

[0062] In the embodiment of the present application, since the first end of the second support member 52 abuts against the first redistribution layer 10, and the second end of the second support member 52 abuts against one of the at least two chip wafers 21, the supporting effect on the first redistribution layer 10 and the second redistribution layer 30 can be further enhanced, and at the same time, it can also support the chip wafer 21.

[0063] In addition, since the support member 50 includes the second support member 52, the support member 50 can include at least one of the first support member 51 and the second support member 52, and the first support member 51 and the second support member 52 are arranged at different positions, thereby increasing the flexibility of the arrangement position of the support member 50.

[0064] As an optional implementation, see Figure 1B and Figure 2 A welding member 60 is disposed on at least one of the first redistribution layer 10 and the second redistribution layer 30 .

[0065] The welding member 60 may include components such as a solder pad and a solder ball.

[0066] Also, see Figure 4 and Figure 5 The first redistribution layer 10 may be provided with a plurality of pads, so that a welding member 60 may be provided on the pads, and may be electrically connected to other electronic devices through the welding member 60. The specific types of the other electronic devices are not limited here. For example, the other electronic devices may be the motherboard of the electronic device.

[0067] In the embodiment of the present application, a welding part 60 is provided on at least one of the first redistribution layer 10 and the second redistribution layer 30. In this way, it can be electrically connected to other components (such as a motherboard) through the welding part 60, thereby increasing the flexibility of the electrical connection position. At the same time, when the welding parts 60 are provided on both the first redistribution layer 10 and the second redistribution layer 30, the chip packaging structure can include two active surfaces, thereby meeting the layout design requirements of two different motherboards, and can greatly save the development cycle of the chip packaging structure, and improve the effectiveness of the mass reuse of the raw materials of the chip packaging structure.

[0068] As an optional embodiment, the first redistribution layer 10 is a multi-layer, and the multi-layer first redistribution layer 10 is stacked in sequence, and / or the second redistribution layer 30 is a multi-layer, and the multi-layer second redistribution layer 30 is stacked in sequence.

[0069] In the embodiment of the present application, the first redistribution layer 10 is a multi-layer and the second redistribution layer 30 is a multi-layer. In this way, the routing length and area on the first redistribution layer 10 and the second redistribution layer 30 can be increased, which facilitates routing and enhances the performance of the chip packaging structure.

[0070] An embodiment of the present application also provides an electronic device, including the chip packaging structure in the above embodiment. Since the electronic device provided by the embodiment of the present application includes the chip packaging structure in the above embodiment, it has the same beneficial technical effects as the above embodiment, and the specific structure of the chip packaging structure can refer to the relevant description in the above embodiment, which will not be repeated here.

[0071] The present application also provides a method for preparing a chip packaging structure. Figure 6 As shown, the chip packaging structure preparation method includes the following steps:

[0072] Step 601: Coat a first thin film layer on a carrier, and form a first redistribution layer on the first thin film layer. The module obtained in step 601 can be as follows: Figure 7 As shown, the module includes a carrier board 70 and a first redistribution layer 10 .

[0073] Among them, the carrier board can be a pre-fabricated carrier board. After the chip packaging structure is prepared, the carrier board can be removed, that is, the carrier board can be understood as a carrier that plays a supporting role in the packaging process of the chip packaging structure. The carrier board does not belong to the chip packaging structure and is only used in the packaging process. The carrier board can be a backplane made of glass, ceramic, metal or other materials with similar functions and compatible with wafer-level packaging processes.

[0074] It should be noted that after the chip packaging structure is prepared and the carrier is removed, the structure obtained can be as follows: Figure 1B and Figure 2 shown.

[0075] The specific type of the first film layer is not limited here. For example, the first film layer can be at least one of the following film layers: an adhesion layer film layer, a sacrificial layer film layer, and a buffer layer film layer.

[0076] Step 602: at least two chip wafers stacked in sequence are arranged on a side of the first redistribution layer away from the carrier board, and any two adjacent chip wafers are electrically connected via a first conductive connector.

[0077] The chip wafer and the first conductive connecting member may refer to the relevant descriptions in the above embodiments, which will not be described again here.

[0078] Among them, the processing steps between any two adjacent chip wafers can be referred to as follows: a plurality of solder pads can be set on the first surface of one of any two adjacent chip wafers, and a plurality of solder pads can be set on the second surface of the other of any two adjacent chip wafers, and the first conductive connector can be respectively welded and fixed to the above-mentioned first surface and second surface using thermocompression bonding (TCB) welding method.

[0079] Step 603: Fill a packaging layer on the at least two chip wafers to package the at least two chip wafers.

[0080] Among them, the encapsulation layer can refer to the relevant description in the above embodiment, and will not be described in detail here.

[0081] Step 604 , forming a second redistribution layer on a side of the packaging layer away from the first redistribution layer.

[0082] In the embodiment of the present application, through the above steps, the chip packaging structure obtained can be made smaller in size and thinner in thickness. When the chip packaging structure is applied to electronic devices, the electronic devices can be made smaller in size and thinner in thickness.

[0083] As an optional implementation manner, before arranging at least two sequentially stacked chip wafers on a side of the first redistribution layer away from the carrier, the method further includes:

[0084] preparing a support member on the first redistribution layer;

[0085] The step of filling a packaging layer on the at least two chip wafers to package the at least two chip wafers comprises:

[0086] A packaging layer is filled on the at least two chip wafers and the support member to encapsulate the at least two chip wafers and the support member.

[0087] In this embodiment, after arranging the support member 50 on the first redistribution layer 10, the structure obtained can be as follows: Figure 8 shown.

[0088] In addition, the encapsulation layer 40 is filled on the at least two chip wafers 21 and the support member 50 to encapsulate the at least two chip wafers 21 and the support member 50. The structure obtained after that can be as follows: Fig.10 shown.

[0089] Among them, the support member and the packaging layer can refer to the relevant description in the above embodiments.

[0090] In the implementation manner of the present application, by providing a support member, a supporting effect can be achieved, thereby enhancing the connection strength of the entire chip packaging structure.

[0091] It should be noted that when filling the packaging layer, at least two chip wafers and the support member can be packaged in the packaging layer, so that the at least two chip wafers and the support member can be isolated from the external environment, thereby enhancing the protection effect of the at least two chip wafers and the support member.

[0092] Optionally, after obtaining the encapsulation layer, the encapsulation layer may be ground to reduce the thickness of the encapsulation layer so that the end of the support member can be exposed from the encapsulation layer to facilitate electrical connection with the second redistribution layer obtained in subsequent steps.

[0093] It should be noted that the types of chip wafers are not limited here. For example, the at least two chip wafers may include at least one of the following chip wafers: an application processor (AP) chip wafer and a dynamic random access memory (DRAM) chip wafer.

[0094] In addition, the first conductive connectors of some of the at least two chip wafers may be fixed to the support member by welding, thereby enhancing the fixing and supporting effect on the chip wafers.

[0095] It should be noted that the location of the support member is not limited here.

[0096] As an optional implementation, the support member includes a first support member, the first support member abuts against the first redistribution layer and the second redistribution layer respectively, and the first redistribution layer and the second redistribution layer are electrically connected through the first support member;

[0097] The step of preparing a support member on the first redistribution layer comprises:

[0098] preparing a support member on the first redistribution layer by a first preset process;

[0099] Among them, the first preset process includes at least one of the following: sputtering seed layer, dry film lithography, development, curing, electroplating, degumming, seed layer removal, and plastic packaging.

[0100] In the implementation manner of the present application, the support member is prepared on the first redistribution layer through the first preset process, so that the efficiency of preparing the support member can be improved.

[0101] As an optional implementation, before filling the packaging layer on the at least two chip wafers to package the at least two chip wafers, the method further includes:

[0102] A through hole is drilled on the chip wafer and a second conductive connector is filled in the through hole, wherein the chip wafer includes a first surface and a second surface arranged opposite to each other, the through hole connects the first surface and the second surface, and the first surface and the second surface are electrically connected through the second conductive connector.

[0103] In which, a through hole is drilled on the chip wafer 21, and the second conductive connecting member 213 is filled in the through hole. Then, the obtained structure can be as follows: Fig. 9 shown.

[0104] In the implementation mode of the present application, an electrical connection between the first surface and the second surface of the chip wafer is achieved by drilling a through hole on the chip wafer and filling the second conductive connecting member in the through hole. In this way, the electrical connection between the first surface and the second surface of the chip wafer can be better. At the same time, compared with the method of separately setting a connecting wire on the outer surface of the chip wafer, the volume occupied by the chip wafer can be reduced and the stability of the electrical connection can be improved.

[0105] As an optional implementation manner, drilling a through hole on the chip wafer includes:

[0106] Drilling through holes on the chip wafer by a second preset process;

[0107] Wherein, the second preset process includes at least one of the following: photoresist marking, deep reactive ion etching, vapor deposition seed layer, filling electroplated copper, chemical mechanical polishing, and circuit layer manufacturing.

[0108] The second preset process may be referred to as a TSV technology process.

[0109] In the implementation manner of the present application, through holes are drilled on the chip wafer through the second preset process, which can improve the efficiency of drilling through holes and reduce the cost of drilling through holes.

[0110] As an optional implementation, coating a first thin film layer on a carrier and forming a first redistribution layer on the first thin film layer includes:

[0111] coating a first film layer on a carrier;

[0112] preparing a connecting layer on the first film layer;

[0113] The first redistribution layer is prepared on the first surface of the connection layer, and a bump metal layer is prepared on the second surface of the connection layer. The bump metal layer is used for preparing a welding piece.

[0114] In an embodiment of the present application, a bump metal layer is prepared on the second surface of the connecting layer, and the bump metal layer is used to prepare a welding part. In this way, when preparing the welding part, the preparation efficiency of the welding part can be improved, and the fixing effect of the welding part on the first redistribution layer can be enhanced.

[0115] As an optional implementation manner, the step of preparing the first redistribution layer on the first surface of the connection layer includes:

[0116] preparing the first redistribution layer on the first surface of the connection layer by a third preset process;

[0117] The third preset process includes at least one of the following: sputtering a seed layer, coating a dielectric layer, photolithography, development, curing at a temperature greater than a preset value, electroplating, and removing a seed layer.

[0118] Among them, curing at a temperature greater than a preset value can be understood as high-temperature curing, and the specific value of the preset value is not limited here.

[0119] In the implementation manner of the present application, the first redistribution layer is prepared on the first surface of the connection layer through the third preset process, so that the preparation efficiency of the first redistribution layer can be improved and the preparation cost of the first redistribution layer can be reduced.

[0120] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0121] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A chip packaging structure, characterized in that: include: A first redistribution layer, a chip wafer, a second redistribution layer and a packaging layer, wherein the first redistribution layer and the second redistribution layer are electrically connected, the packaging layer is sandwiched between the first redistribution layer and the second redistribution layer, at least two stacked chip wafers are embedded in the packaging layer, any two adjacent chip wafers are electrically connected, and any chip wafer is electrically connected to at least one of the first redistribution layer and the second redistribution layer; The chip packaging structure further includes a support member, wherein the support member is embedded in the packaging layer; The support member includes a first support member, the first support member abuts against the first redistribution layer and the second redistribution layer respectively, and the first redistribution layer and the second redistribution layer are electrically connected through the first support member; The first support member includes a plurality of support columns connected in sequence, and a strengthening beam is provided at the connection between adjacent support columns, and the strengthening beam is provided perpendicular to the support columns; There are multiple reinforcing beams, and the multiple reinforcing beams include a first reinforcing beam and a second reinforcing beam, and a first vertical projection of the first reinforcing beam on the first redistribution layer is alternately arranged with a second vertical projection of the second reinforcing beam on the first redistribution layer.

2. The chip packaging structure according to claim 1, characterized in that: The chip wafer comprises a first surface and a second surface disposed opposite to each other, the first surface and / or the second surface is provided with a first conductive connector, and any two adjacent chip wafers are electrically connected via the first conductive connector.

3. The chip packaging structure according to claim 2, characterized in that: A through hole connecting the first surface and the second surface is formed on the chip wafer, the through hole is filled with a second conductive connecting member, and the first surface and the second surface are electrically connected via the second conductive connecting member.

4. The chip packaging structure according to claim 1, characterized in that: A connecting line is inserted into the first supporting member, and the first redistribution layer and the second redistribution layer are electrically connected through the connecting line.

5. The chip packaging structure according to claim 1, characterized in that: The support member includes a second support member, the second support member is located between the first redistribution layer and the second redistribution layer, and a first end of the second support member abuts against the first redistribution layer, and a second end of the second support member abuts against one chip wafer of the at least two chip wafers.

6. The chip packaging structure according to any one of claims 1 to 5, characterized in that: A welding member is disposed on at least one of the first redistribution layer and the second redistribution layer.

7. The chip packaging structure according to any one of claims 1 to 5, characterized in that: The first redistribution layer is a multi-layer structure, and the multi-layer first redistribution layers are stacked in sequence, and / or the second redistribution layer is a multi-layer structure, and the multi-layer second redistribution layers are stacked in sequence.

8. An electronic device, characterized in that: A chip packaging structure comprising any one of claims 1 to 7.

9. A method for preparing a chip packaging structure, characterized in that: include: coating a first thin film layer on a carrier, and forming a first redistribution layer on the first thin film layer; At least two chip wafers stacked in sequence are arranged on a side of the first redistribution layer away from the carrier, and any two adjacent chip wafers are electrically connected via a first conductive connector; Filling a packaging layer on the at least two chip wafers to package the at least two chip wafers; forming a second redistribution layer on a side of the packaging layer away from the first redistribution layer; Before arranging at least two chip wafers stacked in sequence on a side of the first redistribution layer away from the carrier, the method further comprises: preparing a support member on the first redistribution layer; The step of filling a packaging layer on the at least two chip wafers to package the at least two chip wafers comprises: Filling a packaging layer on the at least two chip wafers and the support member to encapsulate the at least two chip wafers and the support member; The support member includes a first support member, the first support member abuts against the first redistribution layer and the second redistribution layer respectively, and the first redistribution layer and the second redistribution layer are electrically connected through the first support member; The first support member includes a plurality of support columns connected in sequence, and a strengthening beam is provided at the connection between adjacent support columns, and the strengthening beam is provided perpendicular to the support columns; There are multiple reinforcing beams, and the multiple reinforcing beams include a first reinforcing beam and a second reinforcing beam, and a first vertical projection of the first reinforcing beam on the first redistribution layer is alternately arranged with a second vertical projection of the second reinforcing beam on the first redistribution layer.

10. The method according to claim 9, characterized in that The step of preparing a support member on the first redistribution layer comprises: preparing a support member on the first redistribution layer by a first preset process; Among them, the first preset process includes at least one of the following: sputtering seed layer, dry film lithography, development, curing, electroplating, degumming, seed layer removal, and plastic packaging.

11. The method according to claim 9, characterized in that Before filling the packaging layer on the at least two chip wafers to package the at least two chip wafers, the method further includes: A through hole is drilled on the chip wafer and a second conductive connector is filled in the through hole, wherein the chip wafer includes a first surface and a second surface arranged opposite to each other, the through hole connects the first surface and the second surface, and the first surface and the second surface are electrically connected through the second conductive connector.

12. The method according to claim 11, characterized in that The step of drilling a through hole on the chip wafer comprises: Drilling through holes on the chip wafer by a second preset process; Wherein, the second preset process includes at least one of the following: photoresist marking, deep reactive ion etching, vapor deposition seed layer, filling electroplated copper, chemical mechanical polishing, and circuit layer manufacturing.

13. The method according to any one of claims 9 to 12, characterized in that The step of coating a first thin film layer on a carrier and forming a first redistribution layer on the first thin film layer comprises: coating a first film layer on a carrier; preparing a connecting layer on the first film layer; The first redistribution layer is prepared on the first surface of the connection layer, and a bump metal layer is prepared on the second surface of the connection layer. The bump metal layer is used for preparing a welding piece.

14. The method according to claim 13, characterized in that The step of preparing the first redistribution layer on the first surface of the connection layer comprises: preparing the first redistribution layer on the first surface of the connection layer by a third preset process; The third preset process includes at least one of the following: sputtering a seed layer, coating a dielectric layer, photolithography, development, curing at a temperature greater than a preset value, electroplating, and removing a seed layer.

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