A data synchronization optimization method, system, device and terminal between serial chips

Abstract

The present invention belongs to the field of chip control technology, and discloses a data synchronization optimization method, system, device and terminal between serial chips, which uses the clock of the first chip of the serial chipset to count and generate information codes; transmits the information codes in sequence to the subsequent chips, and the subsequent chips use their own clocks to count the codes after receiving the codes; calculates the ratio of CNT to CNT0 to obtain the deviation value between the clock of each subsequent chip and the clock of the first chip; the subsequent chip uses the deviation value to correct the data to be synchronized and the continuous time period of the chip, so that the data and time period of the subsequent chip are synchronized with the first chip. The data synchronization optimization method between serial chips of the present invention is applied to multi-core SoC chips. The test results show that the optimized multi-core SoC chip is within 15% of the clock deviation, and the serial chipset runs continuously for 24 hours. The maximum time cumulative deviation is reduced from 7.2 hours to 17.28 seconds, and the optimization effect is obvious.

Description

Technical Field

[0001] The present invention belongs to the field of chip control technology, and in particular relates to a method, system, device and terminal for optimizing data synchronization between serial chips. Background Art

[0002] At present, a complex chip communication system usually consists of a control chip and many slave chips. In this system, the control chip is responsible for controlling each slave chip, that is, each slave chip is directly controlled by a control chip, and each slave chip is independent of each other. However, due to the chip tape-out process, clock deviations will occur between serial chips, resulting in large deviations in data and time period synchronization.

[0003] Through the above analysis, the problems and defects of the prior art are: the clock deviation will occur between the serial chips due to the chip tape-out process, resulting in large deviations in data and time period synchronization. Summary of the invention

[0004] In view of the problems existing in the prior art, the present invention provides a method, system, device and terminal for optimizing data synchronization between serially connected chips.

[0005] The present invention is implemented as follows: a method for optimizing data synchronization between serially connected chips includes: using the clock of the first chip in the serially connected chips to count and generate information codes; transmitting the information codes in serial to the subsequent chips, and the subsequent chips count the codes; calculating the deviation value between the clock of each subsequent chip and the clock of the first chip, and using the deviation value to optimize data synchronization.

[0006] Furthermore, the data synchronization optimization method between serially connected chips includes the following steps:

[0007] Step 1: Use the clock of the first chip in the serial chipset to count, and generate information code within a time period when the counter value is not greater than a certain value CNT0;

[0008] Step 2: The information code is transmitted serially to the subsequent chip. After receiving the code, the subsequent chip uses its own clock to count the code. (1) The first chip counts with its own clock cycle and generates a serial information code of all 1s within CNT0 = 0 to 10^4 (the signal is low level 0 in other time periods). If the clock of the first chip is accurately 10MHz, then the transmission time of the serial code of all 1s is T0 = 1ms (however, due to chip flow process deviation, the actual situation may not be 1ms, but the analysis conclusions are consistent); (2) The high-level information code is transmitted serially to the subsequent chip in sequence. The subsequent chip uses its own clock to count, and the count value is CNT. The CNT value of different subsequent chips may be different;

[0009] Step 3, by calculating the ratio of CNT to CNT0, the deviation value between the clock of each chip in the subsequent stage and the clock of the first chip is calculated; the deviation value of CNT and CNT0 D = (CNT-CNT0) / CNT; if CNT is greater than CNT0, that is, the clock cycle of the chip is smaller than the clock cycle of the first chip, so the count value is large, and D>0 at this time; if CNT is less than CNT0, that is, the clock cycle of the chip is larger than the clock cycle of the first chip, so the count value is small, and D<0 at this time; if CNT is equal to CNT0, that is, the clock cycle of the chip is equal to the clock cycle of the first chip, so the count values ​​are equal, and D=0 at this time;

[0010] Step 4: The subsequent chip uses the deviation value to correct the data to be synchronized and the duration of the chip, so that the data and time period of the subsequent chip are synchronized with the first chip. (1) Test 3 chips in series (as long as the number of chips in series is greater than or equal to 3, the analysis conclusion is consistent). These 3 chips are completely consistent in design. The clock frequency of the chip series transmission is 10MHz. Each chip can control the switch of an LED lamp. It is necessary to realize that the LED lamp controlled by the current chip is turned on 1 hour after the previous LED lamp is turned on. (2) First, the first chip counts with its own clock cycle and generates a serial information code of all 1s within CNT0=0 to 10^4 (the signal is low level 0 in other time periods). If the clock of the first chip is accurately 10MHz, then the transmission time of the serial code of all 1s is T0=1ms (but due to chip flow process deviation, the actual situation may not be 1ms, but the analysis conclusions are consistent); the high-level information code is transmitted backward in sequence, and the subsequent chip uses its own clock to count, and the count value is CNT; (3) Calculate D=(CNT-CNT0) / CNT. The D value of different subsequent chips may be different; (4) If the clock deviation data of the chip manufacturer is + / -15%; (5) If the optimization method described in the present invention is not used (i.e., the subsequent chips all use CNT_ NEW=CNT0_NEW to count), CNT_NEW0 is the count value of the first chip within 1 hour; the maximum time error of each subsequent chip counting CNT_NEW (equal to CNT0_NEW before correction) = 1 hour * 30% = 18 minutes; if it runs continuously for 24 hours, the cumulative maximum error = 24 * 30% = 7.2 hours; (6) If CNT_NEW=(1+D)CNT0_NEW is used to optimize the counting, since the signal sampling uses clock edge counting, it may be more or less 1 cycle within 10^4 cycles, and the error = 2 / 10^4 = 0.02%; then the maximum error of the optimized method in 1 hour = 1 hour * 0.02% = 0.72 seconds, and if it runs continuously for 24 hours, the cumulative maximum error is only = 24 hours * 0.02% = 17.28 seconds. In summary, using the optimized method, the series chip runs continuously for twenty-four hours, and the maximum time cumulative deviation is reduced from the previous 7.2 hours to 17.28 seconds, and the optimization effect is obvious.

[0011] Another object of the present invention is to provide a data synchronization optimization system between serial chips using the data synchronization optimization method between serial chips, the data synchronization optimization system between serial chips comprising:

[0012] An information code generating module, used for counting using the clock of the first chip of the serial chipset, and generating information code within a time period when the counter value is not greater than a certain value CNT0;

[0013] The clock encoding counting module is used to transmit the information encoding in series to the subsequent chip. After receiving the encoding, the subsequent chip uses its own clock to count the encoding;

[0014] The clock deviation value calculation module is used to calculate the deviation value between the clock of each chip in the subsequent stage and the clock of the first chip by calculating the ratio of CNT to CNT0;

[0015] The data synchronization optimization module is used for the subsequent chip to use the deviation value to correct the data to be synchronized and the continuous time period of the chip, so that the data and time period of the subsequent chip are synchronized with the first chip.

[0016] Another object of the present invention is to provide a computer device, the computer device includes a memory and a processor, the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the data synchronization optimization method between serial chips.

[0017] Another object of the present invention is to provide a computer-readable storage medium storing a computer program, which, when executed by a processor, enables the processor to execute the steps of the method for optimizing data synchronization between serially connected chips.

[0018] Another object of the present invention is to provide an application of the data synchronization optimization method between serially connected chips in a chip. (1) Test three chips in series (as long as the number of serially connected chips is greater than or equal to 3, the analysis conclusion is consistent). The three chips are completely consistent in design. The clock frequency of the serially connected chips is 10 MHz. Each chip can control the switch of an LED lamp. It is required to realize that the LED lamp controlled by the current chip is turned on one hour after the previous LED lamp is turned on. (2) First, the first chip counts with its own clock cycle and generates a serial information code of all 1s within CNT0=0 to 10^4 (the signal is low level 0 in other time periods). If the clock of the first chip is accurately 10MHz, then the transmission time of the serial code of all 1s is T0=1ms (but due to chip flow process deviation, the actual situation may not be 1ms, but the analysis conclusions are consistent); the high-level information code is transmitted backward in sequence, and the subsequent chip uses its own clock to count, and the count value is CNT; (3) Calculate D=(CNT-CNT0) / CNT. The D value of different subsequent chips may be different; (4) If the clock deviation data of the chip manufacturer is + / -15%; (5) If the optimization method described in the present invention is not used (i.e., the subsequent chips all use CNT_ NEW=CNT0_NEW to count), CNT_NEW0 is the count value of the first chip within 1 hour; the maximum time error of each subsequent chip counting CNT_NEW (equal to CNT0_NEW before correction) = 1 hour * 30% = 18 minutes; if it runs continuously for 24 hours, the cumulative maximum error = 24 * 30% = 7.2 hours; (6) If CNT_NEW=(1+D)CNT0_NEW is used to optimize the counting, since the signal sampling uses clock edge counting, it may be more or less 1 cycle within 10^4 cycles, and the error = 2 / 10^4 = 0.02%; then the maximum error of the optimized method in 1 hour = 1 hour * 0.02% = 0.72 seconds, and if it runs continuously for 24 hours, the cumulative maximum error is only = 24 hours * 0.02% = 17.28 seconds. In summary, using the optimized method, the series chip runs continuously for twenty-four hours, and the maximum time cumulative deviation is reduced from the previous 7.2 hours to 17.28 seconds, and the optimization effect is obvious.

[0019] Another object of the present invention is to provide an information data processing terminal, which is used to implement the data synchronization optimization system between the serially connected chips.

[0020] In combination with the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solutions to be protected by the present invention are as follows:

[0021] First, in view of the technical problems existing in the above-mentioned prior art and the difficulty of solving the problems, the technical solutions to be protected by the present invention and the results and data during the research and development process are closely combined to analyze in detail and deeply how the technical solutions of the present invention solve the technical problems, and some creative technical effects brought about after solving the problems. The specific description is as follows:

[0022] In order to solve the problem of large data and time period synchronization deviation caused by clock deviation between serial chips due to chip flow process, the present invention proposes an optimization design method, which first uses the clock of the first chip in the serial chipset to count, and generates a section of information code within a time period when the counter value is not greater than a specific value CNT0; then the section of information code is transmitted serially to the subsequent chip in sequence, and the subsequent chip uses its own clock to count the section of code after receiving the code, and the count value is CNT; the deviation between the clock of each subsequent chip and the clock of the first chip can be calculated by calculating the ratio of CNT to CNT0, and the subsequent chip uses this deviation value to correct the data and continuous time period that need to be synchronized for this chip, so that the data and time period of the subsequent chip are synchronized with the first chip.

[0023] Second, considering the technical solution as a whole or from the perspective of the product, the technical effects and advantages of the technical solution to be protected by the present invention are described in detail as follows:

[0024] Applying the data synchronization optimization method between serially connected chips provided by the present invention to the chip;

[0025] The test results show that the clock deviation of the chip optimized by the present invention is within 15%, the serial chip runs continuously for 24 hours, and the maximum cumulative deviation is reduced from 7.2 hours to 17.28 seconds, and the optimization effect is obvious.

[0026] Third, as auxiliary evidence of the inventiveness of the claims of the present invention, it is also reflected in the following important aspects:

[0027] The expected benefits and commercial value of the technical solution of the present invention after transformation are: the optimization design method can be promoted to chip design companies that "need to synchronize data and wait for applications in the same time period between serially connected chips", and corresponding fees can be charged in the form of soft IP. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 It is a flow chart of a method for optimizing data synchronization between serially connected chips provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0031] In view of the problems existing in the prior art, the present invention provides a method, system, device and terminal for optimizing data synchronization between serially connected chips. The present invention is described in detail below with reference to the accompanying drawings.

[0032] like Figure 1 As shown, the data synchronization optimization method between serial chips provided by the embodiment of the present invention includes the following steps:

[0033] S101, using the clock of the first chip in the series connection to count and generate information code;

[0034] S102, encoding the information serially and transmitting it to the subsequent chip, and the subsequent chip counts the codes;

[0035] S103, calculating the clock deviation between each chip in the subsequent stage and the clock of the first chip and performing data synchronization optimization.

[0036] As a preferred embodiment, the data synchronization optimization method between serial chips provided in the embodiment of the present invention specifically includes the following steps:

[0037] Step 1, use the clock of the first chip of the serial chipset to count, and generate information code within a time period when the counter value is not greater than a certain value CNT0;

[0038] Step 2, transmit the information code in serial order to the subsequent chip, which uses its own clock to count the code after receiving it; (1) The first chip counts with its own clock cycle and generates a serial information code of all 1s within CNT0=0 to 10^4 (the signal is low level 0 in other time periods). If the clock of the first chip is accurately 10MHz, then the transmission time of the serial code of all 1s is T0=1ms (however, due to chip flow process deviation, the actual situation may not be 1ms, but the analysis conclusions are consistent); (2) The high-level information code is transmitted serially to the subsequent chip in sequence, and the subsequent chip uses its own clock to count, and the count value is CNT. The CNT value of different subsequent chips may be different;

[0039] Step 3, by calculating the ratio of CNT to CNT0, the deviation value between the clock of each chip in the subsequent stage and the clock of the first chip is calculated; the deviation value of CNT and CNT0 D = (CNT-CNT0) / CNT; if CNT is greater than CNT0, that is, the clock cycle of the chip is smaller than the clock cycle of the first chip, so the count value is large, and D>0 at this time; if CNT is less than CNT0, that is, the clock cycle of the chip is larger than the clock cycle of the first chip, so the count value is small, and D<0 at this time; if CNT is equal to CNT0, that is, the clock cycle of the chip is equal to the clock cycle of the first chip, so the count values ​​are equal, and D=0 at this time;

[0040] Step 4: The subsequent chip uses the deviation value to correct the data to be synchronized and the duration of the chip, so that the data and time period of the subsequent chip are synchronized with the first chip. (1) Test 3 chips in series (as long as the number of chips in series is greater than or equal to 3, the analysis conclusion is consistent). These 3 chips are completely consistent in design. The clock frequency of the chip series transmission is 10MHz. Each chip can control the switch of an LED lamp. It is necessary to realize that the LED lamp controlled by the current chip is turned on 1 hour after the previous LED lamp is turned on. (2) First, the first chip counts with its own clock cycle and generates a serial information code of all 1s within CNT0=0 to 10^4 (the signal is low level 0 in other time periods). If the clock of the first chip is accurately 10MHz, then the transmission time of the serial code of all 1s is T0=1ms (but due to chip flow process deviation, the actual situation may not be 1ms, but the analysis conclusions are consistent); the high-level information code is transmitted backward in sequence, and the subsequent chip uses its own clock to count, and the count value is CNT; (3) Calculate D=(CNT-CNT0) / CNT. The D value of different subsequent chips may be different; (4) If the clock deviation data of the chip manufacturer is + / -15%; (5) If the optimization method described in the present invention is not used (i.e., the subsequent chips all use CNT_ NEW=CNT0_NEW to count), CNT_NEW0 is the count value of the first chip within 1 hour; the maximum time error of each subsequent chip counting CNT_NEW (equal to CNT0_NEW before correction) = 1 hour * 30% = 18 minutes; if it runs continuously for 24 hours, the cumulative maximum error = 24 * 30% = 7.2 hours; (6) If CNT_NEW=(1+D)CNT0_NEW is used to optimize the counting, since the signal sampling uses clock edge counting, it may be more or less 1 cycle within 10^4 cycles, and the error = 2 / 10^4 = 0.02%; then the maximum error of the optimized method in 1 hour = 1 hour * 0.02% = 0.72 seconds, and if it runs continuously for 24 hours, the cumulative maximum error is only = 24 hours * 0.02% = 17.28 seconds. In summary, using the optimized method, the series chip runs continuously for twenty-four hours, and the maximum time cumulative deviation is reduced from the previous 7.2 hours to 17.28 seconds, and the optimization effect is obvious.

[0041] The count value in step 2 provided in the embodiment of the present invention is CNT.

[0042] The data synchronization optimization system between serial chips provided by the embodiment of the present invention includes:

[0043] An information code generating module, used for counting using the clock of the first chip of the serial chipset, and generating information code within a time period when the counter value is not greater than a certain value CNT0;

[0044] The clock encoding counting module is used to transmit the information encoding in series to the subsequent chip. After receiving the encoding, the subsequent chip uses its own clock to count the encoding;

[0045] The clock deviation value calculation module is used to calculate the deviation value between the clock of each chip in the subsequent stage and the clock of the first chip by calculating the ratio of CNT to CNT0;

[0046] The data synchronization optimization module is used for the subsequent chip to use the deviation value to correct the data to be synchronized and the continuous time period of the chip, so that the data and time period of the subsequent chip are synchronized with the first chip.

[0047] In order to prove the creativity and technical value of the technical solution of the present invention, this section provides application examples of the claimed technical solution on specific products or related technologies. (1) Test three chips in series (as long as the number of chips in series is greater than or equal to 3, the analysis conclusion is consistent). These three chips are completely consistent in design. The clock frequency of the chip series transmission is 10MHz. Each chip can control the switch of an LED lamp. It is necessary to realize that the LED lamp controlled by the current chip is turned on one hour after the previous LED lamp is turned on. (2) First, the first chip counts with its own clock cycle and generates a serial information code of all 1s within CNT0=0 to 10^4 (the signal is low level 0 in other time periods). If the clock of the first chip is accurately 10MHz, then the transmission time of the serial code of all 1s is T0=1ms (but due to chip flow process deviation, the actual situation may not be 1ms, but the analysis conclusions are consistent); the high-level information code is transmitted backward in sequence, and the subsequent chip uses its own clock to count, and the count value is CNT; (3) Calculate D=(CNT-CNT0) / CNT. The D value of different subsequent chips may be different; (4) If the clock deviation data of the chip manufacturer is + / -15%; (5) If the optimization method described in the present invention is not used (i.e., the subsequent chips all use CNT_ NEW=CNT0_NEW to count), CNT_NEW0 is the count value of the first chip within 1 hour; the maximum time error of each subsequent chip counting CNT_NEW (equal to CNT0_NEW before optimization) = 1 hour * 30% = 18 minutes; if it runs continuously for 24 hours, the cumulative maximum error = 24 * 30% = 7.2 hours; (6) If CNT_NEW=(1+D)CNT0_NEW is used to optimize the counting, since the signal sampling uses clock edge counting, it may be more or less 1 cycle within 10^4 cycles, and the error = 2 / 10^4 = 0.02%; then the maximum error of the optimized method in 1 hour = 1 hour * 0.02% = 0.72 seconds, and if it runs continuously for 24 hours, the cumulative maximum error is only = 24 hours * 0.02% = 17.28 seconds. In summary, using the optimized method, the series chip runs continuously for twenty-four hours, and the maximum time cumulative deviation is reduced from the previous 7.2 hours to 17.28 seconds, and the optimization effect is obvious.

[0048] An application embodiment of the present invention provides a computer device, which includes a memory and a processor. The memory stores a computer program. When the computer program is executed by the processor, the processor executes the steps of a method for optimizing data synchronization between serial chips.

[0049] An application embodiment of the present invention provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the processor executes the steps of a method for optimizing data synchronization between serially connected chips.

[0050] The application embodiment of the present invention provides an application of a data synchronization optimization method between serially connected chips in a multi-core SoC chip. The multi-core SoC chip is successfully taped out through TSMC 16nm FF+ process, and the die size is 10.7mm×11.9mm.

[0051] The application embodiment of the present invention provides an information data processing terminal, which is used to implement a data synchronization optimization system between serially connected chips.

[0052] It should be noted that the embodiments of the present invention can be implemented by hardware, software, or a combination of software and hardware. The hardware part can be implemented using dedicated logic; the software part can be stored in a memory and executed by an appropriate instruction execution system, such as a microprocessor or dedicated design hardware. It can be understood by a person of ordinary skill in the art that the above-mentioned devices and methods can be implemented using computer executable instructions and / or contained in a processor control code, such as a carrier medium such as a disk, CD or DVD-ROM, a programmable memory such as a read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. Such code is provided on the carrier medium. The device and its modules of the present invention can be implemented by hardware circuits such as very large-scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, etc., or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., can also be implemented by software executed by various types of processors, and can also be implemented by a combination of the above-mentioned hardware circuits and software, such as firmware.

[0053] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with the technical field within the technical scope disclosed by the present invention and within the spirit and principle of the present invention should be covered by the protection scope of the present invention.

Claims

1. A data synchronization optimization method between serially connected chips, characterized in that: The data synchronization optimization method between serial chips includes: using the clock of the first chip of the serial chips to count and generate information code; transmitting the information code to the subsequent chip in serial, and the subsequent chip counts the code; calculating the deviation value between the clock of each subsequent chip and the clock of the first chip, and using the deviation value to optimize the data synchronization between the serial chips; The data synchronization optimization method between serial chips includes the following steps: Step 1: Use the clock of the first chip in the serial chipset to count, and generate information code within a time period when the counter value is not greater than a certain value CNT0; Step 2: The information code is transmitted serially to the subsequent chip, and the subsequent chip uses its own clock to count the code after receiving the code; Step 3: By calculating the ratio of CNT to CNT0, the deviation value between the clock of each chip in the subsequent stage and the clock of the first chip is calculated; Step 4: The subsequent chip uses the deviation value to correct the data to be synchronized and the duration of the chip, so that the data and time period of the subsequent chip are synchronized with the first chip; The count value in step 2 is CNT; specifically, it includes: (1) The first chip counts with its own clock cycle and generates a serial high-level information code of all 1s within CNT0=0 to 10^4. If the clock of the first chip is accurately 10MHz, then the transmission time of the serial high-level information code of all 1s is T0=1ms; (2) The high-level information encoding is transmitted serially to the subsequent chips in turn. The subsequent chips use their own clock to count. The count value is CNT. The CNT value of different subsequent chips may be different.

2. The data synchronization optimization method between serially connected chips as claimed in claim 1, characterized in that: Step three specifically includes: the deviation value D between CNT and CNT0 = (CNT-CNT0) / CNT; if CNT is greater than CNT0, that is, the clock cycle of the chip is smaller than the clock cycle of the first chip, so the count value is large, and D>0 at this time; if CNT is less than CNT0, that is, the clock cycle of the chip is larger than the clock cycle of the first chip, so the count value is small, and D<0 at this time; if CNT is equal to CNT0, that is, the clock cycle of the chip is equal to the clock cycle of the first chip, so the count values ​​are equal, and D=0 at this time.

3. The data synchronization optimization method between serially connected chips as claimed in claim 1, characterized in that: Step 4 specifically includes: (1) Testing three chips in series. These three chips are completely identical in design. The clock frequency of the chips in series transmission is 10 MHz. Each chip can control the switch of an LED light. It is required to realize that the LED light controlled by the current chip is turned on one hour after the previous LED light is turned on. (2) First, the first chip counts with its own clock cycle and generates a serial information code of all 1s within CNT0=0 to 10^4. If the clock of the first chip is accurate to 10MHz, then the transmission time of the serial code of all 1s is T0=1ms. The high-level information code is transmitted backward in sequence, and the subsequent chip uses its own clock to count, and the count value is CNT. (3) Calculate D = (CNT-CNT0) / CNT. The D value of different subsequent chips may be different. (4) If the chip manufacturer's clock deviation data is + / -15%; (5) If all subsequent chips use CNT_NEW=CNT0_NEW to count, CNT_NEW0 is the count value of the first chip within 1 hour; the maximum time error of each subsequent chip counting CNT_NEW = 1 hour * 30% = 18 minutes; if it runs continuously for 24 hours, the cumulative maximum error = 24 * 30% = 7.2 hours; (6) If CNT_NEW=(1+D)CNT0_NEW is used to optimize counting, since signal sampling uses clock edge counting, there may be more or less 1 cycle in 10^4 cycles, and the error = 2 / 10^4 = 0.02%; then the maximum error of the optimized method in 1 hour = 1 hour * 0.02% = 0.72 seconds. If it runs continuously for 24 hours, the cumulative maximum error is only = 24 hours * 0.02% = 17.28 seconds.

4. A data synchronization optimization system between serial chips using the data synchronization optimization method between serial chips as described in any one of claims 1 to 3, characterized in that: The data synchronization optimization system between serial chips includes: An information code generating module, used for counting using the clock of the first chip of the serial chipset, and generating information code within a time period when the counter value is not greater than a certain value CNT0; The clock encoding counting module is used to transmit the information encoding in series to the subsequent chip. After receiving the encoding, the subsequent chip uses its own clock to count the encoding; The clock deviation value calculation module is used to calculate the deviation value between the clock of each chip in the subsequent stage and the clock of the first chip by calculating the ratio of CNT to CNT0; The data synchronization optimization module is used for the subsequent chip to use the deviation value to correct the data to be synchronized and the continuous time period of the chip, so that the data and time period of the subsequent chip are synchronized with the first chip.

5. A computer device, characterized in that: The computer device includes a memory and a processor, the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the data synchronization optimization method between serial chips as described in any one of claims 1 to 3.

6. A computer-readable storage medium storing a computer program, which, when executed by a processor, enables the processor to execute the steps of the method for optimizing data synchronization between serially connected chips as described in any one of claims 1 to 3.

7. An information data processing terminal, characterized in that: The information data processing terminal is used to implement the data synchronization optimization system between serially connected chips as described in claim 4.

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