A multi-channel neural signal compression system applied to brain-computer interface and a method thereof

Abstract

The application relates to a multi-channel neural signal compression system applied to a brain-computer interface and a method thereof. The system comprises an FPGA development board connected with a multi-channel ADC acquisition chip. The FPGA development board is provided with a signal input preprocessing module, a compression method selection module, a compression module and a storage module. The multi-channel ADC acquisition chip is used for acquiring multi-channel neural signals. The signal input preprocessing module is used for preprocessing the multi-channel neural signals to obtain a neural signal sparse matrix. The compression method selection module is used for dynamically selecting a corresponding compression method according to the matrix characteristics of the neural signal sparse matrix. The compression module is used for running the dynamically selected compression method to compress the neural signal sparse matrix to obtain a compressed signal. The storage module is used for storing the compressed signal. Compared with the prior art, the application can efficiently and accurately compress multi-channel neural signals at low cost and low power consumption.

Description

Technical Field

[0001] This invention relates to the field of brain-computer interface information processing technology, and in particular to a multi-channel neural signal compression system and method for use in brain-computer interfaces. Background Technology

[0002] Over the past four decades, the research and development of brain-computer interfaces (BCIs) have garnered increasing attention from the scientific community and the public, becoming one of the most important tools in neuroscience research and the development of neurorehabilitation. Multi-channel neural signal acquisition and real-time signal transmission are core technologies of BCIs. Acquiring neural signals is challenging due to their weakness, large number of channels, and high sampling rate. Currently, Neuralink has developed small and flexible electrode arrays (3072 electrodes per array), enabling the recording of thousands of neural signals. However, large-scale multi-channel neural signal recording presents challenges to the power consumption and area of ​​the recorder chip. First, the neural recording system needs to provide users with more useful information; second, signal transmission becomes more challenging due to the large number of electrodes and the limited on-chip power budget available for real-time processing and transmission. Furthermore, the high temporal and spatial correlation of data means that directly transmitting raw data consumes enormous power. Therefore, it is necessary to compress the neural data in the recorder chip before signal transmission to reduce data volume and power consumption, which is crucial for information extraction in implantable BCIs.

[0003] To address this, researchers have conducted extensive work on methods for compressing the data volume of neural signals containing action potentials. For example, based on the characteristics that action potentials in neural signals are greater than noise, and that noise data accounts for a large proportion of the signal, some studies have explored data compression methods that extract action potentials and transmit only the action potential signals during data transmission. The data compression ratio of this type of method is determined by the action potential content of the signal itself, and it is relatively prone to missed detections and false detections. In addition, based on the sparsity of action potentials in the wavelet domain, some studies have explored methods that compress the data volume by performing wavelet transforms on neural signals and then using a large correlation coefficient to represent the original signal before transmission. This type of method can achieve a large compression ratio and high reliability, but the data processing method is complex and computationally intensive, and the increased complexity and computational intensity can easily lead to increased power consumption.

[0004] Another study proposed a single-channel low-power hardware accelerator for lossless compression of adaptive neural signals. This accelerator consists of an improved second-order differential pulse code modulation and an adaptive coding engine. Although the simulation and implementation results are better than previous studies, it still does not have good high data compression capability. Another study developed a deep learning-based compression model to reduce the data rate of multi-channel action potentials. This compression model is built on a deep compression autoencoder. This model improves the compression rate of neural data and has a high data throughput, but due to the complexity of the model, its hardware resource consumption is relatively high. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art by providing a multi-channel neural signal compression system and method for brain-computer interfaces, which can compress multi-channel neural signals efficiently and accurately at low cost and low power consumption.

[0006] The objective of this invention can be achieved through the following technical solution: a multi-channel neural signal compression system for brain-computer interfaces, comprising a multi-channel ADC (Analog-to-Digital Converter) acquisition chip, wherein the multi-channel ADC acquisition chip is connected to an FPGA (Field Programmable Gate Array) development board, wherein the FPGA development board is provided with a signal input preprocessing module, a compression method selection module, a compression module and a storage module, and the multi-channel ADC acquisition chip is used to acquire multi-channel neural signals;

[0007] The signal input preprocessing module is used to preprocess multi-channel neural signals to obtain a sparse matrix of neural signals;

[0008] The compression method selection module is used to dynamically select the appropriate compression method based on the matrix characteristics of the sparse matrix of the neural signal.

[0009] The compression module is used to run a dynamically selected compression method to compress the sparse matrix of neural signals to obtain the compressed signal.

[0010] The storage module is used to store the compressed signal.

[0011] Furthermore, the multi-channel ADC acquisition chip is specifically a 32-channel ADC acquisition chip MTXR32P.

[0012] Furthermore, the FPGA development board is specifically XC7Z020-2CLG400I.

[0013] A method for compressing multi-channel neural signals for brain-computer interfaces includes the following steps:

[0014] S1. Acquire multi-channel neural signals according to control instructions;

[0015] S2. Preprocess the acquired multi-channel neural signals to convert them into a sparse neural signal matrix containing only "0" and "1".

[0016] S3. Count the number of neural spike signals in the sparse matrix of neural signals, that is, the number of valid non-zero values ​​in the sparse matrix.

[0017] S4. Based on the statistical results of step S3, further calculate the sparsity of the neural signal sparse matrix and determine whether the sparsity is less than the preset sparsity threshold. If the determination is yes, proceed to step S7; otherwise, proceed to step S5.

[0018] S5. Determine if the current neural signal sparse matrix is ​​a non-neural signal sparse matrix, return to step S2, and preprocess the non-neural signal sparse matrix again.

[0019] If the result obtained from step S2 after N iterations is still a sparse matrix of non-neural signals, then proceed to step S6.

[0020] S6. If the matrix data is found to be incorrect, discard it or do not process it, and end the current compression process.

[0021] S7. Determine whether the number of spike signals in the sparse matrix of neural signals within the preset adaptation time window scale is greater than the number of sampling channels. If yes, proceed to step S8; otherwise, proceed to step S9.

[0022] S8. Compress and store the sparse matrix of neural signals using the CSR (Compress Sparse Row) compression method.

[0023] S9. Compress and store the sparse matrix of neural signals using the COO (Coordinate, triplet) compression method.

[0024] Furthermore, the preprocessing process in step S2 includes data filtering and peak potential threshold detection. The data filtering is used to filter out LFP (local field potential) in the neural signal.

[0025] The peak potential threshold detection specifically employs a threshold detection method to detect spike signals in neural signals. The digital marker at the output of the neural signal is defined as 1 when the signal value exceeds a preset spike threshold and 0 at other times.

[0026] Furthermore, the data filtering specifically employs a bandpass filter to filter out LFPs less than 300Hz in the neural signal.

[0027] Furthermore, the specific formula for calculating the sparsity of the neural signal sparse matrix in step S4 is as follows:

[0028] Sparsity = Number of non-zero elements in the matrix / Total number of elements in the matrix.

[0029] Furthermore, the preset sparsity threshold in step S4 is specifically 5‰.

[0030] Furthermore, in step S5, N = 3.

[0031] Furthermore, the preset adaptation time window scale in step S7 is specifically 3ms.

[0032] Compared with the prior art, the present invention has the following advantages:

[0033] I. This invention connects a multi-channel ADC acquisition chip to an FPGA development board. The FPGA development board includes a signal input preprocessing module, a compression method selection module, a compression module, and a storage module. The multi-channel ADC acquisition chip acquires multi-channel neural signals; the signal input preprocessing module preprocesses the multi-channel neural signals to obtain a sparse neural signal matrix; the compression method selection module dynamically selects the appropriate compression method based on the matrix characteristics of the sparse neural signal matrix; the compression module runs the dynamically selected compression method to compress the sparse neural signal matrix, obtaining the compressed signal; and the storage module stores the compressed signal. This enables real-time compression processing of multi-channel neural signals on an embedded hardware platform, offering advantages such as low cost and low power consumption. Furthermore, by employing a novel method of constructing a sparse matrix from multi-channel neural signals, the invention dynamically selects the appropriate compression method based on the characteristics of the sparse neural signal matrix, ensuring the reliability and accuracy of the compression.

[0034] Second, this invention utilizes the refractory period characteristic of neuronal action potential signals and considers that the digitally labeled output of multi-channel neural signals can be defined as a sparse matrix over a certain time scale. Therefore, it designs a method for feature extraction within the sparse matrix composed of acquired multi-channel neural signals, and dynamically selects a classical compression algorithm to compress the neural signal sparse matrix based on its matrix characteristics. Compared to traditional fixed compression methods, this approach offers advantages in terms of high flexibility and high reliability. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the system structure of the present invention;

[0036] Figure 2 This is a schematic diagram of the method flow of the present invention;

[0037] Figure 3 This is a comparative illustration of the COO compression method and the CSR compression method.

[0038] Figure 4 This is a schematic diagram of the hardware architecture connection in the embodiment;

[0039] Figure 5 This is a schematic diagram of the FPGA development board's operation process in the embodiment;

[0040] Figures 6a-6c This is a schematic diagram of the hardware in the embodiment;

[0041] The markings in the diagram are as follows: 1. Multi-channel ADC acquisition chip; 2. FPGA development board; 201. Signal input preprocessing module; 202. Compression method selection module; 203. Compression module; 204. Storage module. Detailed Implementation

[0042] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0043] Example

[0044] like Figure 1 As shown, a multi-channel neural signal compression system for brain-computer interfaces includes a multi-channel ADC acquisition chip 1, which is connected to an FPGA development board 2. The FPGA development board 2 is equipped with a signal input preprocessing module 201, a compression method selection module 202, a compression module 203, and a storage module 204. The multi-channel ADC acquisition chip 1 is used to acquire multi-channel neural signals.

[0045] The signal input preprocessing module 201 is used to preprocess multi-channel neural signals to obtain a sparse matrix of neural signals;

[0046] The compression method selection module 202 is used to dynamically select the appropriate compression method based on the matrix characteristics of the sparse matrix of the neural signal.

[0047] The compression module 203 is used to run a dynamically selected compression method to compress the sparse matrix of neural signals and obtain the compressed signal.

[0048] Storage module 204 is used to store the compressed signal.

[0049] Using the above system, a multi-channel neural signal compression method for brain-computer interfaces is implemented, such as... Figure 2 As shown, it includes the following steps:

[0050] S1. Acquire multi-channel neural signals according to control instructions;

[0051] S2. Preprocess the acquired multi-channel neural signals to convert them into a sparse neural signal matrix containing only "0" and "1".

[0052] S3. Count the number of neural spike signals in the sparse matrix of neural signals, that is, the number of valid non-zero values ​​in the sparse matrix.

[0053] S4. Based on the statistical results of step S3, further calculate the sparsity of the neural signal sparse matrix and determine whether the sparsity is less than the preset sparsity threshold (in this embodiment, the preset sparsity threshold is set to 5‰). If the determination is yes, then execute step S7; otherwise, execute step S5.

[0054] S5. Determine if the current neural signal sparse matrix is ​​a non-neural signal sparse matrix, return to step S2, and preprocess the non-neural signal sparse matrix again.

[0055] If the result obtained from step S2 after N iterations is still a sparse matrix of non-neural signals, then step S6 is executed. In this embodiment, N = 3.

[0056] S6. If the matrix data is found to be incorrect, discard it or do not process it, and end the current compression process.

[0057] S7. Determine whether the number of spike signals in the sparse matrix of neural signals within the preset adaptation time window scale is greater than the number of sampling channels. If yes, proceed to step S8; otherwise, proceed to step S9.

[0058] In this embodiment, the preset adaptation time window scale of the sparse matrix of neural signals is set to 3ms;

[0059] S8. Compress and store the sparse matrix of neural signals using the CSR (Compress Sparse Row) compression method.

[0060] S9. Compress and store the sparse matrix of neural signals using the COO (Coordinate, triplet) compression method.

[0061] Among them, the COO triplet is the simplest storage format. Each non-zero element in the matrix needs to be represented by a triplet, which consists of its value, row number, and column number, corresponding to... Figure 3 values, rows, and cols;

[0062] CSR is a relatively standard storage format that also requires three types of data to represent data: value, column number, and row offset, which correspond to... Figure 3In CSR, values, cols, and row offsets are not triples, but rather a whole encoding method. The values ​​and column numbers are consistent with COO, representing an element and its column number. The row offset represents the starting offset position of the first element in a row within values. Compared to the COO method, row values ​​are compressed when stored.

[0063] This embodiment applies the above-described technical solution, such as Figure 4 , 5 6a~6c (wherein, Figure 6a This corresponds to the audio representation of the collected mouse neural signals. Figure 6b This corresponds to the physical illustration of the 32-channel low-power, low-noise signal acquisition chip MTXR32P. Figure 6c The diagram shows a physical example of an FPGA development board (model XC7Z020-2CLG400I). A simulated 32-channel neural signal dataset is used as the data source to compress multi-channel neural signals. To verify the effectiveness of this technical solution, a logic analyzer is also connected to the output of the FPGA development board.

[0064] The working process of this embodiment mainly includes:

[0065] First, the FPGA control terminal sends control signals to the front-end multi-channel ADC acquisition chip to obtain the acquired 32-channel neural signals, and then executes step two.

[0066] 2. The FPGA control terminal performs preprocessing on the multi-channel neural signals: First, the local field potential (LFP) in the neural signals is filtered out. LFP is generally less than 300Hz. The commonly used bandpass filter to filter out LFP is 300-3000Hz.

[0067] Then, a threshold detection method is used to detect spike signals in the neural signal (the digital markers at the output of the neural signal are defined as 1 when the signal value exceeds the threshold and 0 at other times), and it is converted into a 32*45000 sparse matrix, and then step three is executed;

[0068] 3. The number of spike signals in the sparse matrix is ​​calculated to be 3501. Proceed to step 4.

[0069] 4. Determine whether the sparsity of this sparse matrix is ​​greater than or equal to 5‰. If yes, proceed to step 5; otherwise, proceed to step 7. The matrix sparsity is calculated as sparsity = number of non-zero elements in the matrix (i.e., number of spike signals) / total number of elements in the matrix.

[0070] 5. Determine if this matrix is ​​a non-neural signal sparse matrix. Return this matrix to step 2 for preprocessing. If the result of the three processing steps is still a non-neural signal sparse matrix, then proceed to step 6.

[0071] 6. If this matrix is ​​determined to be a non-neural signal sparse matrix, it indicates a data acquisition error, and the data is discarded without any processing.

[0072] 7. Pre-set the adaptation time window scale value of the sparse matrix of neural signals to 3ms, which corresponds to the digital label 450 in the hardware, and then execute step 8.

[0073] 8. Determine whether the number of spike signals in the sparse matrix of the neural signal within a time scale of 450 (3ms) is greater than the number of sampling channels, 32. If yes, proceed to step 9; otherwise, proceed to step 10.

[0074] 9. Compress and store the sparse matrix within this time scale using the CSR compression method;

[0075] 10. Compress and store the sparse matrix within this timescale using the COO compression method.

[0076] In this embodiment, SSR (space saving ratio) is used as the compression performance evaluation standard. SSR is used to indicate the proportion of data reduction. The larger the compression value, the better the compression result.

[0077] The definition of SSR is:

[0078] SSR% = 1 - Number of bits in compressed data / Number of bits in original data

[0079] In this embodiment, 12 datasets from the following literature were compressed, and their average SSR was 85%, which fully demonstrates that the proposed scheme has a good compression effect.

[0080] QUIROGA RQ,NADASDY Z,BEN-SHAUL Y.Unsupervised spike detection and sorting with wavelets and superparamagnetic clustering[J].Neural Comput,2004,16(8):1661-87.

[0081] In summary, this technical solution addresses the issue that the optimal compression method varies for sparse matrices composed of multiple neural signals under different time domains and similar sparsity levels. Therefore, a dynamic sparse compression algorithm based on sparse matrices composed of multi-channel neural signals—Meanswin—is designed. Since the digitally labeled output of multi-channel neural signals can be defined as a sparse matrix over a certain time scale, the refractory period of neuronal action potential signals can be utilized to extract features from the acquired sparse matrix of multi-channel neural signals. Based on these features, a compression algorithm is dynamically selected to compress the sparse matrix of neural signals.

[0082] This scheme treats the digital output label of the multi-channel neural spike signal in the time domain as a huge sparse matrix, thereby enabling the compression of multi-channel neural signals using traditional sparse matrix compression methods.

[0083] This scheme, based on the analysis of the results of compressing sparse matrices of neural signals using the classical sparse matrix compression method, transforms a fixed compression method into a dynamic and selectable compression method by studying the matrix characteristics of the sparse matrix of neural signals.

[0084] This solution, through real-time application on an embedded hardware platform, is low-cost and highly reliable, enabling multi-channel, high-speed data transmission in brain-computer interfaces, thus making it practical and of great significance to the research and development of brain-computer interfaces.

Claims

1. A multi-channel neural signal compression system for brain-computer interfaces, characterized in that, The device includes a multi-channel ADC acquisition chip, which is connected to an FPGA development board. The FPGA development board is equipped with a signal input preprocessing module, a compression method selection module, a compression module, and a storage module. The multi-channel ADC acquisition chip is used to acquire multi-channel neural signals. The signal input preprocessing module is used to preprocess multi-channel neural signals to obtain a sparse matrix of neural signals; The compression method selection module is used to dynamically select the appropriate compression method based on the matrix characteristics of the sparse matrix of the neural signal. Specifically, the number of neural spike signals in the sparse matrix of neural signals is counted, that is, the number of valid non-zero values ​​in the sparse matrix. Then, the sparsity of the sparse matrix of neural signals is calculated, and it is determined whether the sparsity is less than the preset sparsity threshold. If it is, it is further determined whether the number of spike signals in the sparse matrix of neural signals within the preset adaptation time window scale is greater than the number of sampling channels. If it is, the CSR compression method is selected. Otherwise, choose the COO compression method; The compression module is used to run a dynamically selected compression method to compress the sparse matrix of neural signals to obtain the compressed signal. The storage module is used to store the compressed signal.

2. The multi-channel neural signal compression system for brain-computer interfaces according to claim 1, characterized in that, The multi-channel ADC acquisition chip is specifically the 32-channel ADC acquisition chip MTXR32P.

3. The multi-channel neural signal compression system for brain-computer interfaces according to claim 1, characterized in that, The FPGA development board is specifically XC7Z020-2CLG400I.

4. A multi-channel neural signal compression method applying the multi-channel neural signal compression system for brain-computer interfaces as described in claim 1, characterized in that, Includes the following steps: S1. Acquire multi-channel neural signals according to control instructions; S2. Preprocess the acquired multi-channel neural signals to convert them into a sparse neural signal matrix containing only "0" and "1". The preprocessing process includes data filtering and peak potential threshold detection, wherein the data filtering is used to filter out LFPs in the neural signal; The peak potential threshold detection specifically employs a threshold detection method to detect spike signals in neural signals, defining a digital marker at the output of the neural signal as 1 when the signal value exceeds a preset spike threshold and 0 at other times. S3. Count the number of neural spike signals in the sparse matrix of neural signals, that is, the number of valid non-zero values ​​in the sparse matrix. S4. Based on the statistical results of step S3, further calculate the sparsity of the neural signal sparse matrix and determine whether the sparsity is less than the preset sparsity threshold. If the determination is yes, proceed to step S7; otherwise, proceed to step S5. S5. Determine if the current neural signal sparse matrix is ​​a non-neural signal sparse matrix, return to step S2, and preprocess the non-neural signal sparse matrix again. If the result obtained from step S2 after N iterations is still a sparse matrix of non-neural signals, then proceed to step S6. S6. If the matrix data is found to be incorrect, discard it or do not process it, and end the current compression process. S7. Determine whether the number of spike signals in the sparse matrix of neural signals within the preset adaptation time window scale is greater than the number of sampling channels. If so, proceed to step S8. Otherwise, proceed to step S9; S8. Compress and store the sparse matrix of neural signals using the CSR compression method; S9. Compress and store the sparse matrix of neural signals using the COO compression method.

5. The multi-channel neural signal compression method according to claim 4, characterized in that, The data filtering specifically employs a bandpass filter to filter out LFP frequencies below 300Hz in the neural signal.

6. The multi-channel neural signal compression method according to claim 4, characterized in that, The specific formula for calculating the sparsity of the sparse matrix of the neural signal in step S4 is as follows: Sparsity = Number of non-zero elements in the matrix / Total number of elements in the matrix.

7. The multi-channel neural signal compression method according to claim 4, characterized in that, The preset sparsity threshold in step S4 is specifically 5‰.

8. The multi-channel neural signal compression method according to claim 4, characterized in that, In step S5, N=3.

9. A multi-channel neural signal compression method according to claim 4, characterized in that, The preset adaptation time window size in step S7 is specifically 3ms.

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