Acoustic resonator and preparation method thereof, and filter

Abstract

The present invention relates to the field of semiconductor technology, and in particular to an acoustic resonator and a preparation method thereof, and a filter. The acoustic resonator comprises a supporting substrate, a piezoelectric film layer, and an interdigital electrode structure arranged in sequence from bottom to top, wherein a polygonal cavity is provided in the supporting substrate; the supporting substrate is a {111} single crystal silicon substrate; the peripheral surface of the polygonal cavity comprises silicon <110> The piezoelectric film layer is close to the polygonal cavity, and the piezoelectric film layer is provided with a plurality of etched through holes, and the plurality of etched through holes are connected to the polygonal cavity. The acoustic resonator provided by the present application has excellent electrical and mechanical properties.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an acoustic resonator and a preparation method thereof, and a filter. Background Art

[0002] With the rapid development of communication technology, acoustic resonators are required to have higher frequency and bandwidth.

[0003] However, in the prior art, the acoustic resonator is usually a surface acoustic wave resonator or a bulk acoustic wave resonator. The surface acoustic wave resonator is composed of a substrate, a piezoelectric film and a metal electrode. The preparation process is to bond the substrate to the piezoelectric film and then prepare the metal electrode on the piezoelectric film layer. The acoustic resonator of the above structure has the disadvantages of low frequency and low bandwidth. Summary of the invention

[0004] In order to solve the above technical problems, the present application discloses an acoustic resonator, which includes:

[0005] A support substrate is provided with a polygonal cavity in the support substrate; the support substrate is a {111} single crystal silicon substrate; the peripheral surface of the polygonal cavity includes silicon <110> Crystal orientation;

[0006] A piezoelectric film layer is located on a supporting substrate, the piezoelectric film layer is close to the polygonal cavity, and the piezoelectric film layer is provided with a plurality of etched through holes, the plurality of etched through holes are connected to the polygonal cavity; the electrical characteristics of the acoustic resonator can be adjusted by adjusting the height of the etched through holes;

[0007] and an interdigitated electrode structure located on the piezoelectric film layer.

[0008] In a feasible embodiment, the top surface and the bottom surface of the polygonal cavity are {111} crystal planes, or the bottom surface of the polygonal cavity is a {111} crystal plane.

[0009] In a feasible embodiment, the shape of the polygonal cavity projected onto the bottom surface of the piezoelectric film layer is a hexagon.

[0010] In a feasible embodiment, the distance between the piezoelectric film layer and the polygonal cavity is greater than zero and less than or equal to 1000 nanometers.

[0011] In a feasible embodiment, it further includes a dielectric layer;

[0012] The dielectric layer is located between the piezoelectric film layer and the supporting substrate, or the dielectric layer is located on the piezoelectric film layer;

[0013] The material of the dielectric layer is SiO x , SiN x , any one or more of Al2O3, AlN, and SiC.

[0014] In a feasible embodiment, the interdigital electrode structure includes a first bus bar, a plurality of first interdigital electrodes connected to the first bus bar, a second bus bar, and a plurality of second interdigital electrodes connected to the second bus bar;

[0015] A plurality of first interdigital electrodes and a plurality of second interdigital electrodes are arranged in a staggered manner;

[0016] The plurality of etched through holes are distributed in the region between the first interdigital electrode and the second bus bar, and in the region between the second interdigital electrode and the first bus bar; or, the plurality of etched through holes are distributed in the region between adjacent interdigital electrodes.

[0017] In a feasible embodiment, the distance between the center line of the adjacent first interdigital electrodes and the center line of the adjacent second interdigital electrodes is greater than 2 micrometers;

[0018] The metallization rate of the interdigital electrode structure is greater than or equal to 5% and less than or equal to 40%.

[0019] In a feasible embodiment, the material of the piezoelectric film layer is lithium niobate or lithium tantalate.

[0020] In a feasible embodiment, the crystal cut of the piezoelectric film layer is a Z-cut or a YXθ-cut, and θ satisfies 80°≤θ≤180°.

[0021] In a feasible embodiment, the thickness of the piezoelectric film layer is greater than or equal to 100 nanometers and less than or equal to 900 nanometers.

[0022] The present application further provides a method for preparing the above-mentioned acoustic resonator, which comprises:

[0023] A piezoelectric structure is provided; the piezoelectric structure comprises a stacked support substrate and a piezoelectric film layer; the support substrate is a {111} single crystal silicon substrate;

[0024] Performing front etching on the piezoelectric structure from the surface of the piezoelectric film layer to form a plurality of etched through holes in the piezoelectric structure;

[0025] preparing an interdigitated electrode structure on the piezoelectric film layer;

[0026] The supporting substrate is anisotropically etched by a wet etching process to form a polygonal cavity in the supporting substrate; the polygonal cavity is connected to a plurality of etched through holes.

[0027] In a feasible embodiment, the top surface and the bottom surface of the polygonal cavity are {111} crystal planes, or the bottom surface of the polygonal cavity is a {111} crystal plane.

[0028] In a feasible embodiment, before anisotropically etching the support substrate using a wet etching process to form a polygonal cavity in the support substrate, the method further includes:

[0029] A dielectric layer is prepared on the interdigital electrode structure.

[0030] In a feasible embodiment, a dielectric layer is provided between the supporting substrate and the piezoelectric film layer.

[0031] On the other hand, the present application also discloses a filter, which includes at least two of the above-mentioned acoustic resonators; at least two acoustic resonators are electrically connected in series or in parallel to form the filter, and the frequency of the series acoustic resonator is greater than the frequency of the parallel acoustic resonator.

[0032] By adopting the above technical solution, an acoustic resonator provided in the present application has the following beneficial effects:

[0033] The acoustic resonator comprises a supporting substrate, in which a polygonal cavity is arranged; the supporting substrate is a {111} single crystal silicon substrate; the peripheral surface of the polygonal cavity comprises silicon <110> The invention relates to a piezoelectric film layer located on a supporting substrate, the piezoelectric film layer is close to the polygonal cavity, and the piezoelectric film layer is provided with a plurality of etched through holes, and the plurality of etched through holes are connected to the polygonal cavity; the electrical characteristics of the acoustic resonator can be adjusted by adjusting the height of the etched through holes; and an interdigitated electrode structure located on the piezoelectric film layer. Since the supporting substrate is a {111} single crystal silicon substrate, the circumference of the polygonal cavity includes a silicon <110> Crystal direction, thereby effectively ensuring the etching accuracy of the polygonal cavity, so that the acoustic resonator containing the polygonal cavity has the characteristics of high frequency and high bandwidth, and has higher structural stability, better preparation accuracy and lower cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 is a schematic structural diagram of an acoustic resonator provided in an embodiment of the present application;

[0036] Figure 2 is a schematic diagram of a silicon unit cell structure provided in an embodiment of the present application;

[0037] Figure 3 is a cross-sectional view of an acoustic resonator provided in an embodiment of the present application;

[0038] Figure 4 is a top view of a first acoustic resonator provided in an embodiment of the present application;

[0039] Figure 5 is a cross-sectional view of another acoustic resonator provided in an embodiment of the present application;

[0040] Figure 6 is a top view of a second acoustic resonator provided in an embodiment of the present application;

[0041] Figure 7 is a top view of a third acoustic resonator provided in an embodiment of the present application;

[0042] Figure 8 It is a schematic diagram of a process for preparing an acoustic resonator provided in an embodiment of the present application;

[0043] Fig. 9 It is a schematic diagram of a process for preparing an acoustic resonator provided in an embodiment of the present application;

[0044] Fig.10 1 is a simulated admittance response diagram of two acoustic resonators provided in an embodiment of the present application;

[0045] Fig.11 is a structural schematic diagram of a filter provided in an embodiment of the present application;

[0046] Fig.12 This is a top view of a filter provided in an embodiment of the present application.

[0047] The following is a supplementary description of the attached drawings:

[0048] 1-support substrate; 11-polygonal cavity; 2-piezoelectric film layer; 3-etched through hole; 4-interdigitated electrode structure; 41-first bus bar; 42-first interdigitated electrode; 43-second bus bar; 44-second interdigitated electrode; 5-dielectric layer. DETAILED DESCRIPTION

[0049] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0050] The term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present application. In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "top", "bottom", etc. is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may include one or more of the features explicitly or implicitly. Moreover, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here.

[0051] For the purpose of the following detailed description, it should be understood that the present invention may adopt various alternative changes and step sequences, unless expressly specified to the contrary. In addition, except in any operating examples, or otherwise indicated, all numbers representing the amount of ingredients used in the specification and claims should be understood to be modified by the term "about" in all cases. Therefore, unless otherwise indicated, the numerical parameters set forth in the following specification and the attached claims are approximate values ​​that vary according to the desired performance to be obtained by the present invention. At least it is not intended to limit the application of the doctrine of equivalents to the scope of the claims, and each numerical parameter should at least be interpreted according to the number of reported significant figures and by applying ordinary rounding techniques.

[0052] Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the invention are approximations, the numerical values ​​set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements.

[0053] When a numerical range is disclosed herein, the above range is deemed to be continuous and includes the minimum and maximum values ​​of the range, as well as each value between such minimum and maximum values. Further, when a range refers to an integer, each integer between the minimum and maximum values ​​of the range is included. In addition, when multiple ranges are provided to describe features or characteristics, the ranges can be merged. In other words, unless otherwise indicated, all ranges disclosed herein should be understood to include any and all sub-ranges included therein. For example, a specified range from "1 to 10" should be deemed to include any and all sub-ranges between a minimum of 1 and a maximum of 10. Exemplary sub-ranges of ranges 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.

[0054] Example 1

[0055] See also Figure 1 , Figure 1 1 is a schematic diagram of the structure of an acoustic resonator provided in an embodiment of the present application. The acoustic resonator comprises: a support substrate 1, a piezoelectric film layer 2 located on the support substrate 1, and an interdigitated electrode structure 4 located on the piezoelectric film layer 2. A polygonal cavity 11 is provided in the support substrate 1, and the support substrate 1 is a {111} single crystal silicon substrate. The peripheral surface of the polygonal cavity 11 comprises silicon <110> piezoelectric film layer 2 is close to the polygonal cavity 11, and the piezoelectric film layer 2 is provided with a plurality of etched through holes 3, and the plurality of etched through holes 3 are connected to the polygonal cavity 11; by adjusting the height of the etched through holes 3, the electrical characteristics of the acoustic resonator can be adjusted.

[0056] See also Figure 2 , Figure 2 Schematic diagram of a silicon unit cell structure provided in the embodiment of the present application. <110> Crystal orientation refers to silicon <110> The crystal orientation family, i.e., the crystal orientation in the same plane as the

[110] crystal orientation, may specifically include the silicon

[101] crystal orientation, the silicon

[011] crystal orientation, and the silicon

[110] crystal orientation. Similarly, the {111} crystal plane involved in this application refers to the {111} crystal plane family, which may specifically include the (11-1), (1-1-1), (-1-1-1), and other crystal planes. Please refer to Figure 1 There is a preset angle α between the circumference of the polygonal cavity 11 and the bottom surface of the polygonal cavity 11, which can be an acute angle, such as about 70.5°.

[0057] In a feasible embodiment, the top and bottom surfaces of the polygonal cavity 11 are {111} crystal planes, or the bottom surface of the polygonal cavity 11 is {111} crystal planes. Figure 1 As shown, there is a silicon film layer between the piezoelectric film layer 2 and the polygonal cavity 11, and the bottom surface of the polygonal cavity 11 is a {111} crystal plane. Optionally, it can also be as follows Figure 3In the structure shown, the top surface of the polygonal cavity 11 is the bottom of the piezoelectric film layer 2, and only the bottom surface of the polygonal cavity 11 is a {111} crystal plane. Figure 1 The projection of the polygonal cavity 11 on the xz plane is a parallelogram. In the process of wet etching to form the air cavity, since the upper and lower surfaces of the polygonal cavity 11 are both silicon {111} crystal planes, the etching rate is extremely low. Therefore, the thickness of the Si{111} film is determined by the etching depth of the etched through hole 3 and is not affected by the wet etching step, which has the advantage of high controllable etching accuracy.

[0058] In a feasible embodiment, the distance between the piezoelectric film layer 2 and the polygonal cavity 11 is greater than zero and less than or equal to 1000 nanometers. In other words, the thickness of the silicon film layer is greater than zero and less than or equal to 1000 nanometers. When the silicon film layer is present, the cooperation of the silicon film layer and the piezoelectric film layer 2 can achieve higher frequency and bandwidth, and improve the stability and heat dissipation of the device.

[0059] In one possible embodiment, see Figure 4 The shape of the polygonal cavity 11 projected on the bottom surface of the piezoelectric film layer 2 is a hexagon (eg Figure 4 The dashed box in the figure); each side of the hexagon is <110> Crystal orientation. Optional, Figure 1 Shown is Figure 4 The cross-sectional view corresponding to the dotted line AA'.

[0060] In a feasible embodiment, the acoustic resonator further comprises a dielectric layer 5, and the dielectric layer 5 is located between the piezoelectric film layer 2 and the supporting substrate 1 (see Figure 5 ), or the dielectric layer 5 can also be located on the piezoelectric film layer 2 (see Figure 3 ); the material of the dielectric layer 5 is SiO x , SiN x , Al2O3, AlN, SiC, any one or more thereof, wherein x varies in value based on different precipitation conditions. The position and material of the dielectric layer 5 can be selected as needed. The setting of the dielectric layer 5 can affect the electrical properties, structural stability and temperature stability of the acoustic resonator. For example, when the material of the dielectric layer 5 is silicon oxide, the device quality and temperature stability can be improved. Aluminum oxide can be used as a bonding material to improve the bonding strength between the piezoelectric film layer 2 and the supporting substrate 1, and to improve the thermal mismatch problem of the device during subsequent annealing. Silicon carbide can improve the heat dissipation performance of the device.

[0061] It can be understood that the working mode of the acoustic resonator provided in the present application is a high-order Lamb wave, and the order N satisfies the relationship: 1≤N≤n, where n is the total number of layers of the suspended membrane. Figure 1The structure shown is a double-layer suspended membrane structure (i.e., including a piezoelectric film layer 2 and a silicon film layer), so the Lamb wave can be either first-order or second-order, depending on actual design requirements. The number and type of dielectric layers specifically set are not limited to the above one.

[0062] In one possible embodiment, see Figure 4 , the interdigitated electrode structure 4 includes a first bus bar 41, a plurality of first interdigitated electrodes 42 connected to the first bus bar 41, a second bus bar 43 and a plurality of second interdigitated electrodes 44 connected to the second bus bar 43; the plurality of first interdigitated electrodes 42 and the plurality of second interdigitated electrodes 44 are arranged alternately; a plurality of etched through holes 3 are distributed in the area between the first interdigitated electrodes 42 and the second bus bar 43, and in the area between the second interdigitated electrodes 44 and the first bus bar 41; or, a plurality of etched through holes 3 are distributed in the area between adjacent first interdigitated electrodes 42 and second interdigitated electrodes 44. The etched through holes 3 may be gaps distributed between the ends of the interdigitated electrodes and the corresponding adjacent bus bars. This distribution structure will affect the heat dissipation of the interdigitated electrode area to a certain extent, which is not conducive to the improvement of power capacity. For example, assuming that the distance between the first bus bar 41 and the second bus bar 43 is H, the distribution of the etched through holes 3 is as follows Figure 4 As shown, the etching rate of each etched through hole 3 in the y direction is the same, so each etched through hole 3 is etched H / 2 in the positive and negative directions of the y axis, and the width of the obtained polygonal cavity 11 in the y axis direction is 2H, making the cavity larger. In order to avoid the above problem, an etched through hole 3 (such as Figure 6 As shown), specifically, it can be between adjacent first interdigitated electrodes 42, or, between adjacent second interdigitated electrodes 44, the width, length and number of the etched through holes 3 can be set as needed, and the length of the etched through holes 3 is less than or equal to the length of the first interdigitated electrode 42 or the second interdigitated electrode 44, which can greatly reduce the area of ​​the cavity region.

[0063] In a feasible embodiment, the distance between the center line of the adjacent first interdigital electrodes 42 and the center line of the second interdigital electrodes 44 is greater than 2 micrometers; the metallization rate of the interdigital electrode structure 4 is greater than or equal to 5% and less than or equal to 40%.

[0064] In a feasible embodiment, the material of the piezoelectric film layer 2 is lithium niobate or lithium tantalate.

[0065] In a feasible embodiment, the crystal cut of the piezoelectric film layer 2 is a Z-cut, or a YXθ-cut, wherein θ satisfies 80°≤θ≤180°.

[0066] In a feasible embodiment, the thickness of the piezoelectric film layer 2 is greater than or equal to 100 nanometers and less than or equal to 900 nanometers.

[0067] See also Figure 4 and Figure 7 The interdigital electrodes of the interdigital transducer (including the first interdigital electrode 42 and the second interdigital electrode 44) can be parallel or perpendicular to the silicon <110> Crystal direction.

[0068] Example 2

[0069] See also Figure 8 and Fig. 9 , Figure 8 It is a schematic diagram of a process for preparing an acoustic resonator provided in an embodiment of the present application; Fig. 9 1 is a schematic diagram of a process for preparing an acoustic resonator provided in an embodiment of the present application. The method for preparing the above-mentioned acoustic resonator comprises:

[0070] S801: Provide a piezoelectric structure; the piezoelectric structure includes a stacked support substrate 1 and a piezoelectric film layer 2; the support substrate 1 is a {111} single crystal silicon substrate.

[0071] See also Fig. 9 The piezoelectric structure can be specifically as follows Fig. 9 The structure shown in Figure (a) in the figure, optionally, the method for preparing the piezoelectric structure can be prepared by ion implantation and annealing stripping process, or directly bonding the piezoelectric wafer on the supporting substrate 1, and then thinning the piezoelectric wafer to obtain; optionally, the above-mentioned dielectric layer 5 is provided between the supporting substrate 1 and the piezoelectric film layer 2, and finally the following can be prepared Figure 5 The device structure shown.

[0072] S803: The piezoelectric structure is etched from the surface of the piezoelectric film layer 2 to form a plurality of etched through holes 3 in the piezoelectric structure. Fig. 9 The structure shown in Figure (b).

[0073] In this embodiment, the distribution of the plurality of etched through holes 3 can be seen in detail in the above embodiment.

[0074] S805: Prepare an interdigitated electrode structure 4 on the piezoelectric film layer 2 to obtain Fig. 9 The structure shown in Figure (c).

[0075] S807 : Anisotropically etching the support substrate 1 by using a wet etching process to form a polygonal cavity 11 in the support substrate 1 ; the polygonal cavity 11 is connected to the plurality of etched through holes 3 .

[0076] In order to prevent the interdigital electrode structure 4 and the piezoelectric film layer 2 from being affected during the etching process, before step S807, the method further includes: preparing a dielectric layer 5 on the interdigital electrode structure 4 to obtain a dielectric layer 5 as shown in FIG. Fig. 9The structure shown in Figure (d).

[0077] Optionally, the specific implementation of step S807 may include: further extending the etching of the plurality of etched through holes 3 until a preset depth position is reached, and the following may be obtained: Fig. 9 The structure shown in Figure (e) is then anisotropically etched on the support substrate 1 using a wet etching process, so that a Fig. 9 The polygonal cavity 11 shown in the middle figure (f) is a {111} single crystal silicon substrate. Therefore, during the etching process, the upper and lower surfaces etched are all {111} crystal planes, and the side surfaces are silicon <110> The etching rate of the {111} crystal plane is lower than that of silicon <110> The etching rate of crystal direction etching forms anisotropic etching, and the height of the polygonal cavity 11 formed is the length of the etched through hole 3 of the above-mentioned extended etching. The above method can achieve precise etching of the size of the polygonal cavity 11, thereby improving the electrical and mechanical properties of the device.

[0078] Subsequently, it can be selected whether to remove the dielectric layer 5 as required. If the dielectric layer 5 is removed, the following can be obtained: Fig. 9 The structure shown in Figure (g).

[0079] Optionally, KOH or TMAH (tetramethylammonium hydroxide) solution can be used for wet etching. Since silicon has strong anisotropy in wet etching and the reaction rate of silicon {111} crystal plane is extremely low, silicon is difficult to be etched in the thickness direction. The thickness of the suspended silicon thin film layer obtained is determined by the etching depth in step S803. In the horizontal direction, Figure 4 The hexagonal boundary is shown.

[0080] Specifically, other parameters for preparing the acoustic resonator can be found in the above description and will not be repeated here.

[0081] Since the commonly used etching method is isotropic etching, if it is used to prepare the acoustic resonator of the present application, the area of ​​the suspended region will be difficult to control, which will lead to poor mechanical stability and poor heat dissipation of the device. However, the present application can accurately control the size of the etched cavity through this anisotropic etching method, and the etching edge is smoother, thereby effectively improving the stability and heat dissipation of the acoustic resonator, and the preparation process is simple, which effectively improves the production and processing efficiency and the consistency of product quality.

[0082] Example 3

[0083] See also Fig.10, which shows the simulated admittance response diagram of two acoustic resonators provided in the embodiments of the present application. An acoustic resonator 1 is provided, which is a first-order Lamb wave resonator of a double-layer composite film, the supporting substrate 1 is 200nm Si{111}, the piezoelectric film layer 2 is 400nm, YX128° cut lithium niobate; the distance between adjacent interdigital electrodes is 5 microns. An acoustic resonator 2 is also provided, which is a first-order Lamb wave resonator of a three-layer composite film, the supporting substrate 1 is 100nm Si{111}, the piezoelectric film layer 2 is 400nm, YX128° cut lithium niobate, the dielectric layer 5 is 100nm SiO2 located between the supporting substrate 1 and the piezoelectric film layer 2, and the distance between adjacent interdigital electrodes is 5 microns. By simulating and calculating the acoustic resonator 1 and the acoustic resonator 2, it can be obtained as follows Fig.10 The simulated admittance response diagram is shown in Figure 1, where Fig.10 The dotted line in corresponds to acoustic resonator 2, Fig.10 The solid line in the figure corresponds to acoustic resonator 1. Fig.10 It can be seen that both exhibit the characteristics of high frequency, high electromechanical coupling coefficient and high Q value.

[0084] Example 4

[0085] On the other hand, the present application also discloses a filter, which includes at least two of the above-mentioned acoustic resonators; the at least two acoustic resonators are electrically connected in series or in parallel to form the filter, and the frequency of the series acoustic resonator is greater than the frequency of the parallel acoustic resonator.

[0086] Optionally, since the operating frequency of a high-order Lamb wave resonator is inversely proportional to the film thickness, the frequency of a series acoustic resonator is greater than that of a parallel acoustic resonator. Therefore, for a high-order Lamb wave filter, two types of acoustic resonators with different film thicknesses are required, such as Fig.11 As shown, the piezoelectric film thickness of the series acoustic resonator and the parallel acoustic resonator is the same, and it may be that only the parallel acoustic resonator contains a silicon film layer of a certain thickness, while the series acoustic resonator does not contain a silicon film layer. Optionally, the thickness of the silicon film layer is greater than zero and less than or equal to 1000 nanometers. Optionally, it may also be that both the series acoustic resonator and the parallel acoustic resonator contain a silicon film layer, but the thickness of the silicon film layer contained in the two is different, and the length of the silicon film layer of the series acoustic resonator is less than the thickness of the silicon film layer of the parallel acoustic resonator.

[0087] The preparation method of the series acoustic resonator and the parallel acoustic resonator is detailed in the above-mentioned embodiment 2. Since the thickness of the silicon thin film layer of the two acoustic resonators is different, it is only necessary to set etched through holes 3 of different lengths during preparation, so that the length of the silicon thin film layer of the series acoustic resonator is smaller than the thickness of the silicon thin film layer of the parallel acoustic resonator.

[0088] See also Fig.12 , which is a top view of a filter provided by an embodiment of the present application. The filter is electrically cascaded by three series acoustic resonators and two parallel acoustic resonators, with a total of three etched through holes 3 ( Fig.12 The white hollowed-out area in the figure) are all located outside the interdigital electrode area (i.e., the area where the first interdigital electrode 42 and the second interdigital electrode 44 are located). By reasonably designing the relationship between the position of the etched through hole 3 and the electrode layout, most of the interdigital electrode areas can be suspended (i.e., located within the white dotted line frame), and most of the non-interdigital electrode areas are in a non-suspended state, thereby improving the electrical properties of the device (such as frequency, electromechanical coupling coefficient, etc.) on the basis of improving the etching accuracy. Therefore, the etched through holes in the present application are not limited to the setting positions mentioned in the above embodiments, as long as the position and shape changes of the etched through holes under the concept of the present application are within the scope of protection of the present application.

[0089] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. An acoustic resonator, characterized in that: include: A supporting substrate, wherein a polygonal cavity is provided in the supporting substrate; The support substrate is a {111} single crystal silicon substrate; The peripheral surface of the polygonal cavity includes silicon <110> Crystal direction; the polygonal cavity is obtained by anisotropically etching the supporting substrate; A piezoelectric film layer located on the supporting substrate, the piezoelectric film layer is close to the polygonal cavity, and the piezoelectric film layer is provided with a plurality of etched through holes, the plurality of etched through holes are connected to the polygonal cavity; the electrical characteristics of the acoustic resonator can be adjusted by adjusting the height of the etched through holes; A silicon thin film layer is disposed between the piezoelectric thin film layer and the polygonal cavity; the thickness of the silicon thin film layer is greater than zero and less than or equal to 1000 nanometers; the thickness of the silicon thin film layer is determined by the etching depth of the etched through hole; the silicon thin film layer is {111} single crystal silicon; and an interdigitated electrode structure located on the piezoelectric film layer; The top and bottom surfaces of the polygonal cavity are {111} crystal planes; There is a preset angle between the peripheral surface of the polygonal cavity and the bottom surface of the polygonal cavity, and the preset angle includes an acute angle.

2. The acoustic resonator according to claim 1, characterized in that The shape of the polygonal cavity projected onto the bottom surface of the piezoelectric film layer is a hexagon.

3. The acoustic resonator according to claim 1, characterized in that Also includes a dielectric layer; The dielectric layer is located between the piezoelectric film layer and the supporting substrate, or the dielectric layer is located on the piezoelectric film layer; The material of the dielectric layer is SiO x , SiN x , any one or more of Al2O3, AlN, and SiC.

4. The acoustic resonator according to claim 1, characterized in that The interdigital electrode structure includes a first bus bar, a plurality of first interdigital electrodes connected to the first bus bar, a second bus bar, and a plurality of second interdigital electrodes connected to the second bus bar; A plurality of the first interdigital electrodes and a plurality of the second interdigital electrodes are arranged alternately; The plurality of etched through holes are distributed in the region between the first interdigital electrodes and the second bus bar, and in the region between the second interdigital electrodes and the first bus bar; or, the plurality of etched through holes are distributed in the region between adjacent interdigital electrodes.

5. The acoustic resonator according to claim 4, characterized in that The distance between the center line of the adjacent first interdigital electrodes and the center line of the adjacent second interdigital electrodes is greater than 2 micrometers; The metallization rate of the interdigital electrode structure is greater than or equal to 5% and less than or equal to 40%.

6. The acoustic resonator according to claim 1, characterized in that The material of the piezoelectric film layer is lithium niobate or lithium tantalate.

7. The acoustic resonator according to claim 6, characterized in that The crystal cut of the piezoelectric film layer is a Z cut or a YXθ cut, and θ satisfies 80°≤θ≤180°.

8. The acoustic resonator according to claim 7, characterized in that The thickness of the piezoelectric film layer is greater than or equal to 100 nanometers and less than or equal to 900 nanometers.

9. A method for preparing the acoustic resonator according to any one of claims 1 to 8, characterized in that: include: Providing a piezoelectric structure; The piezoelectric structure includes a stacked support substrate and a piezoelectric film layer; The support substrate is a {111} single crystal silicon substrate; Performing front etching on the piezoelectric structure from the surface of the piezoelectric film layer to form a plurality of etched through holes in the piezoelectric structure; preparing an interdigitated electrode structure on the piezoelectric film layer; Anisotropically etching the support substrate using a wet etching process to form a polygonal cavity in the support substrate; The polygonal cavity is connected to a plurality of the etched through holes; a silicon thin film layer is formed between the piezoelectric film layer and the polygonal cavity by controlling the depth of the etched through holes; the thickness of the silicon thin film layer is greater than zero and less than or equal to 1000 nanometers; the thickness of the silicon thin film layer is determined by the etching depth of the etched through holes; the silicon thin film layer is {111} single crystal silicon; the top and bottom surfaces of the polygonal cavity are {111} crystal planes; a preset angle exists between the peripheral surface of the polygonal cavity and the bottom surface of the polygonal cavity, and the preset angle includes an acute angle.

10. The method according to claim 9, characterized in that Before anisotropically etching the support substrate using a wet etching process to form a polygonal cavity in the support substrate, the method further includes: A dielectric layer is prepared on the interdigital electrode structure.

11. The method according to claim 9, characterized in that A dielectric layer is provided between the supporting substrate and the piezoelectric film layer.

12. A filter, characterized in that: The filter comprises at least two acoustic resonators as described in any one of claims 1 to 8; the at least two acoustic resonators are electrically connected in series or in parallel to form the filter, and the frequency of the series acoustic resonator is greater than the frequency of the parallel acoustic resonator.

Images