Anti-surge intelligent power module and variable frequency device

Abstract

The application provides an intelligent power module with good surge resistance effect, which comprises a metal ceramic substrate, external pins and a high-voltage integrated module formed on the metal ceramic substrate, wherein the high-voltage integrated module comprises a first inverter circuit, a second inverter circuit, a PFC circuit, a rectifier circuit and an anti-surge circuit which are electrically connected with each other; the anti-surge circuit comprises a patch current-limiting resistor, a patch voltage-dependent resistor, a bidirectional diode and a high-frequency filter capacitor, the first end of the high-frequency filter capacitor is connected with the first end of the voltage-dependent resistor and the patch current-limiting resistor, the second end of the patch current-limiting resistor is connected with the first end of the bidirectional diode and the rectifier circuit, and the second end of the high-frequency filter capacitor is connected with the second end of the voltage-dependent resistor, the second end of the bidirectional diode TVS and the rectifier circuit; the intelligent power module is internally designed with an anti-surge protection circuit, so that the product is prevented from being burnt due to the untimely protection of the peripheral mainboard, the reliability of the product is ensured, and the loss is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor circuit application technology, and in particular to a surge-resistant intelligent power module and frequency converter. Background Technology

[0002] Intelligent Power Modules (IPMs) are power drive products that combine power electronics and integrated circuit technology. They possess the advantages of high current, low saturation voltage, and high withstand voltage of GTRs (High-Power Transistors), and the advantages of high input impedance, high switching frequency, and low drive power of MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). Furthermore, IPMs integrate logic, control, detection, and protection circuits, making them easy to use. They not only reduce system size and development time but also enhance system reliability, leading to their increasing widespread application in consumer electronics, automotive, military, and aerospace fields.

[0003] However, based on current market failure data for smart power modules, power device failures mainly fall into two categories: overheating and overvoltage burnout. Upon opening the packages of products failing due to overvoltage, some chips exhibited obvious overvoltage breakdown morphology (breakdown at the withstand voltage ring). Since power modules are high-voltage devices, they are typically connected directly to the mains power after passing through an EMI circuit. If struck by lightning or experiencing grid instability, these devices are prone to overvoltage breakdown, and even surge protection designs on the motherboard may not provide timely protection.

[0004] Therefore, a surge-resistant intelligent power module is needed to solve the above problems. Summary of the Invention

[0005] To address the shortcomings of the aforementioned related technologies, this invention proposes a surge-resistant intelligent power module and frequency converter.

[0006] To address the aforementioned technical problems, this invention provides a surge-resistant smart power module, comprising a metal-ceramic substrate, external pins disposed around the periphery of the metal-ceramic substrate, and a high-voltage integrated module formed on the metal-ceramic substrate. The high-voltage integrated module includes a first inverter circuit, a second inverter circuit, a PFC circuit, a rectifier circuit, and a surge-resistant circuit, all electrically connected to each other. The rectifier circuit includes a first rectifier diode D1, a second rectifier diode D2, a third rectifier diode D3, and a fourth rectifier diode D4. The positive terminal of the first rectifier diode D1 is connected to the negative terminal of the fourth rectifier diode D4, and the negative terminal of the first rectifier diode D1 is connected to the negative terminal of the second rectifier diode D2. The positive terminal of D2 is connected to the negative terminal of the third rectifier D3, and the positive terminal of the third rectifier D3 is connected to the positive terminal of the fourth rectifier D4. The surge protection circuit includes a surface-mount current-limiting resistor, a surface-mount varistor, a bidirectional diode, and a high-frequency filter capacitor. The first terminal of the high-frequency filter capacitor is connected to the first terminals of the varistor and the surface-mount current-limiting resistor. The second terminal of the surface-mount current-limiting resistor is connected to the first terminal of the bidirectional diode, the positive terminal of the first rectifier D1, and the negative terminal of the fourth rectifier D4. The second terminal of the high-frequency filter capacitor is connected to the second terminal of the varistor, the second terminal of the bidirectional diode TVS, the positive terminal of the second rectifier D2, and the negative terminal of the third rectifier D3.

[0007] Preferably, the first inverter circuit includes a first control chip, a first U-phase control module, a first V-phase control module, a first W-phase control module, a first power supply module, a first fault detection module, a first bootstrap circuit, a first inverter module, and a first filter unit. The first terminal of the first power supply module is connected to the external pin VDD terminal. The second terminal of the first power supply module is simultaneously connected to the first terminal of the first U-phase control module, the first terminal of the first V-phase control module, the first terminal of the first W-phase control module, and the first terminal of the first fault detection module. The second terminals of the first U-phase control module, the first V-phase control module, and the first W-phase control module are simultaneously connected to the first bootstrap circuit. The third terminals of the first U-phase control module, the first V-phase control module, and the first W-phase control module are simultaneously connected to the second terminal of the first fault detection module. The third terminal of the first fault detection module is connected to the first control chip.

[0008] Preferably, the first bootstrap circuit includes a first high-voltage DMOS transistor, a second high-voltage DMOS transistor, and a third high-voltage DMOS transistor. The second terminal of the first U-phase control module is connected to the first terminal of the first high-voltage DMOS transistor, the second terminal of the first V-phase control module is connected to the first terminal of the second high-voltage DMOS transistor, and the second terminal of the first W-phase control module is connected to the first terminal of the third high-voltage DMOS transistor. The first filtering unit includes a first filtering capacitor connected to the second terminal of the first high-voltage DMOS transistor, a second filtering capacitor connected to the second terminal of the second high-voltage DMOS transistor, a third filtering capacitor connected to the second terminal of the third high-voltage DMOS transistor, and a fourth filtering capacitor connected to the first inverter module.

[0009] Preferably, the first inverter module includes a first bridge arm unit, a second bridge arm unit, and a third bridge arm unit. The first bridge arm unit includes two NMOS transistors connected in series: a first NMOS transistor and a second NMOS transistor. The second bridge arm unit includes two NMOS transistors connected in series: a third NMOS transistor and a fourth NMOS transistor. The third bridge arm unit includes two NMOS transistors connected in series: a fifth NMOS transistor and a sixth NMOS transistor. The drain of the first NMOS transistor is connected to an external high-voltage input terminal P. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor. The source of the second NMOS transistor is connected to the external pin UN. The gates of the first NMOS transistor and the second NMOS transistor are connected to the first NMOS transistor. A control chip is connected; the drain of the third NMOS transistor is connected to the external high-voltage input terminal P, the source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor, the source of the fourth NMOS transistor is connected to the external pin VN, and the gates of the third and fourth NMOS transistors are connected to the first control chip; the drain of the fifth NMOS transistor is connected to the external high-voltage input terminal P, the source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor, the source of the sixth NMOS transistor is connected to the external pin WN, and the gates of the fifth and sixth NMOS transistors are connected to the first control chip.

[0010] Preferably, the second inverter circuit includes a second control chip, a second U-phase control module, a second V-phase control module, a second W-phase control module, a second power supply module, a second fault detection module, a second bootstrap circuit, a second inverter module, and a second filter unit. The first terminal of the second power supply module is connected to the external pin VDD terminal. The second terminal of the second power supply module is simultaneously connected to the first terminals of the second U-phase control module, the second V-phase control module, the second W-phase control module, and the second fault detection module. The second terminals of the second U-phase control module, the second V-phase control module, and the second W-phase control module are simultaneously connected to the second bootstrap circuit. The third terminals of the second U-phase control module, the second V-phase control module, and the second W-phase control module are simultaneously connected to the second terminal of the second fault detection module. The third terminal of the second fault detection module is connected to the second control chip.

[0011] Preferably, the second bootstrap circuit includes a fourth high-voltage DMOS transistor, a fifth high-voltage DMOS transistor, and a sixth high-voltage DMOS transistor. The second terminal of the second U-phase control module is connected to the first terminal of the fourth high-voltage DMOS transistor, the second terminal of the second V-phase control module is connected to the first terminal of the fifth high-voltage DMOS transistor, and the second terminal of the second W-phase control module is connected to the first terminal of the sixth high-voltage DMOS transistor. The second filter unit includes a fifth filter capacitor connected to the second terminal of the fourth high-voltage DMOS transistor, a sixth filter capacitor connected to the second terminal of the fifth high-voltage DMOS transistor, a seventh filter capacitor connected to the second terminal of the sixth high-voltage DMOS transistor, and an eighth filter capacitor connected to the second inverter module.

[0012] Preferably, the second inverter module includes a fourth bridge arm unit, a fifth bridge arm unit, and a sixth bridge arm unit. The fourth bridge arm unit includes two NMOS transistors connected in series: a seventh NMOS transistor and an eighth NMOS transistor. The fifth bridge arm unit includes two NMOS transistors connected in series: a ninth NMOS transistor and a tenth NMOS transistor. The sixth bridge arm unit includes two NMOS transistors connected in series: an eleventh NMOS transistor and a twelfth NMOS transistor. The drain of the seventh NMOS transistor is connected to an external high-voltage input terminal P. The source of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor. The source of the eighth NMOS transistor is connected to the external pin UN. The gates of the seventh and eighth NMOS transistors are connected to the second control... The control chip is connected as follows: the drain of the ninth NMOS transistor is connected to the external high-voltage input terminal P, the source of the ninth NMOS transistor is connected to the drain of the tenth NMOS transistor, the source of the tenth NMOS transistor is connected to the external pin VN, and the gates of the ninth and tenth NMOS transistors are connected to the second control chip; the drain of the eleventh NMOS transistor is connected to the external high-voltage input terminal P, the source of the eleventh NMOS transistor is connected to the drain of the twelfth NMOS transistor, the source of the twelfth NMOS transistor is connected to the external pin WN, and the gates of the eleventh and twelfth NMOS transistors are connected to the second control chip.

[0013] Preferably, the PFC circuit includes a third control chip, a thirteenth NMOS transistor, a fifth rectifier transistor, and a ninth filter capacitor. The drain of the thirteenth NMOS transistor is connected to the positive terminal of the fifth rectifier transistor, the source of the thirteenth NMOS transistor is connected to the third control chip, the gate of the thirteenth NMOS transistor is connected to the first terminal of the ninth filter capacitor, and the second terminal of the ninth filter capacitor is connected to the negative terminal of the fifth rectifier transistor.

[0014] The present invention also provides a frequency converter, which includes a power grid module, a main board module, a surge-resistant intelligent power module as described in any of the above embodiments, and a load module connected in sequence, wherein the main board module is provided with an EMI surge protection circuit.

[0015] Preferably, the EMI surge protection circuit includes a fuse, a first gas discharge tube, a second gas discharge tube, a second varistor, a first inductor, a second inductor, a film capacitor, a first suppression capacitor, and a second suppression capacitor. The first end of the fuse is connected to the external pin AC(I) terminal. The second end of the fuse is connected to the first end of the first inductor and the first end of the first gas discharge tube. The second end of the first gas discharge tube is connected to the first end of the second gas discharge tube. The second end of the second gas discharge tube is connected to the external pin AC(N) terminal and the first end of the second inductor. The second end of the first inductor is connected to the first end of the second varistor, the first end of the film capacitor, and the first end of the first suppression capacitor. The second end of the second inductor is connected to the second end of the second varistor, the second end of the film capacitor, and the second end of the second suppression capacitor. The second end of the first suppression capacitor is connected to the first end of the second suppression capacitor.

[0016] Compared with related technologies, the present invention includes a metal-ceramic substrate, external pins, and a high-voltage integrated module formed on the metal-ceramic substrate. The high-voltage integrated module includes a first inverter circuit, a second inverter circuit, a PFC circuit, a rectifier circuit, and a surge protection circuit that are electrically connected to each other. The surge protection circuit includes a surface-mount current-limiting resistor, a surface-mount varistor, a bidirectional diode, and a high-frequency filter capacitor. The first terminal of the high-frequency filter capacitor is connected to the first terminals of the varistor and the surface-mount current-limiting resistor. The second terminal of the surface-mount current-limiting resistor is connected to the first terminal of the bidirectional diode and the rectifier circuit. The second terminal of the high-frequency filter capacitor is connected to the second terminal of the varistor, the second terminal of the bidirectional diode (TVS), and the rectifier circuit. By designing a surge protection circuit inside the intelligent power module, the overvoltage impact resistance and anti-interference capability of the intelligent power module body are enhanced, effectively preventing product burnout due to untimely protection of the external motherboard. This improves the product's service life, ensures product reliability, and reduces maintenance costs. Furthermore, designing a surge protection circuit inside the intelligent power module can appropriately simplify the external circuit design and improve production efficiency. Attached Figure Description

[0017] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:

[0018] Figure 1 This is a schematic diagram of the surge-resistant intelligent power module of the present invention;

[0019] Figure 2 This is a circuit diagram of the high-voltage integrated module of the present invention;

[0020] Figure 3 This is a schematic diagram of the structure of the frequency converter device of the present invention;

[0021] Figure 4 This is a circuit diagram of the EMI surge protection circuit of the present invention. Detailed Implementation

[0022] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0023] The specific embodiments and examples described herein are specific implementations of the present invention, used to illustrate the concept of the invention, and are illustrative and exemplary, and should not be construed as limiting the implementation methods or scope of the present invention. In addition to the embodiments described herein, those skilled in the art can employ other obvious technical solutions based on the content disclosed in the claims and specification of this application. These technical solutions include those that make any obvious substitutions and modifications to the embodiments described herein, all of which are within the protection scope of the present invention.

[0024] Please refer to Figure 1-2 As shown, the present invention provides a surge-resistant smart power module 705, including a metal-ceramic substrate 1000, a high-voltage integrated module 2000 formed on the metal-ceramic substrate 1000, and external pins 3000 disposed on the periphery of the metal-ceramic substrate 1000.

[0025] Specifically, the high-voltage integrated module 2000 includes a first inverter circuit 100, a second inverter circuit 300, a PFC circuit 800, a rectifier circuit 500, and a surge protection circuit 600, all electrically connected to each other. The rectifier circuit 400 includes a first rectifier diode D1, a second rectifier diode D2, a third rectifier diode D3, and a fourth rectifier diode D4. The positive terminal of the first rectifier diode D1 is connected to the negative terminal of the fourth rectifier diode D4, the negative terminal of the first rectifier diode D1 is connected to the negative terminal of the second rectifier diode D2, the positive terminal of the second rectifier diode D2 is connected to the negative terminal of the third rectifier diode D3, and the positive terminal of the third rectifier diode D3 is connected to the positive terminal of the fourth rectifier diode D4. The surge protection circuit 600 includes a surface-mount current-limiting resistor 601, a surface-mount varistor 602, a bidirectional diode 603, and a high-frequency filter capacitor 604. The first terminal of the high-frequency filter capacitor 604 is connected to the first terminals of the varistor 602 and the surface-mount current-limiting resistor 601. The second terminal of the surface-mount current-limiting resistor 601 is connected to the first terminal of the bidirectional diode 603, the positive terminal of the first rectifier D1, and the negative terminal of the fourth rectifier D4. The second terminal of the high-frequency filter capacitor 604 is connected to the second terminal of the varistor 602, the second terminal of the bidirectional diode 603, the positive terminal of the second rectifier D2, and the negative terminal of the third rectifier D3.

[0026] It should be noted that in the structural design of the surge protection circuit 600, the surface-mount current-limiting resistor 601 mainly prevents the bidirectional diode 603 from conducting before the damage occurs, while the varistor 602 has not yet had time to provide protection. The surface-mount varistor 602 is used for transient overvoltage protection such as surges. The transient voltage of the varistor 602 suppresses the bidirectional diode 603. When its voltage exceeds the breakdown threshold, it directly shunts the excessive current, thus suppressing the excessively high voltage exceeding its breakdown voltage. When the overvoltage disappears, the bidirectional diode 603 automatically resets. The high-frequency filter capacitor 604 is used to absorb peak voltages in the circuit and improve surge protection capability. Therefore, by designing an anti-surge circuit 600 inside the intelligent power module, the overvoltage impact resistance and anti-interference capability of the intelligent power module body can be enhanced, effectively preventing product burnout due to untimely protection of the external motherboard, thereby extending the product's service life, ensuring product reliability, and reducing maintenance costs. Furthermore, designing an anti-surge circuit 600 inside the intelligent power module can appropriately simplify the external circuit design and improve production efficiency.

[0027] In this embodiment, the first inverter circuit includes a first control chip 56, a first U-phase control module 11, a first V-phase control module 12, a first W-phase control module 13, a first power supply module 14, a first fault detection module 15, a first bootstrap circuit 16, a first inverter module 17, and a first filter unit 18. The first terminal of the first power supply module 17 is connected to the external pin VDD terminal. The second terminal of the first power supply module 14 is simultaneously connected to the first terminals of the first U-phase control module 11, the first V-phase control module 12, the first W-phase control module 13, and the first terminal of the first fault detection module 17. The second terminals of the first U-phase control module 11, the first V-phase control module 12, and the first W-phase control module 13 are simultaneously connected to the first bootstrap circuit 16. The third terminals of the first U-phase control module 11, the first V-phase control module 12, and the first W-phase control module 13 are simultaneously connected to the second terminal of the first fault detection module 15. The third terminal of the first fault detection module 15 is connected to the first control chip 56.

[0028] Furthermore, the first bootstrap circuit 16 includes a first high-voltage DMOS transistor 003, a second high-voltage DMOS transistor 004, and a third high-voltage DMOS transistor 005. The second terminal of the first U-phase control module 11 is connected to the first terminal of the first high-voltage DMOS transistor 003, the second terminal of the first V-phase control module 12 is connected to the first terminal of the second high-voltage DMOS transistor 004, and the second terminal of the first W-phase control module 13 is connected to the first terminal of the third high-voltage DMOS transistor 005. The first filter unit 18 includes a first filter capacitor 20 connected to the second terminal of the first high-voltage DMOS transistor 003, a second filter capacitor 21 connected to the second terminal of the second high-voltage DMOS transistor, a third filter capacitor 22 connected to the second terminal of the third high-voltage DMOS transistor 005, and a fourth filter capacitor 23 connected to the first inverter module 17. The first filter capacitor 20, the second filter capacitor 21, and the third filter capacitor 22 are used to prevent damage to the first bootstrap circuit 16, and the fourth filter capacitor 23 is used to prevent ITRIIP triggering caused by high-frequency switching oscillations.

[0029] Furthermore, the first inverter module 17 includes a first bridge arm unit, a second bridge arm unit, and a third bridge arm unit. The first bridge arm unit includes two NMOS transistors 200 and 203 connected in series. The second bridge arm unit includes two NMOS transistors 201 and 204 connected in series. The third bridge arm unit includes two NMOS transistors 202 and 205 connected in series. The drain of the first NMOS transistor 200 is connected to the external high-voltage input terminal P, the source of the first NMOS transistor 200 is connected to the drain of the second NMOS transistor 203, the source of the second NMOS transistor 203 is connected to the external pin UN, and the gates of the first NMOS transistor 200 and the second NMOS transistor 203 are connected to the first... The control chip 56 is connected; the drain of the third NMOS transistor 201 is connected to the external high-voltage input terminal P, the source of the third NMOS transistor 201 is connected to the drain of the fourth NMOS transistor 204, the source of the fourth NMOS transistor 204 is connected to the external pin VN, and the gates of the third NMOS transistor 201 and the fourth NMOS transistor 204 are connected to the first control chip 56; the drain of the fifth NMOS transistor 202 is connected to the external high-voltage input terminal P, the source of the fifth NMOS transistor 202 is connected to the drain of the sixth NMOS transistor 205, the source of the sixth NMOS transistor 205 is connected to the external pin WN, and the gates of the fifth NMOS transistor 202 and the sixth NMOS transistor 205 are connected to the first control chip 56.

[0030] In this embodiment, the second inverter circuit 300 includes a second control chip 57, a second U-phase control module 31, a second V-phase control module 32, a second W-phase control module 33, a second power supply module 34, a second fault detection module 35, a second bootstrap circuit 36, a second inverter module 37, and a second filter unit 38. The first terminal of the second power supply module 34 is connected to the external pin VDD terminal. The second terminal of the second power supply module 34 is simultaneously connected to the first terminals of the second U-phase control module 31, the second V-phase control module 32, the second W-phase control module 33, and the second fault detection module 35. The second terminals of the second U-phase control module 31, the second V-phase control module 32, and the second W-phase control module 33 are simultaneously connected to the second bootstrap circuit 36. The third terminals of the second U-phase control module 31, the second V-phase control module 32, and the second W-phase control module 33 are simultaneously connected to the second terminal of the second fault detection module 35. The third terminal of the second fault detection module 35 is connected to the second control chip 57.

[0031] Furthermore, the second bootstrap circuit includes a fourth high-voltage DMOS transistor 007, a fifth high-voltage DMOS transistor 008, and a sixth high-voltage DMOS transistor 009. The second terminal of the second U-phase control module 31 is connected to the first terminal of the fourth high-voltage DMOS transistor 007, the second terminal of the second V-phase control module 32 is connected to the first terminal of the fifth high-voltage DMOS transistor 008, and the second terminal of the second W-phase control module 33 is connected to the first terminal of the sixth high-voltage DMOS transistor 009. The second filter unit 38 includes a fifth filter capacitor 24 connected to the second terminal of the fourth high-voltage DMOS transistor, a sixth filter capacitor 25 connected to the second terminal of the fifth high-voltage DMOS transistor 008, a seventh filter capacitor 26 connected to the second terminal of the sixth high-voltage DMOS transistor 009, and an eighth filter capacitor 27 connected to the second inverter module 37. The fifth filter capacitor 24, the sixth filter capacitor 25, and the eighth filter capacitor 26 are used to prevent damage to the second bootstrap circuit 36, and the eighth filter capacitor 27 is used to prevent ITRIP triggering caused by high-frequency switching oscillations.

[0032] More preferably, the second inverter module 37 includes a fourth bridge arm unit, a fifth bridge arm unit, and a sixth bridge arm unit. The fourth bridge arm unit includes two series-connected seventh NMOS transistors 400 and eighth NMOS transistors 403. The fifth bridge arm unit includes two series-connected ninth NMOS transistors 401 and tenth NMOS transistors 404. The sixth bridge arm unit includes two series-connected eleventh NMOS transistors 402 and twelfth NMOS transistors 405. The drain of the seventh NMOS transistor 400 is connected to the external high-voltage input terminal P, the source of the seventh NMOS transistor 400 is connected to the drain of the eighth NMOS transistor 403, the source of the eighth NMOS transistor 403 is connected to the external pin UN, and the gates of the seventh NMOS transistor 400 and the eighth NMOS transistor 403 are connected to the second control chip. The chip 57 is connected; the drain of the ninth NMOS transistor 401 is connected to the external high-voltage input terminal P, the source of the ninth NMOS transistor 401 is connected to the drain of the tenth NMOS transistor 404, the source of the tenth NMOS transistor 404 is connected to the external pin VN, and the gates of the ninth NMOS transistor 401 and the tenth NMOS transistor 404 are connected to the second control chip 57; the drain of the eleventh NMOS transistor 402 is connected to the external high-voltage input terminal P, the source of the eleventh NMOS transistor 402 is connected to the drain of the twelfth NMOS transistor 405, the source of the twelfth NMOS transistor 405 is connected to the external pin WN, and the gates of the eleventh NMOS transistor 402 and the twelfth NMOS transistor 403 are connected to the second control chip 57.

[0033] In this embodiment, the PFC circuit 800 includes a third control chip 58, a thirteenth NMOS transistor 503, a fifth rectifier transistor 501, and a ninth filter capacitor 502. The drain of the thirteenth NMOS transistor 503 is connected to the positive terminal of the fifth rectifier transistor 501, the source of the thirteenth NMOS transistor 503 is connected to the third control chip 58, the gate of the thirteenth NMOS transistor 503 is connected to the first terminal of the ninth filter capacitor 502, and the second terminal of the ninth filter capacitor 502 is connected to the negative terminal of the fifth rectifier transistor 501. The ninth filter capacitor 502 is used to prevent ITRIIP triggering caused by high-frequency switching oscillations.

[0034] Please refer to Figure 3-4 As shown, the present invention provides a frequency converter 10000, which includes a power grid module 700, a main board module 701, a smart power module 705 with good surge protection, and a load module 701 connected in sequence. The main board module is provided with an EMI surge protection circuit 706.

[0035] It is worth mentioning that the EMI surge protection circuit 706 includes a fuse F, a first gas discharge tube G1, a second gas discharge tube G2, a second varistor VR, a first inductor L1, a second inductor L2, a thin-film capacitor CX, a first suppression capacitor CY1, and a second suppression capacitor CY2. The first end of the fuse F is connected to the external pin AC(I) terminal, the second end of the fuse F is connected to the first end of the first inductor L1 and the first end of the first gas discharge tube G1, the second end of the first gas discharge tube G1 is connected to the first end of the second gas discharge tube G2, and the second end of the second gas discharge tube G2 is connected to the external pin AC(N) terminal and the first end of the second inductor L2. The first inductor L1 is connected to the second varistor VR, the first film capacitor CX, and the first suppression capacitor CY1. The second inductor L2 is connected to the second varistor VR, the second film capacitor CX, and the second suppression capacitor CY2. The second suppression capacitor CY1 is connected to the first suppression capacitor CY2. The fuse F, the first gas discharge tube G1, and the second gas discharge tube G2 are mainly used to suppress high-voltage common-mode surge pulses, and also have the ability to suppress high-voltage differential-mode surge pulses. The second varistor VR is mainly used to suppress high-voltage differential-mode surge pulses. The first inductor L1 and the second inductor L2 suppress differential-mode signals. After suppression by the first gas discharge tube G1, the second gas discharge tube G2, and the second varistor VR, the amplitude and energy of both common-mode and differential-mode surge pulses are significantly reduced. The breakdown voltages of the first gas discharge tube G1 and the second gas discharge tube G2 can be selected from 1000Vp to 3000Vp. The varistor voltage of the second varistor VR is generally taken as 1.7 times the maximum value of the power frequency voltage. The thin film capacitor CX suppresses differential mode interference, and the first suppression capacitor CY1 and the second suppression capacitor CY2 suppress common mode interference.

[0036] Compared with related technologies, the present invention includes a metal-ceramic substrate, external pins, and a high-voltage integrated module formed on the metal-ceramic substrate. The high-voltage integrated module includes a first inverter circuit, a second inverter circuit, a PFC circuit, a rectifier circuit, and a surge protection circuit that are electrically connected to each other. The surge protection circuit includes a surface-mount current-limiting resistor, a surface-mount varistor, a bidirectional diode, and a high-frequency filter capacitor. The first terminal of the high-frequency filter capacitor is connected to the first terminals of the varistor and the surface-mount current-limiting resistor. The second terminal of the surface-mount current-limiting resistor is connected to the first terminal of the bidirectional diode and the rectifier circuit. The second terminal of the high-frequency filter capacitor is connected to the second terminal of the varistor, the second terminal of the bidirectional diode (TVS), and the rectifier circuit. By designing a surge protection circuit inside the intelligent power module, the overvoltage impact resistance and anti-interference capability of the intelligent power module body are enhanced, effectively preventing product burnout due to untimely protection of the external motherboard. This improves the product's service life, ensures product reliability, and reduces maintenance costs. Furthermore, designing a surge protection circuit inside the intelligent power module can appropriately simplify the external circuit design and improve production efficiency.

[0037] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any alterations, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of the claims of the present invention.

Claims

1. A surge-resistant smart power module, comprising a metal-ceramic substrate, external pins disposed around the periphery of the metal-ceramic substrate, and a high-voltage integrated module formed on the metal-ceramic substrate, characterized in that, The high-voltage integrated module includes a first inverter circuit, a second inverter circuit, a PFC circuit, a rectifier circuit, and a surge protection circuit that are electrically connected to each other. The rectifier circuit includes a first rectifier diode D1, a second rectifier diode D2, a third rectifier diode D3, and a fourth rectifier diode D4. The positive terminal of the first rectifier diode D1 is connected to the negative terminal of the fourth rectifier diode D4, the negative terminal of the first rectifier diode D1 is connected to the negative terminal of the second rectifier diode D2, the positive terminal of the second rectifier diode D2 is connected to the negative terminal of the third rectifier diode D3, and the positive terminal of the third rectifier diode D3 is connected to the fourth rectifier diode D4. The positive terminal is connected to the voltage regulator; the surge protection circuit includes a surface-mount current-limiting resistor, a surface-mount varistor, a bidirectional diode, and a high-frequency filter capacitor. The first terminal of the high-frequency filter capacitor is connected to the first terminals of the varistor and the surface-mount current-limiting resistor. The second terminal of the surface-mount current-limiting resistor is connected to the first terminal of the bidirectional diode, the positive terminal of the first rectifier D1, and the negative terminal of the fourth rectifier D4. The second terminal of the high-frequency filter capacitor is connected to the second terminal of the varistor, the second terminal of the bidirectional diode TVS, the positive terminal of the second rectifier D2, and the negative terminal of the third rectifier D3. The intelligent power module is connected to an EMI surge protection circuit, which includes a fuse, a first gas discharge tube, a second gas discharge tube, a second varistor, a first inductor, a second inductor, a film capacitor, a first suppression capacitor, and a second suppression capacitor. The first end of the fuse is connected to the external pin AC(I) terminal. The second end of the fuse is connected to the first end of the first inductor and the first end of the first gas discharge tube. The second end of the first gas discharge tube is connected to the first end of the second gas discharge tube. The second end of the second gas discharge tube is connected to the external pin AC(N) terminal and the first end of the second inductor. The second end of the first inductor is connected to the first end of the second varistor, the first end of the film capacitor, and the first end of the first suppression capacitor. The second end of the second inductor is connected to the second end of the second varistor, the second end of the film capacitor, and the second end of the second suppression capacitor. The second end of the first suppression capacitor is connected to the first end of the second suppression capacitor.

2. The surge-resistant intelligent power module as described in claim 1, characterized in that, The first inverter circuit includes a first control chip, a first U-phase control module, a first V-phase control module, a first W-phase control module, a first power supply module, a first fault detection module, a first bootstrap circuit, a first inverter module, and a first filter unit. The first terminal of the first power supply module is connected to the external pin VDD. The second terminal of the first power supply module is simultaneously connected to the first terminals of the first U-phase control module, the first terminals of the first V-phase control module, the first terminals of the first W-phase control module, and the first terminal of the first fault detection module. The second terminals of the first U-phase control module, the first V-phase control module, and the first W-phase control module are simultaneously connected to the first bootstrap circuit. The third terminals of the first U-phase control module, the first V-phase control module, and the first W-phase control module are simultaneously connected to the second terminal of the first fault detection module. The third terminal of the first fault detection module is connected to the first control chip.

3. The surge-resistant intelligent power module as described in claim 2, characterized in that, The first bootstrap circuit includes a first high-voltage DMOS transistor, a second high-voltage DMOS transistor, and a third high-voltage DMOS transistor. The second terminal of the first U-phase control module is connected to the first terminal of the first high-voltage DMOS transistor, the second terminal of the first V-phase control module is connected to the first terminal of the second high-voltage DMOS transistor, and the second terminal of the first W-phase control module is connected to the first terminal of the third high-voltage DMOS transistor. The first filter unit includes a first filter capacitor connected to the second terminal of the first high-voltage DMOS transistor, a second filter capacitor connected to the second terminal of the second high-voltage DMOS transistor, a third filter capacitor connected to the second terminal of the third high-voltage DMOS transistor, and a fourth filter capacitor connected to the first inverter module.

4. The surge-resistant intelligent power module as described in claim 3, characterized in that, The first inverter module includes a first bridge arm unit, a second bridge arm unit, and a third bridge arm unit. The first bridge arm unit includes two NMOS transistors connected in series: a first NMOS transistor and a second NMOS transistor. The second bridge arm unit includes two NMOS transistors connected in series: a third NMOS transistor and a fourth NMOS transistor. The third bridge arm unit includes two NMOS transistors connected in series: a fifth NMOS transistor and a sixth NMOS transistor. The drain of the first NMOS transistor is connected to an external high-voltage input terminal P. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor. The source of the second NMOS transistor is connected to an external pin UN. The gates of the first and second NMOS transistors are connected to the first... The control chip is connected as follows: the drain of the third NMOS transistor is connected to the external high-voltage input terminal P, the source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor, the source of the fourth NMOS transistor is connected to the external pin VN, and the gates of the third and fourth NMOS transistors are connected to the first control chip; the drain of the fifth NMOS transistor is connected to the external high-voltage input terminal P, the source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor, the source of the sixth NMOS transistor is connected to the external pin WN, and the gates of the fifth and sixth NMOS transistors are connected to the first control chip.

5. The surge-resistant intelligent power module as described in claim 1, characterized in that, The second inverter circuit includes a second control chip, a second U-phase control module, a second V-phase control module, a second W-phase control module, a second power supply module, a second fault detection module, a second bootstrap circuit, a second inverter module, and a second filter unit. The first terminal of the second power supply module is connected to the external pin VDD. The second terminal of the second power supply module is simultaneously connected to the first terminals of the second U-phase control module, the second V-phase control module, the second W-phase control module, and the second fault detection module. The second terminals of the second U-phase control module, the second V-phase control module, and the second W-phase control module are simultaneously connected to the second bootstrap circuit. The third terminals of the second U-phase control module, the second V-phase control module, and the second W-phase control module are simultaneously connected to the second terminal of the second fault detection module. The third terminal of the second fault detection module is connected to the second control chip.

6. The surge-resistant intelligent power module as described in claim 5, characterized in that, The second bootstrap circuit includes a fourth high-voltage DMOS transistor, a fifth high-voltage DMOS transistor, and a sixth high-voltage DMOS transistor. The second terminal of the second U-phase control module is connected to the first terminal of the fourth high-voltage DMOS transistor, the second terminal of the second V-phase control module is connected to the first terminal of the fifth high-voltage DMOS transistor, and the second terminal of the second W-phase control module is connected to the first terminal of the sixth high-voltage DMOS transistor. The second filter unit includes a fifth filter capacitor connected to the second terminal of the fourth high-voltage DMOS transistor, a sixth filter capacitor connected to the second terminal of the fifth high-voltage DMOS transistor, a seventh filter capacitor connected to the second terminal of the sixth high-voltage DMOS transistor, and an eighth filter capacitor connected to the second inverter module.

7. The surge-resistant intelligent power module as described in claim 6, characterized in that, The second inverter module includes a fourth bridge arm unit, a fifth bridge arm unit, and a sixth bridge arm unit. The fourth bridge arm unit includes two NMOS transistors connected in series: a seventh NMOS transistor and an eighth NMOS transistor. The fifth bridge arm unit includes two NMOS transistors connected in series: a ninth NMOS transistor and a tenth NMOS transistor. The sixth bridge arm unit includes two NMOS transistors connected in series: an eleventh NMOS transistor and a twelfth NMOS transistor. The drain of the seventh NMOS transistor is connected to the external high-voltage input terminal P. The source of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor. The source of the eighth NMOS transistor is connected to the external pin UN. The gates of the seventh and eighth NMOS transistors are connected to the second control... Chip connections: The drain of the ninth NMOS transistor is connected to the external high-voltage input terminal P; the source of the ninth NMOS transistor is connected to the drain of the tenth NMOS transistor; the source of the tenth NMOS transistor is connected to the external pin VN; and the gates of the ninth and tenth NMOS transistors are connected to the second control chip. The drain of the eleventh NMOS transistor is connected to the external high-voltage input terminal P; the source of the eleventh NMOS transistor is connected to the drain of the twelfth NMOS transistor; the source of the twelfth NMOS transistor is connected to the external pin WN; and the gates of the eleventh and twelfth NMOS transistors are connected to the second control chip.

8. The surge-resistant intelligent power module as described in claim 1, characterized in that, The PFC circuit includes a third control chip, a thirteenth NMOS transistor, a fifth rectifier transistor, and a ninth filter capacitor. The drain of the thirteenth NMOS transistor is connected to the positive terminal of the fifth rectifier transistor, the source of the thirteenth NMOS transistor is connected to the third control chip, the gate of the thirteenth NMOS transistor is connected to the first terminal of the ninth filter capacitor, and the second terminal of the ninth filter capacitor is connected to the negative terminal of the fifth rectifier transistor.

Images